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KEY LIBERO "9.1"
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KEY CAPTURE "9.1.3.4"
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KEY DEFAULT_IMPORT_LOC ""
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KEY DEFAULT_OPEN_LOC ""
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KEY ProjectID "ef446e1c-1d6a-43a8-a14a-ebd5dda7bc29"
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KEY HDLTechnology "VHDL"
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KEY VendorTechnology_Family "ProASIC3L"
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KEY VendorTechnology_Die "IS8X8M2LDP"
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KEY VendorTechnology_Package "fg256"
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KEY ProjectLocation "C:\opt\VHD_Lib\designs\ProjetBlanc-LeonLPP-A3PE3kL"
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KEY SimulationType "VHDL"
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KEY Vendor "Actel"
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KEY ActiveRoot "ahbrom::work"
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LIST REVISIONS
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VALUE="Impl1",NUM=1
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VALUE="Impl2",NUM=2
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CURREV=2
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ENDLIST
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LIST LIBRARIES
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grlib
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synplify
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techmap
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spw
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eth
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opencores
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gaisler
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esa
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fmf
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spansion
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gsi
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lpp
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cypress
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ENDLIST
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LIST LIBRARY_grlib
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ALIAS=grlib
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_synplify
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ALIAS=synplify
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_techmap
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ALIAS=techmap
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_spw
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ALIAS=spw
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_eth
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ALIAS=eth
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_opencores
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ALIAS=opencores
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_gaisler
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ALIAS=gaisler
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_esa
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ALIAS=esa
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_fmf
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ALIAS=fmf
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_spansion
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ALIAS=spansion
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_gsi
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ALIAS=gsi
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_lpp
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ALIAS=lpp
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST LIBRARY_cypress
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ALIAS=cypress
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COMPILE_OPTION=COMPILE
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ENDLIST
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LIST FileManager
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VALUE "<project>\ahbrom.vhd,hdl"
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STATE="utd"
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TIME="1367568565"
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SIZE="8992"
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ENDFILE
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VALUE "<project>\config.vhd,hdl"
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STATE="utd"
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TIME="1367568565"
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SIZE="6294"
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ENDFILE
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VALUE "<project>\leon3mp.vhd,hdl"
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STATE="utd"
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TIME="1367568565"
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SIZE="13693"
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ENDFILE
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ENDLIST
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LIST UsedFile
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ENDLIST
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LIST NewModulesInfo
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ENDLIST
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LIST AssociatedStimulus
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ENDLIST
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LIST Other_Association
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ENDLIST
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LIST SimulationOptions
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UseAutomaticDoFile=true
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IncludeWaveDo=false
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Type=max
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RunTime=1000ns
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Resolution=1ps
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VsimOpt=
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EntityName=testbench
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TopInstanceName=<top>_0
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DoFileName=
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DoFileName2=wave.do
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DoFileParams=
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DisplayDUTWave=false
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LogAllSignals=false
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DumpVCD=false
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VCDFileName=power.vcd
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ENDLIST
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LIST ModelSimLibPath
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UseCustomPath=FALSE
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LibraryPath=
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ENDLIST
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LIST GlobalFlowOptions
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GenerateHDLAfterSynthesis=FALSE
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GenerateHDLAfterPhySynthesis=FALSE
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RunDRCAfterSynthesis=FALSE
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AutoCheckConstraints=TRUE
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UpdateViewDrawIni=TRUE
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UpdateModelSimIni=TRUE
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NoIOMode=FALSE
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GenerateHDLFromSchematic=TRUE
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FlashProInputFile=pdb
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SmartGenCompileReport=T
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ENDLIST
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LIST PhySynthesisOptions
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ENDLIST
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LIST Profiles
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NAME="Synplify AE"
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FUNCTION="Synthesis"
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TOOL="Synplify"
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LOCATION="C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\bin\synplify_pro.exe"
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PARAM=""
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BATCH=0
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EndProfile
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NAME="ModelSim AE"
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FUNCTION="Simulation"
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TOOL="ModelSim"
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LOCATION="C:\Actel\Libero_v9.1\Model\win32acoem\modelsim.exe"
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PARAM=""
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BATCH=0
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EndProfile
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NAME="WFL"
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FUNCTION="Stimulus"
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TOOL="WFL"
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LOCATION="syncad.exe"
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PARAM="-pwflite"
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BATCH=0
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EndProfile
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NAME="FlashPro"
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FUNCTION="Program"
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TOOL="FlashPro"
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LOCATION="C:\Actel\Libero_v9.1\Designer\bin\FlashPro.exe"
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PARAM=""
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BATCH=0
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EndProfile
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ENDLIST
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LIST ProjectState5.1
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ENDLIST
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LIST ExcludePackageForSimulation
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ENDLIST
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LIST ExcludePackageForSynthesis
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ENDLIST
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LIST IncludeModuleForSimulation
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ENDLIST
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LIST CDBOrder
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ENDLIST
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LIST UserCustomizedFileList
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ENDLIST
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LIST OpenedFileList
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DESIGNFLOW:
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ACTIVE_VIEW:0
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ENDLIST
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