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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.lpp_Header.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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use lpp.lpp_amba.all;
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use lpp.lpp_memory.all;
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use lpp.lpp_uart.all;
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use lpp.lpp_matrix.all;
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use lpp.lpp_delay.all;
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use lpp.lpp_fft.all;
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use lpp.fft_components.all;
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use lpp.lpp_ad_conv.all;
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use lpp.iir_filter.all;
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use lpp.general_purpose.all;
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use lpp.Filtercfg.all;
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use lpp.lpp_demux.all;
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use lpp.lpp_top_lfr_pkg.all;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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-------------------------------------------------------------------------------
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ENTITY TB_Header IS
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END TB_Header;
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-------------------------------------------------------------------------------
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ARCHITECTURE tb OF TB_Header IS
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COMPONENT TestModule_ADS7886
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GENERIC (
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freq : INTEGER;
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amplitude : INTEGER;
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impulsion : INTEGER);
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PORT (
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cnv_run : IN STD_LOGIC;
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cnv : IN STD_LOGIC;
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sck : IN STD_LOGIC;
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sdo : OUT STD_LOGIC);
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END COMPONENT;
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-- component ports
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SIGNAL cnv_rstn : STD_LOGIC;
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SIGNAL cnv : STD_LOGIC;
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SIGNAL rstn : STD_LOGIC;
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SIGNAL sck : STD_LOGIC;
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SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL run_cnv : STD_LOGIC;
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-- clock
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SIGNAL Clk : STD_LOGIC := '1';
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SIGNAL cnv_clk : STD_LOGIC := '1';
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-----------------------------------------------------------------------------
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-- FIFOs
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SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
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-- MATRICE SPECTRALE
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SIGNAL SM_FlagError : STD_LOGIC;
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SIGNAL SM_Pong : STD_LOGIC;
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SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
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SIGNAL Dma_acq : STD_LOGIC;
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-- FFT
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SIGNAL FFT_Load : STD_LOGIC;
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SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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-- DEMUX
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SIGNAL DEMU_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL DEMU_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL DEMU_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
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-- ACQ
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SIGNAL sample_val : STD_LOGIC;
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SIGNAL sample : Samples(8-1 DOWNTO 0);
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SIGNAL TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL pong : STD_LOGIC;
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SIGNAL Statu : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL Matrix_Type : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL Matrix_Write : STD_LOGIC;
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SIGNAL Valid : STD_LOGIC;
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SIGNAL dataIN : STD_LOGIC_VECTOR((2*Data_sz)-1 DOWNTO 0);
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SIGNAL emptyIN : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL RenOUT : STD_LOGIC_VECTOR(1 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL AHB_Master_In : AHB_Mst_In_Type;
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SIGNAL AHB_Master_Out : AHB_Mst_Out_Type;
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-----------------------------------------------------------------------------
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SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fifo_empty : STD_LOGIC;
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SIGNAL fifo_ren : STD_LOGIC;
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SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL header_val : STD_LOGIC;
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SIGNAL header_ack : STD_LOGIC;
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SIGNAL ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL ready_matrix_f1 : STD_LOGIC;
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SIGNAL ready_matrix_f2 : STD_LOGIC;
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SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL error_bad_component_error : STD_LOGIC;
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SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f2 : STD_LOGIC;
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SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL status_error_bad_component_error : STD_LOGIC;
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SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
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SIGNAL config_active_interruption_onError : STD_LOGIC;
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SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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BEGIN -- tb
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MODULE_ADS7886 : FOR I IN 0 TO 6 GENERATE
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TestModule_ADS7886_u : TestModule_ADS7886
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GENERIC MAP (
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freq => 24*(I+1),
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amplitude => 30000/(I+1),
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impulsion => 0)
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PORT MAP (
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cnv_run => run_cnv,
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cnv => cnv,
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sck => sck,
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sdo => sdo(I));
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END GENERATE MODULE_ADS7886;
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TestModule_ADS7886_u : TestModule_ADS7886
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GENERIC MAP (
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freq => 0,
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amplitude => 30000,
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impulsion => 1)
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PORT MAP (
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cnv_run => run_cnv,
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cnv => cnv,
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sck => sck,
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sdo => sdo(7));
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-- clock generation
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Clk <= NOT Clk AFTER 20 ns; -- 25 Mhz
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cnv_clk <= NOT cnv_clk AFTER 10173 ps; -- 49.152 MHz
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-- waveform generation
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WaveGen_Proc : PROCESS
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BEGIN
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-- insert signal assignments here
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WAIT UNTIL Clk = '1';
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rstn <= '0';
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cnv_rstn <= '0';
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run_cnv <= '0';
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WAIT UNTIL Clk = '1';
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WAIT UNTIL Clk = '1';
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WAIT UNTIL Clk = '1';
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rstn <= '1';
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cnv_rstn <= '1';
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WAIT UNTIL Clk = '1';
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WAIT UNTIL Clk = '1';
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WAIT UNTIL Clk = '1';
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WAIT UNTIL Clk = '1';
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WAIT UNTIL Clk = '1';
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WAIT UNTIL Clk = '1';
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run_cnv <= '1';
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WAIT;
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END PROCESS WaveGen_Proc;
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-----------------------------------------------------------------------------
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TopACQ : lpp_top_acq
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PORT MAP(run_cnv, cnv,sck, sdo, cnv_clk, rstn, clk, rstn, TopACQ_WenF0, TopACQ_DataF0, TopACQ_WenF1, TopACQ_DataF1, OPEN, OPEN, TopACQ_WenF3, TopACQ_DataF3);
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Bias_Fails <= '0';
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Memf0 : lppFIFOxN
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GENERIC MAP(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
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PORT MAP(rstn, clk, clk, (OTHERS => '0'), TopACQ_WenF0, DEMU_Read(4 DOWNTO 0), TopACQ_DataF0, FifoF0_Data, OPEN, FifoF0_Empty);
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Memf1 : lppFIFOxN
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GENERIC MAP(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
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PORT MAP(rstn, clk, clk, (OTHERS => '0'), TopACQ_WenF1, DEMU_Read(9 DOWNTO 5), TopACQ_DataF1, FifoF1_Data, OPEN, FifoF1_Empty);
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Memf3 : lppFIFOxN
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GENERIC MAP(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
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PORT MAP(rstn, clk, clk, (OTHERS => '0'), TopACQ_WenF3, DEMU_Read(14 DOWNTO 10), TopACQ_DataF3, FifoF3_Data, OPEN, FifoF3_Empty);
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--- DEMUX -------------------------------------------------------------
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DEMU0 : DEMUX
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GENERIC MAP(Data_sz => 16)
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PORT MAP(clk, rstn, FFT_Read, FFT_Load, FifoF0_Empty, FifoF1_Empty, FifoF3_Empty, FifoF0_Data, FifoF1_Data, FifoF3_Data,Matrix_Type ,DEMU_Read, DEMU_Empty, DEMU_Data);
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--- FFT -------------------------------------------------------------
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FFT0 : FFT
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GENERIC MAP(Data_sz => 16, NbData => 256)
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PORT MAP(clk, rstn, DEMU_Empty, DEMU_Data, FifoINT_Full, FFT_Load, FFT_Read, FFT_Write, FFT_ReUse, FFT_Data);
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----- LINK MEMORY -------------------------------------------------------
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MemInt : lppFIFOxN
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GENERIC MAP(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
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PORT MAP(rstn, clk, clk, SM_ReUse, FFT_Write, SM_Read, FFT_Data, FifoINT_Data, FifoINT_Full, OPEN);
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----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
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SM0 : MatriceSpectrale
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GENERIC MAP(Input_SZ => 16, Result_SZ => 32)
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PORT MAP(clk, rstn, FifoINT_Full, FFT_ReUse,Valid,-- FifoOUT_Full,
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FifoINT_Data, Dma_acq, Matrix_Write,SM_FlagError, SM_Pong, SM_Param,
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SM_Write, SM_Read, SM_ReUse, SM_Data);
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Dma_acq <= '1';
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MemOut : APB_FIFO
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GENERIC MAP (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
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PORT MAP (clk, rstn, clk, clk, (OTHERS => '0'), RenOUT, SM_Write, emptyIN, FifoOUT_Full, dataIN, SM_Data, OPEN, OPEN, apbi, apbo(9));
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-----------------------------------------------------------------------------
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HeaderBuilder_1 : HeaderBuilder
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GENERIC MAP (
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Data_sz => Data_sz)
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PORT MAP (
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clkm => clk,
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rstn => rstn,
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pong => SM_Pong,--pong,
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Statu => SM_Param,--Statu,
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Matrix_Type => Matrix_Type, --
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Matrix_Write => Matrix_Write,
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Valid => Valid,
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dataIN => dataIN,
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emptyIN => emptyIN,
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RenOUT => RenOUT,
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dataOUT => fifo_data,
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emptyOUT => fifo_empty,
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RenIN => fifo_ren,
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header => header,
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header_val => header_val,
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header_ack => header_ack);
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-----------------------------------------------------------------------------
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lpp_dma_ip_1 : lpp_dma_ip
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GENERIC MAP (
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tech => 0,
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hindex => 2)
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PORT MAP (
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HCLK => clk,
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HRESETn => rstn,
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AHB_Master_In => AHB_Master_In,
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AHB_Master_Out => AHB_Master_Out,
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fifo_data => fifo_data,
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fifo_empty => fifo_empty,
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fifo_ren => fifo_ren,
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header => header,
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header_val => header_val,
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header_ack => header_ack,
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--OUT
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ready_matrix_f0_0 => ready_matrix_f0_0,
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ready_matrix_f0_1 => ready_matrix_f0_1,
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ready_matrix_f1 => ready_matrix_f1,
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ready_matrix_f2 => ready_matrix_f2,
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error_anticipating_empty_fifo => error_anticipating_empty_fifo,
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error_bad_component_error => error_bad_component_error,
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debug_reg => debug_reg,
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-- IN
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status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
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status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
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status_ready_matrix_f1 => status_ready_matrix_f1,
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status_ready_matrix_f2 => status_ready_matrix_f2,
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status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
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status_error_bad_component_error => status_error_bad_component_error,
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config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
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config_active_interruption_onError => config_active_interruption_onError,
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addr_matrix_f0_0 => addr_matrix_f0_0,
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addr_matrix_f0_1 => addr_matrix_f0_1,
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addr_matrix_f1 => addr_matrix_f1,
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addr_matrix_f2 => addr_matrix_f2);
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-----------------------------------------------------------------------------
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AHB_Master_In.HGRANT(2) <= '1';
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AHB_Master_In.HREADY <= '1';
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AHB_Master_In.HRESP <= HRESP_OKAY;
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END tb;
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