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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library grlib, techmap;
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use grlib.amba.all;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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--use gaisler.sim.all;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.general_purpose.all;
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use lpp.Rocket_PCM_Encoder.all;
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use work.Convertisseur_config.all;
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use work.config.all;
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entity ici4 is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
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);
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port (
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reset : in std_ulogic;
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clk : in std_ulogic;
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sclk : in std_logic;
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Gate : in std_logic;
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MinF : in std_logic;
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MajF : in std_logic;
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Data : out std_logic;
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DC_ADC_Sclk : out std_logic;
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DC_ADC_IN : in std_logic_vector(1 downto 0);
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DC_ADC_ClkDiv : out std_logic;
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DC_ADC_FSynch : out std_logic;
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SET_RESET0 : out std_logic;
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SET_RESET1 : out std_logic;
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LED : out std_logic
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);
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end;
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architecture rtl of ici4 is
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signal clk_buf,reset_buf : std_logic;
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Constant FramePlacerCount : integer := 2;
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signal MinF_Inv : std_logic;
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signal Gate_Inv : std_logic;
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signal sclk_Inv : std_logic;
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signal WordCount : integer range 0 to WordCnt-1;
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signal WordClk : std_logic;
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signal data_int : std_logic;
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signal MuxOUT : std_logic_vector(WordSize-1 downto 0);
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signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0);
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signal Sel : integer range 0 to 1;
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signal AMR1X : std_logic_vector(23 downto 0);
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signal AMR1Y : std_logic_vector(23 downto 0);
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signal AMR1Z : std_logic_vector(23 downto 0);
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signal AMR2X : std_logic_vector(23 downto 0);
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signal AMR2Y : std_logic_vector(23 downto 0);
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signal AMR2Z : std_logic_vector(23 downto 0);
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signal AMR3X : std_logic_vector(23 downto 0);
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signal AMR3Y : std_logic_vector(23 downto 0);
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signal AMR3Z : std_logic_vector(23 downto 0);
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signal AMR4X : std_logic_vector(23 downto 0);
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signal AMR4Y : std_logic_vector(23 downto 0);
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signal AMR4Z : std_logic_vector(23 downto 0);
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signal Temp1 : std_logic_vector(23 downto 0);
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signal Temp2 : std_logic_vector(23 downto 0);
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signal Temp3 : std_logic_vector(23 downto 0);
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signal Temp4 : std_logic_vector(23 downto 0);
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signal LF1 : std_logic_vector(15 downto 0);
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signal LF2 : std_logic_vector(15 downto 0);
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signal LF3 : std_logic_vector(15 downto 0);
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signal LF1_int : std_logic_vector(23 downto 0);
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signal LF2_int : std_logic_vector(23 downto 0);
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signal LF3_int : std_logic_vector(23 downto 0);
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signal DC_ADC_SmplClk : std_logic;
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signal LF_ADC_SmplClk : std_logic;
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signal SET_RESET0_sig : std_logic;
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signal SET_RESET1_sig : std_logic;
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signal MinFCnt : integer range 0 to MinFCount-1;
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signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0);
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begin
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clk_buf <= clk;
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reset_buf <= reset;
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--
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Gate_Inv <= not Gate;
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sclk_Inv <= not Sclk;
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MinF_Inv <= not MinF;
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LED <= not data_int;
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data <= data_int;
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SD0 : Serial_Driver
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generic map(WordSize)
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port map(sclk_Inv,MuxOUT,Gate_inv,data_int);
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WC0 : Word_Cntr
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generic map(WordSize,WordCnt)
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port map(sclk_Inv,MinF,WordClk,WordCount);
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MFC0 : MinF_Cntr
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generic map(MinFCount)
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port map(
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clk => MinF_Inv,
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reset => MajF,
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Cnt_out => MinFCnt
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);
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MUX0 : Serial_Driver_Multiplexor
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generic map(FramePlacerCount,WordSize)
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port map(sclk_Inv,Sel,MuxIN,MuxOUT);
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DCFP0 : entity work.DC_FRAME_PLACER
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generic map(WordSize,WordCnt,MinFCount)
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port map(
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clk => Sclk,
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Wcount => WordCount,
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MinFCnt => MinFCnt,
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Flag => FramePlacerFlags(0),
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AMR1X => AMR1X,
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AMR1Y => AMR1Y,
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AMR1Z => AMR1Z,
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AMR2X => AMR2X,
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AMR2Y => AMR2Y,
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AMR2Z => AMR2Z,
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AMR3X => AMR3X,
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AMR3Y => AMR3Y,
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AMR3Z => AMR3Z,
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AMR4X => AMR4X,
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AMR4Y => AMR4Y,
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AMR4Z => AMR4Z,
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Temp1 => Temp1,
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Temp2 => Temp2,
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Temp3 => Temp3,
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Temp4 => Temp4,
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WordOut => MuxIN(7 downto 0));
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LFP0 : entity work.LF_FRAME_PLACER
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generic map(WordSize,WordCnt,MinFCount)
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port map(
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clk => Sclk,
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Wcount => WordCount,
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Flag => FramePlacerFlags(1),
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LF1 => LF1,
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LF2 => LF2,
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LF3 => LF3,
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WordOut => MuxIN(15 downto 8));
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DC_SMPL_CLK0 : entity work.DC_SMPL_CLK
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port map(MinF_Inv,DC_ADC_SmplClk);
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process(reset,DC_ADC_SmplClk)
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begin
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if reset = '0' then
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SET_RESET0_sig <= '0';
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elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '1' then
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SET_RESET0_sig <= not SET_RESET0_sig;
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end if;
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end process;
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SET_RESET1_sig <= SET_RESET0_sig;
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SET_RESET0 <= SET_RESET0_sig;
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SET_RESET1 <= SET_RESET1_sig;
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--
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send_ADC_DATA : IF SEND_CONSTANT_DATA = 0 GENERATE
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DC_ADC0 : DUAL_ADS1278_DRIVER --With AMR down ! => 24bits DC TM -> SC high res on Spin
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port map(
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Clk => clk_buf,
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reset => reset_buf,
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SpiClk => DC_ADC_Sclk,
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DIN => DC_ADC_IN,
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SmplClk => DC_ADC_SmplClk,
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OUT00 => AMR1X,
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OUT01 => AMR1Y,
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OUT02 => AMR1Z,
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OUT03 => AMR2X,
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OUT04 => AMR2Y,
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OUT05 => AMR2Z,
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OUT06 => Temp1,
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OUT07 => Temp2,
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OUT10 => AMR3X,
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OUT11 => AMR3Y,
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OUT12 => AMR3Z,
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OUT13 => AMR4X,
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OUT14 => AMR4Y,
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OUT15 => AMR4Z,
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OUT16 => Temp3,
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OUT17 => Temp4,
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FSynch => DC_ADC_FSynch
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);
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LF1 <= LF1cst;
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LF2 <= LF2cst;
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LF3 <= LF3cst;
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END GENERATE;
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send_CST_DATA : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 0) GENERATE
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AMR1X <= AMR1Xcst;
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AMR1Y <= AMR1Ycst;
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AMR1Z <= AMR1Zcst;
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AMR2X <= AMR2Xcst;
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AMR2Y <= AMR2Ycst;
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AMR2Z <= AMR2Zcst;
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Temp1 <= Temp1cst;
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Temp2 <= Temp2cst;
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AMR3X <= AMR3Xcst;
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AMR3Y <= AMR3Ycst;
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AMR3Z <= AMR3Zcst;
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AMR4X <= AMR4Xcst;
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AMR4Y <= AMR4Ycst;
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AMR4Z <= AMR4Zcst;
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Temp3 <= Temp3cst;
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Temp4 <= Temp4cst;
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LF1 <= LF1cst;
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LF2 <= LF2cst;
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LF3 <= LF3cst;
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END GENERATE;
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send_minF_valuelbl : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 1) GENERATE
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AMR1X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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AMR1Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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AMR1Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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AMR2X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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AMR2Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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AMR2Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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Temp1 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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Temp2 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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AMR3X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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AMR3Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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AMR3Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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AMR4X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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AMR4Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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AMR4Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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Temp3 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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Temp4 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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LF1 <= LF1cst;
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LF2 <= LF2cst;
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LF3 <= LF3cst;
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END GENERATE;
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LF_SMPL_CLK0 : entity work.LF_SMPL_CLK
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port map(
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Wclck => WordClk,
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MinF => MinF,
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SMPL_CLK => LF_ADC_SmplClk
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);
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process(clk)
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variable SelVar : integer range 0 to 1;
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begin
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if clk'event and clk ='1' then
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Decoder: FOR i IN 0 to FramePlacerCount-1 loop
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if FramePlacerFlags(i) = '1' then
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SelVar := i;
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end if;
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END loop Decoder;
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Sel <= SelVar;
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end if;
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end process;
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end rtl;
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