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Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.
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leon3mp_synplify_win32.npl
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JDF G
PROJECT leon3mp
DESIGN leon3mp
DEVFAM Spartan3E
DEVICE xc3s1600e
DEVSPEED -4
DEVPKG fg320
DEVTOPLEVELMODULETYPE EDIF
DEVSIMULATOR Modelsim
DEVGENERATEDSIMULATIONMODEL VHDL
SOURCE synplify\leon3mp.edf
DEPASSOC leon3mp leon3mp.ucf
[Normal]
xilxMapAllowLogicOpt=edif, Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, True
xilxMapCoverMode=edif, Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, Speed
xilxNgdbld_AUL=edif, Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, True
xilxPAReffortLevel=edif, Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, Medium
xilxNgdbldMacro=edif, Spartan3E, EDIF.t_placeAndRouteDes, 1105378344, ..\..\netlists\xilinx\Spartan3