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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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entity Starter is
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port(
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clk : in std_logic;
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raz : in std_logic;
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Full : in std_logic_vector(1 downto 0);
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Empty : in std_logic_vector(1 downto 0);
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Statu : in std_logic_vector(3 downto 0);
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Write : in std_logic;
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Start : out std_logic
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);
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end Starter;
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architecture ar_Starter of Starter is
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type etat is (eX,e0,e1,e2);
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signal ect : etat;
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signal Write_reg : std_logic;
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signal Conjugate : std_logic;
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begin
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process(clk,raz)
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begin
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if(raz='0')then
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Start <= '0';
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Write_reg <= '0';
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ect <= eX;
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elsif(clk'event and clk='1')then
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Write_reg <= Write;
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case ect is
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when eX =>
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if(Conjugate='0')then
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if(full="11")then
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Start <= '1';
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ect <= e0;
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end if;
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else
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if(full(0)='1')then
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Start <= '1';
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ect <= e0;
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end if;
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end if;
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when e0 =>
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if(Conjugate='0')then
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if(empty="11")then
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ect <= e1;
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end if;
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else
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if(empty(0)='1')then
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ect <= e2;
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end if;
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end if;
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when e1 =>
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if(Write_reg='1' and Write='0')then
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ect <= e2;
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end if;
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when e2 =>
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if(Write_reg='1' and Write='0')then
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Start <= '0';
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ect <= eX;
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end if;
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end case;
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end if;
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end process;
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With Statu select
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Conjugate <= '1' when "0001",
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'1' when "0011",
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'1' when "0110",
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'1' when "1010",
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'1' when "1111",
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'0' when others;
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end ar_Starter;
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