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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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entity GetResult is
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generic(
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Result_SZ : integer := 32);
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port(
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clk : in std_logic;
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raz : in std_logic;
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Valid : in std_logic;
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Conjugate : in std_logic;
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Res : in std_logic_vector(Result_SZ-1 downto 0);
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-- Full : in std_logic;
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WriteFIFO : out std_logic;
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Received : out std_logic;
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Result : out std_logic_vector(Result_SZ-1 downto 0)
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);
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end GetResult;
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architecture ar_GetResult of GetResult is
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signal Valid_reg : std_logic;
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type state is (st0,st1,stX,stY);
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signal ect : state;
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begin
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process(clk,raz)
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begin
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if(raz='0')then
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Received <= '0';
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Valid_reg <= '0';
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WriteFIFO <= '0';
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ect <= st0;
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Result <= (others => '0');
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elsif(clk'event and clk='1')then
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Valid_reg <= Valid;
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case ect is
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when st0 =>
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if(Valid='1')then--if(Full='0' and Valid='1')then
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Result <= Res;
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WriteFIFO <= '1';
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Received <= '1';
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ect <= stX;
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end if;
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when stX =>
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WriteFIFO <= '0';
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if(Conjugate='1')then
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Received <= '0';
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end if;
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if(Valid_reg='1' and Valid='0')then
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if(Conjugate='1')then
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ect <= st0;
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else
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ect <= st1;
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end if;
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end if;
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when st1 =>
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if(Valid='1')then--if(Full='0' and Valid='1')then
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Result <= Res;
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WriteFIFO <= '1';
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Received <= '0';
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ect <= stY;
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end if;
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when stY =>
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WriteFIFO <= '0';
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if(Valid_reg='1' and Valid='0')then
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ect <= st0;
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end if;
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end case;
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end if;
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end process;
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end ar_GetResult;
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