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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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--! This is an automatic Baud generator. To synchronize baudrate, it measure the smalest time between two transitions of RXD. So to set baud rate, the device connected to this UART should send at least one data such as 0xA5 (0b10100101) witch gives a lot of transition of one bit length.
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--! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
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entity BaudGen is
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port(
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clk : in std_logic; --! System clock
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reset : in std_logic; --! System reset
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Capture : in std_logic; --! baudrate reset so if you want to synchronize again the baudrate generator, usefull if you whant to decrease speed.
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Bclk : out std_logic; --! Output baud clock
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RXD : in std_logic; --! UART Reception pin used to sample baudrate
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BTrigger : out std_logic_vector(11 downto 0) --! Current value of the frequency divider
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);
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end BaudGen;
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architecture ar_BaudGen of BaudGen is
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signal cpt : std_logic_vector(11 downto 0) := (others => '0');
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signal errorFlag : std_logic;
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signal triger : std_logic_vector(11 downto 0) := (others => '0');
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signal RX_reg : std_logic:='1';
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begin
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BTrigger <= triger;
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BaudGeneration:
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process(clk,reset)
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begin
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if reset = '0' then
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cpt <= (others => '0');
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triger <= (others => '1');
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errorFlag <= '0';
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elsif clk'event and clk = '1'then
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RX_reg <= RXD;
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if capture = '1' then
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cpt <= (others => '0');
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triger <= (others => '1');
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errorFlag <= '0';
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else
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if RX_reg /= RXD then
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cpt <= (others => '0');
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if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then
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errorFlag <= '1';
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elsif errorFlag = '1' then
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triger <= cpt;
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errorFlag <= '0';
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else
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errorFlag <= '1';
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end if;
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else
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if cpt = triger then
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cpt <= (others => '0');
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errorFlag <= '0';
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else
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cpt <= std_logic_vector(unsigned(cpt) + 1);
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end if;
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end if;
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end if;
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end if;
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end process;
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process(clk)
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begin
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if clk'event and clk = '1' then
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if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then
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Bclk <= '0';
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elsif cpt = '0' & triger(11 downto 1) then
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Bclk <= '1';
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end if;
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end if;
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end process;
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end ar_BaudGen;
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