HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-M7A3P1k/synthesis/leon3mp.srr

#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010

#install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1

#OS: 6.1

#Hostname: PC-SOLAR2

#Implementation: synthesis

#Tue Jul 24 16:56:59 2012

$ Start of Compile

#Tue Jul 24 16:56:59 2012

Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010

@N|Running in 32-bit mode

@N: CD720 :"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns

@N:"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":40:7:40:13|Top entity is set to leon3mp.

@W: CD433 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\sparc\sparc_disas.vhd":720:24:720:24|No design units in file

VHDL syntax check successful!

@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":40:7:40:13|Synthesizing work.leon3mp.behavioral

@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":169:2:169:8|Port lock of entity techmap.clkpad is unconnected

@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":171:2:171:8|Port clkc of entity techmap.clkgen is unconnected

@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":171:2:171:8|Port clkb of entity techmap.clkgen is unconnected

@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":171:2:171:8|Port clk2xu of entity techmap.clkgen is unconnected

@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":171:2:171:8|Port clk1xu of entity techmap.clkgen is unconnected

@W: CD326 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":171:2:171:8|Port clk4x of entity techmap.clkgen is unconnected

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":98:7:98:13|Signal resetnl is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":107:7:107:9|Signal cgi.clksel is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":107:7:107:9|Signal cgi.pllref is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_5.pindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_5.pconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_5.pconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_5.pirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_5.prdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_6.pindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_6.pconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_6.pconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_6.pirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_6.prdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_7.pindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_7.pconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_7.pconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_7.pirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_7.prdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_8.pindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_8.pconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_8.pconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_8.pirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_8.prdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_9.pindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_9.pconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_9.pconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_9.pirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_9.prdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_10.pindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_10.pconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_10.pconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_10.pirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_10.prdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_12.pindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_12.pconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_12.pconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_12.pirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_12.prdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_13.pindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_13.pconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_13.pconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_13.pirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_13.prdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_14.pindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_14.pconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_14.pconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_14.pirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_14.prdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_15.pindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_15.pconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_15.pconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_15.pirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":111:7:111:10|Signal apbo_15.prdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_15.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_14.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_13.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_12.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_11.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_10.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_9.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_8.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_7.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_6.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_5.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_4.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hcache is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hsplit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hrdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hresp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":113:7:113:11|Signal ahbso_3.hready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_15.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_14.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_13.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_12.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_11.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_10.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_9.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_8.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_7.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_6.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_5.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_4.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_3.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hconfig_0 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hconfig_1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hconfig_2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hconfig_3 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hconfig_4 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hconfig_5 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hconfig_6 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hconfig_7 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hirq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hprot is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.haddr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":115:7:115:11|Signal ahbmo_2.hbusreq is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":117:7:117:14|Signal ahbuarti.extclk is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":117:7:117:14|Signal ahbuarti.ctsn is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Signal memi.edac is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Signal memi.scb is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Signal memi.cb is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Signal memi.sd is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":124:7:124:9|Signal wpo.wprothit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":130:7:130:10|Signal gpti.wdogen is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Signal gpioi.sig_en is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Signal gpioi.sig_in is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 7 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 8 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 9 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 10 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 11 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 12 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 13 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 14 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 15 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 16 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 17 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 18 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 19 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 20 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 21 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 22 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 23 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 24 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 25 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 26 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 27 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 28 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 29 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 30 of signal gpioi.din is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 31 of signal gpioi.din is undriven

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\iopad.vhd":32:7:32:11|Synthesizing techmap.iopad.rtl

Post processing for techmap.iopad.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":45:7:45:12|Synthesizing gaisler.grgpio.rtl

Post processing for gaisler.grgpio.rtl

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_6(0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_5(0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_4(0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_3(0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_2(0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_1(0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.irqmap_0(0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.bypass(6 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.ilat(6 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.edge(6 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.level(6 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":320:4:320:5|Pruning Register r.imask(6 downto 0)

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":47:7:47:13|Synthesizing gaisler.apbuart.rtl

@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":77:15:77:16|Using sequential encoding for type txfsmtype

@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":76:15:76:16|Using onehot encoding for type rxfsmtype (idle="10000")

Post processing for gaisler.apbuart.rtl

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.rwaddr(0) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.tshift(10) is always 1, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.tcnt(1) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Register bit r.rcnt(1) is always 0, optimizing ...

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Pruning Register bit 1 of r.tcnt(1 downto 0)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Pruning Register bit 10 of r.tshift(10 downto 0)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Pruning Register bit 1 of r.rcnt(1 downto 0)

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\gptimer.vhd":47:7:47:13|Synthesizing gaisler.gptimer.rtl

Post processing for gaisler.gptimer.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":43:7:43:13|Synthesizing grlib.apbctrl.rtl

Post processing for grlib.apbctrl.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\outpad.vhd":32:7:32:12|Synthesizing techmap.outpad.rtl

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\outpad.vhd":39:7:39:10|Signal padx is undriven

Post processing for techmap.outpad.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\inpad.vhd":32:7:32:11|Synthesizing techmap.inpad.rtl

Post processing for techmap.inpad.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\ahbuart.vhd":45:7:45:13|Synthesizing gaisler.ahbuart.struct

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom.vhd":35:7:35:10|Synthesizing gaisler.dcom.struct

@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom.vhd":49:21:49:22|Using onehot encoding for type dcom_state_type (idle="100000")

Post processing for gaisler.dcom.struct

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom.vhd":147:8:147:9|Pruning Register r.hresp(1 downto 0)

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":39:7:39:15|Synthesizing gaisler.dcom_uart.rtl

@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":66:15:66:16|Using sequential encoding for type txfsmtype

@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":65:15:65:16|Using sequential encoding for type rxfsmtype

Post processing for gaisler.dcom_uart.rtl

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":49:4:49:5|uo.flow is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":49:4:49:5|uo.txen is not assigned a value (floating) - a simulation mismatch is possible

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Register bit r.tshift(10) is always 1, optimizing ...

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Pruning Register bit 10 of r.tshift(10 downto 0)

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\ahbmst.vhd":35:7:35:12|Synthesizing gaisler.ahbmst.rtl

Post processing for gaisler.ahbmst.rtl

Post processing for gaisler.ahbuart.struct

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":37:7:37:13|Synthesizing grlib.ahbctrl.rtl

Post processing for grlib.ahbctrl.rtl

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register r.lsplmst(0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register reg0.r.defmst_3

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register r.beat(3 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register r.hsize(2 downto 0)

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Register bit r.ldefmst is always 0, optimizing ...

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 0 of r.htrans(1 downto 0)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 15 of r.haddr(15 downto 2)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 14 of r.haddr(15 downto 2)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 13 of r.haddr(15 downto 2)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 12 of r.haddr(15 downto 2)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Pruning Register bit 11 of r.haddr(15 downto 2)

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\iopad.vhd":137:7:137:12|Synthesizing techmap.iopadv.rtl

Post processing for techmap.iopadv.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\outpad.vhd":115:7:115:13|Synthesizing techmap.outpadv.rtl

Post processing for techmap.outpadv.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":46:7:46:11|Synthesizing esa.mctrl.rtl

@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":120:18:120:19|Using onehot encoding for type memcycletype (idle="10000000")

@W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":740:4:740:17|OTHERS clause is not synthesized

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|Signal sdmo.vhready is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|Signal sdmo.bsel is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|Signal sdmo.hsel is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":199:7:199:9|Signal sdi.merror is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.dqm is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.casn is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.rasn is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.sdwen is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.sdcsn is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Signal lsdo.sdcke is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Signal rrsbdrive is undriven

Post processing for esa.mctrl.rtl

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 0 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 1 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 2 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 3 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 4 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 5 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 6 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 7 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 8 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 9 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 10 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 11 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 12 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 13 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 14 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 15 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 16 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 17 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 18 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 19 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 20 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 21 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 22 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 23 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 24 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 25 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 26 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 27 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 28 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 29 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 30 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 31 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 32 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 33 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 34 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 35 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 36 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 37 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 38 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 39 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 40 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 41 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 42 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 43 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 44 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 45 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 46 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 47 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 48 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 49 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 50 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 51 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 52 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 53 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 54 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 55 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 56 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 57 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 58 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 59 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 60 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 61 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 62 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":204:7:204:15|Bit 63 of signal rrsbdrive is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 0 of signal lsdo.dqm is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 1 of signal lsdo.dqm is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 2 of signal lsdo.dqm is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 3 of signal lsdo.dqm is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 4 of signal lsdo.dqm is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 5 of signal lsdo.dqm is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 6 of signal lsdo.dqm is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 7 of signal lsdo.dqm is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|lsdo.casn is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|lsdo.rasn is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|lsdo.sdwen is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 0 of signal lsdo.sdcsn is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 1 of signal lsdo.sdcsn is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 0 of signal lsdo.sdcke is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":200:7:200:10|Bit 1 of signal lsdo.sdcke is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":199:7:199:9|sdi.merror is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":199:7:199:9|sdi.idle is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|sdmo.vhready is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|sdmo.bsel is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":198:7:198:10|sdmo.hsel is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|memo.rs_edac_en is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|memo.sdram_en is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|memo.ce is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 0 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 1 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 2 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 3 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 4 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 5 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 6 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 7 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 8 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 9 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 10 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 11 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 12 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 13 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 14 of signal memo.sa is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 0 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 1 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 2 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 3 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 4 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 5 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 6 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 7 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 8 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 9 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 10 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 11 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 12 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 13 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 14 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 15 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 16 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 17 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 18 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 19 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 20 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 21 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 22 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 23 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 24 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 25 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 26 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 27 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 28 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 29 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 30 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 31 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 32 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 33 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 34 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 35 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 36 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 37 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 38 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 39 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 40 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 41 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 42 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 43 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 44 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 45 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 46 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 47 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 48 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 49 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 50 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 51 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 52 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 53 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 54 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 55 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 56 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 57 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 58 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 59 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 60 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 61 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 62 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":80:4:80:7|Bit 63 of signal memo.sddata is floating - a simulation mismatch is possible

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register stdregs.rsbdrive_3(63 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sd(63 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sa(14 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.htrans(1 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sdhsel

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.hsel

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.haddr(31 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.mcfg2.sdren

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.mcfg2.srdis

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.mcfg2.brdyen

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register stdregs.r.nbdrive_3(3 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.ready8

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.readdata(31 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.sdwritedata(63 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register r.writedata8(15 downto 0)

@W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Optimizing register bit r.ramsn(2) to a constant 1

@W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Optimizing register bit r.ramsn(3) to a constant 1

@W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Optimizing register bit r.ramsn(4) to a constant 1

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Pruning Register bit 4 of r.ramsn(4 downto 0)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Pruning Register bit 3 of r.ramsn(4 downto 0)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Pruning Register bit 2 of r.ramsn(4 downto 0)

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\irqmp.vhd":43:7:43:11|Synthesizing gaisler.irqmp.rtl

Post processing for gaisler.irqmp.rtl

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\irqmp.vhd":316:8:316:9|Pruning Register r.ibroadcast(15 downto 1)

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3.vhd":44:7:44:10|Synthesizing gaisler.dsu3.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":37:7:37:11|Synthesizing gaisler.dsu3x.rtl

@W: CD434 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":164:79:164:86|Signal hrdata2x in the sensitivity list is not used in the process

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Signal tbo.data is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.break is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbwr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.write is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.read is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.mask is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg2.addr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.write is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.read is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.mask is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.tbreg1.addr is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.delaycnt is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.dcnten is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.bphit2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.bphit is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.enable is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.aindex is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.ahbactive is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hsel is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hmastlock is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hmaster is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hwdata is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hburst is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hsize is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.htrans is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.hwrite is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Signal tr.haddr is undriven

Post processing for gaisler.dsu3x.rtl

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":158:13:158:16|rhin.irq is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.break is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbwr is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg2.write is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg2.read is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg1.write is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.tbreg1.read is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.delaycnt is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.delaycnt is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.delaycnt is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.delaycnt is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.delaycnt is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.delaycnt is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.dcnten is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.bphit2 is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.bphit is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.enable is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.aindex is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.aindex is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.aindex is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.aindex is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.aindex is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.aindex is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.ahbactive is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.hsel is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.hmastlock is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hmaster is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hmaster is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hmaster is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.hmaster is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 30 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 31 of signal tr.hwdata is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hburst is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hburst is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hburst is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.hsize is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.hsize is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.hsize is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.htrans is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.htrans is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|tr.hwrite is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 0 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 1 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 2 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 3 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 4 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 5 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 6 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 7 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 8 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 9 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 10 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 11 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 12 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 13 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 14 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 15 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 16 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 17 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 18 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 19 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 20 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 21 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 22 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 23 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 24 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 25 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 26 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 27 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 28 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 29 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 30 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":155:9:155:10|Bit 31 of signal tr.haddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 0 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 1 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 2 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 3 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 4 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 5 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 6 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 7 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 8 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 9 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 10 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 11 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 12 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 13 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 14 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 15 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 16 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 17 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 18 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 19 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 20 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 21 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 22 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 23 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 24 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 25 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 26 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 27 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 28 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 29 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 30 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 31 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 32 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 33 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 34 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 35 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 36 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 37 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 38 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 39 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 40 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 41 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 42 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 43 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 44 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 45 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 46 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 47 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 48 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 49 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 50 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 51 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 52 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 53 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 54 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 55 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 56 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 57 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 58 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 59 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 60 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 61 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 62 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 63 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 64 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 65 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 66 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 67 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 68 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 69 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 70 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 71 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 72 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 73 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 74 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 75 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 76 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 77 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 78 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 79 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 80 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 81 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 82 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 83 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 84 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 85 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 86 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 87 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 88 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 89 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 90 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 91 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 92 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 93 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 94 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 95 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 96 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 97 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 98 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 99 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 100 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 101 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 102 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 103 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 104 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 105 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 106 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 107 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 108 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 109 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 110 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 111 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 112 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 113 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 114 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 115 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 116 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 117 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 118 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 119 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 120 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 121 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 122 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 123 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 124 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 125 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 126 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":153:9:153:11|Bit 127 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Pruning Register bit 1 of r.slv.haddr(24 downto 0)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Pruning Register bit 0 of r.slv.haddr(24 downto 0)

Post processing for gaisler.dsu3.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":158:7:158:12|Synthesizing gaisler.leon3s.rtl

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Signal tbo.data is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":241:7:241:9|Signal rd1 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":241:12:241:14|Signal rd2 is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":241:17:241:18|Signal wd is undriven

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":37:7:37:14|Synthesizing gaisler.cachemem.rtl

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":127:9:127:17|Signal ildataout is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":148:19:148:26|Signal ldataout is undriven

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":34:7:34:13|Synthesizing techmap.syncram.rtl

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":49:9:49:12|Signal rena is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":49:15:49:18|Signal wena is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":50:19:50:24|Signal databp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":50:27:50:34|Signal testdata is undriven

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":380:7:380:22|Synthesizing techmap.proasic3_syncram.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":178:7:178:25|Synthesizing techmap.proasic3_syncram_dp.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":33:7:33:21|Synthesizing techmap.proasic3_ram4k9.rtl

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":77:7:77:8|Bit 9 of signal qa is undriven

@W: CD796 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":77:11:77:12|Bit 9 of signal qb is undriven

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":46:12:46:17|Synthesizing techmap.ram4k9.syn_black_box

Post processing for techmap.ram4k9.syn_black_box

Post processing for techmap.proasic3_ram4k9.rtl

Post processing for techmap.proasic3_syncram_dp.rtl

Post processing for techmap.proasic3_syncram.rtl

Post processing for techmap.syncram.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":34:7:34:13|Synthesizing techmap.syncram.rtl

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":49:9:49:12|Signal rena is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":49:15:49:18|Signal wena is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":50:19:50:24|Signal databp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":50:27:50:34|Signal testdata is undriven

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":380:7:380:22|Synthesizing techmap.proasic3_syncram.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":274:7:274:25|Synthesizing techmap.proasic3_syncram_2p.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":120:7:120:24|Synthesizing techmap.proasic3_ram512x18.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":132:12:132:20|Synthesizing techmap.ram512x18.syn_black_box

Post processing for techmap.ram512x18.syn_black_box

Post processing for techmap.proasic3_ram512x18.rtl

Post processing for techmap.proasic3_syncram_2p.rtl

Post processing for techmap.proasic3_syncram.rtl

Post processing for techmap.syncram.rtl

Post processing for gaisler.cachemem.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\regfile_3p.vhd":32:7:32:16|Synthesizing techmap.regfile_3p.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram_2p.vhd":35:7:35:16|Synthesizing techmap.syncram_2p.rtl

@W: CD434 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram_2p.vhd":107:36:107:41|Signal testin in the sensitivity list is not used in the process

@W: CD729 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram_2p.vhd":199:4:199:5|Component declaration has 3 generics but entity declares only 2 generics

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram_2p.vhd":58:7:58:12|Signal databp is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram_2p.vhd":58:15:58:22|Signal testdata is undriven

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":274:7:274:25|Synthesizing techmap.proasic3_syncram_2p.rtl

Post processing for techmap.proasic3_syncram_2p.rtl

Post processing for techmap.syncram_2p.rtl

Post processing for techmap.regfile_3p.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\proc3.vhd":43:7:43:11|Synthesizing gaisler.proc3.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_cache.vhd":39:7:39:15|Synthesizing gaisler.mmu_cache.rtl

@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":40:7:40:16|Synthesizing gaisler.mmu_acache.rtl

@W: CD434 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":100:57:100:62|Signal hclken in the sensitivity list is not used in the process

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":96:7:96:8|Signal r2.hclken2 is undriven

Post processing for gaisler.mmu_acache.rtl

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":96:7:96:8|r2.hclken2 is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 0 of signal mcdo.par is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 1 of signal mcdo.par is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 2 of signal mcdo.par is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":53:4:53:7|Bit 3 of signal mcdo.par is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 0 of signal mcio.par is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 1 of signal mcio.par is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 2 of signal mcio.par is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":51:4:51:7|Bit 3 of signal mcio.par is floating - a simulation mismatch is possible

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":41:7:41:16|Synthesizing gaisler.mmu_dcache.rtl

@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache

@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":131:16:131:17|Using onehot encoding for type dstatetype (idle="100000000")

@N: CD231 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":118:15:118:16|Using onehot encoding for type rdatatype (dtag="100000000")

@W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1061:4:1061:17|OTHERS clause is not synthesized

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Signal rh.snmiss is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Signal rh.hitaddr is undriven

Post processing for gaisler.mmu_dcache.rtl

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|rh.snmiss is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 0 of signal rh.hitaddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 1 of signal rh.hitaddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 2 of signal rh.hitaddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 3 of signal rh.hitaddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 4 of signal rh.hitaddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 5 of signal rh.hitaddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 6 of signal rh.hitaddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":274:7:274:8|Bit 7 of signal rh.hitaddr is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.sdiag is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.sdiag is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.sdiag is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.sdiag is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|dcrami.spar is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 0 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 1 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 2 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 3 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 4 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 5 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 6 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 7 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 8 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 9 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 10 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 11 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 12 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 13 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 14 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 15 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 16 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 17 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 18 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":74:4:74:9|Bit 19 of signal dcrami.faddress is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|dco.cache is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 0 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 1 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 2 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":69:4:69:6|Bit 3 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.cache is always 1, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.cctrl.dsnoop is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.e is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.nf is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.pso is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.tlbdis is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.bar(0) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.bar(1) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.pagesize(0) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.pagesize(1) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(0) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(1) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(2) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(3) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(4) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(5) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(6) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctx(7) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(0) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(1) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(2) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(3) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(4) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(5) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(6) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(7) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(8) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(9) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(10) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(11) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(12) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(13) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(14) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(15) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(16) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(17) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(18) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(19) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(20) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(21) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(22) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(23) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(24) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(25) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(26) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(27) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(28) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.mmctrl1.ctxp(29) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.lock is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.flush_op is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.trans_op is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.dsuset(0) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.lrr is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.ilramen is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Register bit r.ready is always 0, optimizing ...

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":37:7:37:16|Synthesizing gaisler.mmu_icache.rtl

@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmuconfig.vhd":39:17:39:18|Using sequential encoding for type mmu_idcache

@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":162:16:162:17|Using sequential encoding for type istatetype

@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":94:15:94:16|Using sequential encoding for type rdatatype

@W: CD604 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":474:4:474:17|OTHERS clause is not synthesized

Post processing for gaisler.mmu_icache.rtl

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.dpar is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.dpar is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.dpar is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.dpar is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_0 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_1 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_2 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 0 of signal icrami.tpar_3 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 1 of signal icrami.tpar_3 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 2 of signal icrami.tpar_3 is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":59:4:59:9|Bit 3 of signal icrami.tpar_3 is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.mhold is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.chold is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.tmiss is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":54:4:54:6|ico.cstat.cmiss is not assigned a value (floating) - a simulation mismatch is possible

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflushtyp

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflushaddr(31 downto 12)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflushr

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.pflush

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.diagset(0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.setrepl(0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.rndcnt(0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Pruning Register r.flush3

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.lock is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.trans_op is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.lrr is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Register bit r.cache is always 1, optimizing ...

Post processing for gaisler.mmu_cache.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":42:7:42:9|Synthesizing gaisler.iu3.rtl

@N: CD233 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":242:23:242:24|Using sequential encoding for type exception_state

@N: CD364 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2808:4:2808:4|Removed redundant assignment

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2349:9:2349:17|Signal cpu_index is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2350:9:2350:15|Signal disasen is undriven

Post processing for gaisler.iu3.rtl

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.su is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.wbhold is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.mhold is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.chold is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.tmiss is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.dstat.cmiss is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.mhold is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.chold is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.tmiss is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.istat.cmiss is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.bpmiss is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 0 of signal dbgo.optype is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 1 of signal dbgo.optype is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 2 of signal dbgo.optype is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 3 of signal dbgo.optype is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 4 of signal dbgo.optype is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|Bit 5 of signal dbgo.optype is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":80:4:80:7|dbgo.fcnt is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":78:4:78:7|irqo.fpen is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":73:4:73:6|dci.flushl is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":71:4:71:6|ici.pnull is not assigned a value (floating) - a simulation mismatch is possible

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":3026:6:3026:7|Pruning Register dsur.tbufcnt(5 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.w.except

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.w.wreg

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.w.wa(6 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.mac

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.asi(7 downto 0)

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.dsuen

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.lock

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.write

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.read

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.x.dci.enaddr

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.m.casaz

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.m.mul

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.m.divz

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.e.mul

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldchkex

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldchkra

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldcheck2

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.a.ldcheck1

@W: CL169 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register r.d.divrdy

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.divstart is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.mulstart is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.w.s.ec is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.w.s.ef is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(0) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(1) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(2) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(3) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(4) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.a.ctrl.tt(5) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Register bit r.x.npc(2) is always 0, optimizing ...

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Pruning Register bit 2 of r.x.npc(2 downto 0)

Post processing for gaisler.proc3.rtl

Post processing for gaisler.leon3s.rtl

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 0 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 1 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 2 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 3 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 4 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 5 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 6 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 7 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 8 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 9 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 10 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 11 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 12 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 13 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 14 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 15 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 16 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 17 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 18 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 19 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 20 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 21 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 22 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 23 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 24 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 25 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 26 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 27 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 28 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 29 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 30 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 31 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 32 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 33 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 34 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 35 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 36 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 37 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 38 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 39 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 40 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 41 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 42 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 43 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 44 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 45 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 46 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 47 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 48 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 49 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 50 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 51 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 52 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 53 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 54 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 55 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 56 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 57 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 58 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 59 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 60 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 61 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 62 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 63 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 64 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 65 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 66 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 67 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 68 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 69 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 70 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 71 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 72 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 73 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 74 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 75 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 76 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 77 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 78 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 79 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 80 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 81 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 82 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 83 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 84 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 85 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 86 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 87 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 88 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 89 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 90 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 91 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 92 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 93 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 94 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 95 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 96 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 97 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 98 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 99 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 100 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 101 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 102 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 103 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 104 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 105 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 106 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 107 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 108 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 109 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 110 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 111 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 112 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 113 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 114 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 115 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 116 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 117 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 118 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 119 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 120 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 121 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 122 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 123 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 124 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 125 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 126 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":233:7:233:9|Bit 127 of signal tbo.data is floating - a simulation mismatch is possible

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 0 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 1 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 2 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 3 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 4 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 5 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 6 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 7 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 8 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 9 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 10 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 11 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 12 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 13 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 14 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 15 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 16 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 17 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 18 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 19 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 20 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 21 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 22 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 23 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 24 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 25 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 26 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 27 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 28 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 29 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 30 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 31 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 32 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 33 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 34 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 35 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 36 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 37 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 38 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 39 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 40 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 41 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 42 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 43 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 44 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 45 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 46 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 47 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 48 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 49 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 50 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 51 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 52 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 53 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 54 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 55 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 56 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 57 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 58 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 59 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 60 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 61 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 62 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 63 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 64 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 65 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 66 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 67 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 68 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 69 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 70 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 71 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 72 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 73 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 74 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 75 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 76 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 77 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 78 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 79 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 80 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 81 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 82 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 83 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 84 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 85 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 86 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 87 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 88 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 89 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 90 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 91 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 92 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 93 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 94 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 95 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 96 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 97 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 98 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 99 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 100 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 101 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 102 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 103 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 104 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 105 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 106 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 107 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 108 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 109 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 110 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 111 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 112 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 113 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 114 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 115 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 116 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 117 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 118 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 119 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 120 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 121 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 122 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 123 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 124 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 125 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 126 of input tbo of instance p0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\leon3s.vhd":258:2:258:3|Bit 127 of input tbo of instance p0 is floating

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":32:7:32:12|Synthesizing techmap.clkgen.struct

@W: CD279 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\allclkgen.vhd":348:4:348:7|Port clkb of component clkgen_proasic3 not found on corresponding entity

@W: CD279 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\allclkgen.vhd":349:4:349:7|Port clkc of component clkgen_proasic3 not found on corresponding entity

@W: CD729 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":157:4:157:4|Component declaration has 8 generics but entity declares only 6 generics

@W: CD730 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":157:4:157:4|Component declaration has 9 ports but entity declares 7 ports

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":66:7:66:12|Signal intclk is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":66:15:66:22|Signal sdintclk is undriven

@W: CD638 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":67:7:67:10|Signal lock is undriven

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd":41:7:41:21|Synthesizing techmap.clkgen_proasic3.struct

@W: CD280 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd":83:14:83:19|Unbound component PLLINT mapped to black box

@W: CD280 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd":64:14:64:16|Unbound component PLL mapped to black box

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd":64:14:64:16|Synthesizing techmap.pll.syn_black_box

Post processing for techmap.pll.syn_black_box

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd":83:14:83:19|Synthesizing techmap.pllint.syn_black_box

Post processing for techmap.pllint.syn_black_box

Post processing for techmap.clkgen_proasic3.struct

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd":53:4:53:8|sdclk is not assigned a value (floating) - a simulation mismatch is possible

Post processing for techmap.clkgen.struct

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":62:4:62:7|clkc is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":61:4:61:7|clkb is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":60:4:60:9|clk2xu is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":59:4:59:9|clk1xu is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":58:4:58:8|clk4x is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":53:4:53:8|clk2x is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkgen.vhd":52:4:52:7|clkn is not assigned a value (floating) - a simulation mismatch is possible

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkpad.vhd":32:7:32:12|Synthesizing techmap.clkpad.rtl

Post processing for techmap.clkpad.rtl

@N: CD630 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\rstgen.vhd":29:7:29:12|Synthesizing gaisler.rstgen.rtl

Post processing for gaisler.rstgen.rtl

Post processing for work.leon3mp.behavioral

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 0 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 1 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 2 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 3 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 4 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 5 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 6 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 7 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 8 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 9 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 10 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 11 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 12 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 13 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 14 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 15 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 16 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 17 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 18 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 19 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 20 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 21 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 22 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 23 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 24 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 25 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 26 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 27 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 28 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 29 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 30 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 31 of signal gpioi.sig_en is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 0 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 1 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 2 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 3 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 4 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 5 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 6 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 7 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 8 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 9 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 10 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 11 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 12 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 13 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 14 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 15 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 16 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 17 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 18 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 19 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 20 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 21 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 22 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 23 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 24 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 25 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 26 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 27 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 28 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 29 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 30 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":133:7:133:11|Bit 31 of signal gpioi.sig_in is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":130:7:130:10|gpti.wdogen is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":124:7:124:9|wpo.wprothit is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|memi.edac is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 0 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 1 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 2 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 3 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 4 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 5 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 6 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 7 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 8 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 9 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 10 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 11 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 12 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 13 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 14 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 15 of signal memi.scb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 0 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 1 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 2 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 3 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 4 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 5 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 6 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 7 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 8 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 9 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 10 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 11 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 12 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 13 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 14 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 15 of signal memi.cb is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 0 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 1 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 2 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 3 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 4 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 5 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 6 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 7 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 8 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 9 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 10 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 11 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 12 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 13 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 14 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 15 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 16 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 17 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 18 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 19 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 20 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 21 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 22 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 23 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 24 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 25 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 26 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 27 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 28 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 29 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 30 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 31 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 32 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 33 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 34 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 35 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 36 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 37 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 38 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 39 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 40 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 41 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 42 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 43 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 44 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 45 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 46 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 47 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 48 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 49 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 50 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 51 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 52 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 53 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 54 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 55 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 56 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 57 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 58 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 59 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 60 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 61 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 62 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":122:7:122:10|Bit 63 of signal memi.sd is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":117:7:117:14|ahbuarti.extclk is not assigned a value (floating) - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":117:7:117:14|ahbuarti.ctsn is not assigned a value (floating) - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":107:7:107:9|Bit 0 of signal cgi.clksel is floating - a simulation mismatch is possible

@W: CL252 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":107:7:107:9|Bit 1 of signal cgi.clksel is floating - a simulation mismatch is possible

@W: CL240 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":107:7:107:9|cgi.pllref is not assigned a value (floating) - a simulation mismatch is possible

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 32 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 33 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 34 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 35 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 36 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 37 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 38 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 39 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 40 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 41 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 42 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 43 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 44 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 45 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 46 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 47 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 48 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 49 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 50 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 51 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 52 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 53 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 54 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 55 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 56 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 57 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 58 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 59 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 60 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 61 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 62 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 63 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 64 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 65 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 66 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 67 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 68 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 69 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 70 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 71 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 72 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 73 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 74 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 75 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 76 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 77 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 78 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 79 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 80 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 81 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 82 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 83 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 84 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 85 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 86 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 87 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 88 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 89 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 90 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 91 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 92 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 93 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 94 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":348:4:348:10|Bit 95 of input gpioi of instance grgpio0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":333:4:333:8|Bit 1 of input uarti of instance uart1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":333:4:333:8|Bit 2 of input uarti of instance uart1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":317:4:317:9|Bit 2 of input gpti of instance timer0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":295:4:295:8|Bit 1 of input uarti of instance dcom0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":295:4:295:8|Bit 2 of input uarti of instance dcom0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 41 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 42 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 43 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 44 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 45 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 46 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 47 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 48 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 49 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 50 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 51 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 52 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 53 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 54 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 55 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 56 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 57 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 58 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 59 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 60 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 61 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 62 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 63 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 64 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 65 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 66 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 67 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 68 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 69 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 70 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 71 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 72 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 73 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 74 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 75 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 76 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 77 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 78 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 79 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 80 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 81 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 82 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 83 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 84 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 85 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 86 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 87 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 88 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 89 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 90 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 91 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 92 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 93 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 94 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 95 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 96 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 97 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 98 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 99 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 100 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 101 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 102 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 103 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 104 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 105 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 106 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 107 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 108 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 109 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 110 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 111 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 112 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 113 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 114 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 115 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 116 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 117 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 118 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 119 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 120 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 121 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 122 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 123 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 124 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 125 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 126 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 127 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 128 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 129 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 130 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 131 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 132 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 133 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 134 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 135 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 136 of input memi of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Bit 137 of input memi of instance sr1 is floating

@W: CL167 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":240:4:240:6|Input wpo of instance sr1 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":171:2:171:8|Bit 0 of input cgi of instance clkgen0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":171:2:171:8|Bit 4 of input cgi of instance clkgen0 is floating

@W: CL245 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":171:2:171:8|Bit 5 of input cgi of instance clkgen0 is floating

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\rstgen.vhd":40:4:40:10|Input testrst is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\rstgen.vhd":41:4:41:9|Input testen is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\clkpad.vhd":36:49:36:52|Input rstn is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd":51:4:51:11|Input pciclkin is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd":55:4:55:6|Input cgi is unused

@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Trying to extract state machine for register r.d.cnt

@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Trying to extract state machine for register r.x.rstate

Extracted state machine for register r.x.rstate

State machine has 4 reachable states with original encodings of:

00

01

10

11

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 203 to 200 of ico(203 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 198 to 167 of ico(203 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 165 to 134 of ico(203 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 132 to 131 of ico(203 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 129 to 128 of ico(203 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":72:4:72:6|Input port bits 95 to 0 of ico(203 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bits 207 to 134 of dco(210 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bit 131 of dco(210 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bits 129 to 128 of dco(210 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":74:4:74:6|Input port bits 95 to 0 of dco(210 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":77:4:77:7|Input port bits 30 to 4 of irqi(30 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":79:4:79:7|Input port bits 97 to 66 of dbgi(97 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":85:4:85:6|Input port bit 37 of fpo(69 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":85:4:85:6|Input port bits 35 to 0 of fpo(69 downto 0) are unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":82:4:82:7|Input mulo is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":84:4:84:7|Input divo is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":87:4:87:6|Input cpo is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\iu3.vhd":89:4:89:6|Input tbo is unused

@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Trying to extract state machine for register r.istate

Extracted state machine for register r.istate

State machine has 3 reachable states with original encodings of:

00

10

11

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 131 to 101 of ici(131 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 95 to 64 of ici(131 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 33 to 22 of ici(131 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":53:4:53:6|Input port bits 1 to 0 of ici(131 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":55:4:55:6|Input port bits 117 to 40 of dci(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":55:4:55:6|Input port bits 7 to 0 of dci(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 210 to 207 of dco(210 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 205 to 180 of dco(210 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 177 to 173 of dco(210 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bit 169 of dco(210 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 165 to 156 of dco(210 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 135 to 132 of dco(210 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":56:4:56:6|Input port bits 130 to 0 of dco(210 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":58:4:58:7|Input port bits 41 to 37 of mcio(41 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":60:4:60:9|Input port bits 319 to 256 of icramo(319 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":60:4:60:9|Input port bits 95 to 0 of icramo(319 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":62:4:62:9|Input port bits 117 to 85 of mmudci(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":62:4:62:9|Input port bits 76 to 0 of mmudci(117 downto 0) are unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_icache.vhd":64:4:64:9|Input mmuico is unused

@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Trying to extract state machine for register r.dstate

Extracted state machine for register r.dstate

State machine has 6 reachable states with original encodings of:

000000001

000000010

000001000

001000000

010000000

100000000

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bit 116 of dci(117 downto 0) is unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bit 113 of dci(117 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bits 71 to 52 of dci(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bits 41 to 40 of dci(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":68:4:68:6|Input port bits 7 to 5 of dci(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":70:4:70:6|Input port bits 203 to 199 of ico(203 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":70:4:70:6|Input port bit 166 of ico(203 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":70:4:70:6|Input port bits 130 to 0 of ico(203 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":72:4:72:7|Input port bits 43 to 38 of mcdo(45 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":73:4:73:8|Input port bits 139 to 28 of ahbsi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":73:4:73:8|Input port bits 19 to 0 of ahbsi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":75:4:75:9|Input port bits 451 to 384 of dcramo(451 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":75:4:75:9|Input port bits 363 to 256 of dcramo(451 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":78:4:78:9|Input port bits 110 to 2 of mmudco(110 downto 0) are unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_dcache.vhd":79:4:79:7|Input sclk is unused

@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":355:4:355:5|Trying to extract state machine for register r.bo

Extracted state machine for register r.bo

State machine has 4 reachable states with original encodings of:

00

01

10

11

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":50:4:50:7|Input port bit 35 of mcii(35 downto 0) is unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":54:4:54:8|Input port bit 66 of mcmmi(69 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":56:4:56:7|Input port bits 87 to 85 of ahbi(87 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":56:4:56:7|Input port bits 83 to 51 of ahbi(87 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":56:4:56:7|Input port bits 14 to 0 of ahbi(87 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5503 to 5372 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5359 to 5357 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5343 to 5340 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5327 to 5325 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5311 to 5308 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5295 to 5293 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5279 to 5276 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5263 to 5261 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5247 to 5028 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 5015 to 5013 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4999 to 4996 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4983 to 4981 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4967 to 4964 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4951 to 4949 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4935 to 4932 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4919 to 4917 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4903 to 4684 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4671 to 4669 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4655 to 4652 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4639 to 4637 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4623 to 4620 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4607 to 4605 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4591 to 4588 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4575 to 4573 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4559 to 4340 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4327 to 4325 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4311 to 4308 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4295 to 4293 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4279 to 4276 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4263 to 4261 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4247 to 4244 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4231 to 4229 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 4215 to 3996 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3983 to 3981 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3967 to 3964 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3951 to 3949 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3935 to 3932 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3919 to 3917 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3903 to 3900 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3887 to 3885 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3871 to 3652 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3639 to 3637 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3623 to 3620 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3607 to 3605 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3591 to 3588 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3575 to 3573 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3559 to 3556 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3543 to 3541 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3527 to 3308 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3295 to 3293 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3279 to 3276 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3263 to 3261 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3247 to 3244 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3231 to 3229 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3215 to 3212 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3199 to 3197 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 3183 to 2964 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2951 to 2949 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2935 to 2932 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2919 to 2917 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2903 to 2900 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2887 to 2885 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2871 to 2868 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2855 to 2853 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2839 to 2620 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2607 to 2605 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2591 to 2588 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2575 to 2573 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2559 to 2556 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2543 to 2541 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2527 to 2524 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2511 to 2509 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2495 to 2276 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2263 to 2261 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2247 to 2244 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2231 to 2229 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2215 to 2212 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2199 to 2197 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2183 to 2180 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2167 to 2165 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 2151 to 1932 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1919 to 1917 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1903 to 1900 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1887 to 1885 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1871 to 1868 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1855 to 1853 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1839 to 1836 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1823 to 1821 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1807 to 1588 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1575 to 1573 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1559 to 1556 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1543 to 1541 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1527 to 1524 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1511 to 1509 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1495 to 1492 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1479 to 1477 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1463 to 1244 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1231 to 1229 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1215 to 1212 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1199 to 1197 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1183 to 1180 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1167 to 1165 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1151 to 1148 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1135 to 1133 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 1119 to 900 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 887 to 885 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 871 to 868 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 855 to 853 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 839 to 836 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 823 to 821 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 807 to 804 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 791 to 789 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 775 to 556 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 543 to 541 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 527 to 524 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 511 to 509 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 495 to 492 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 479 to 477 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 463 to 460 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 447 to 445 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 431 to 212 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 199 to 197 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 183 to 180 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 167 to 165 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 151 to 148 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 135 to 133 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 119 to 116 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 103 to 101 of ahbso(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":58:4:58:8|Input port bits 87 to 0 of ahbso(5503 downto 0) are unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_acache.vhd":59:4:59:9|Input hclken is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\mmu_cache.vhd":88:4:88:7|Input hclk is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram_2p.vhd":48:4:48:9|Input testin is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":127:4:127:6|Input wea is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":44:4:44:9|Input testin is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":188:4:188:11|Input address2 is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\proasic3\memory_apa3.vhd":189:4:189:10|Input datain2 is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\techmap\maps\syncram.vhd":44:4:44:9|Input testin is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 796 to 647 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 645 to 643 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 641 to 639 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 606 to 511 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 508 to 502 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 500 to 370 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 349 to 342 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 337 to 232 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 221 to 191 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 189 to 187 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 150 to 148 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 127 to 120 of crami(796 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":62:1:62:5|Input port bits 115 to 10 of crami(796 downto 0) are unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\cachemem.vhd":64:8:64:11|Input sclk is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 139 to 94 of ahbsi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 92 to 89 of ahbsi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 56 to 51 of ahbsi(139 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bit 49 of ahbsi(139 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 47 to 41 of ahbsi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 17 to 14 of ahbsi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":55:4:55:8|Input port bits 12 to 0 of ahbsi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":57:4:57:7|Input port bits 0 to 18 of dbgi(0 to 58) are unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":52:4:52:7|Input hclk is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\dsu3x.vhd":54:4:54:8|Input ahbmi is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 117 to 98 of apbi(117 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bit 82 of apbi(117 downto 0) is unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bit 66 of apbi(117 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 15 to 14 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\irqmp.vhd":54:4:54:7|Input port bits 12 to 0 of apbi(117 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\leon3\irqmp.vhd":56:4:56:7|Input port bit 0 of irqi(0 to 6) is unused

@W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Optimizing register bit r.ramoen(2) to a constant 1

@W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Optimizing register bit r.ramoen(3) to a constant 1

@W: CL190 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Optimizing register bit r.ramoen(4) to a constant 1

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Pruning Register bit 4 of r.ramoen(4 downto 0)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Pruning Register bit 3 of r.ramoen(4 downto 0)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Pruning Register bit 2 of r.ramoen(4 downto 0)

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bwrite16) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bread16) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bwrite8) is always 0, optimizing ...

@W: CL189 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit r.bstate(bread8) is always 0, optimizing ...

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 0 of r.bstate(0 to 7)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 1 of r.bstate(0 to 7)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 2 of r.bstate(0 to 7)

@W: CL260 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Pruning Register bit 3 of r.bstate(0 to 7)

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":79:4:79:7|Input port bits 137 to 41 of memi(137 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":79:4:79:7|Input port bits 38 to 34 of memi(137 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 139 to 103 of ahbsi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 99 to 94 of ahbsi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 92 to 89 of ahbsi(139 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bit 53 of ahbsi(139 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":81:4:81:8|Input port bits 14 to 0 of ahbsi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 117 to 79 of apbi(117 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bit 74 of apbi(117 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 68 to 63 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 48 to 23 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":83:4:83:7|Input port bits 14 to 0 of apbi(117 downto 0) are unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\esa\memoryctrl\mctrl.vhd":85:4:85:6|Input wpo is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 5935 to 738 of msto(5935 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 705 to 482 of msto(5935 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 370 to 367 of msto(5935 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":73:4:73:7|Input port bits 334 to 111 of msto(5935 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 5503 to 2748 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2458 to 2443 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2407 to 2404 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2114 to 2099 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 2063 to 2060 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1770 to 1755 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1719 to 1716 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1426 to 1411 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1375 to 1372 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1082 to 1067 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 1031 to 1028 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 738 to 723 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 687 to 684 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 394 to 379 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 343 to 340 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\ahbctrl.vhd":75:4:75:7|Input port bits 50 to 35 of slvo(5503 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\ahbmst.vhd":49:6:49:9|Input port bits 87 to 51 of ahbi(87 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\ahbmst.vhd":49:6:49:9|Input port bit 15 of ahbi(87 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\ahbmst.vhd":49:6:49:9|Input port bits 13 to 0 of ahbi(87 downto 0) are unused

@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Trying to extract state machine for register r.txstate

Extracted state machine for register r.txstate

State machine has 3 reachable states with original encodings of:

00

01

10

@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Trying to extract state machine for register r.rxstate

Extracted state machine for register r.rxstate

State machine has 4 reachable states with original encodings of:

00

01

10

11

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":48:4:48:5|Input port bits 2 to 1 of ui(2 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 117 to 68 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 48 to 21 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 15 to 12 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom_uart.vhd":50:4:50:7|Input port bits 10 to 0 of apbi(117 downto 0) are unused

@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom.vhd":147:8:147:9|Trying to extract state machine for register r.state

Extracted state machine for register r.state

State machine has 6 reachable states with original encodings of:

000001

000010

000100

001000

010000

100000

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom.vhd":40:6:40:9|Input port bits 14 to 3 of dmao(46 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom.vhd":40:6:40:9|Input port bit 0 of dmao(46 downto 0) is unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom.vhd":42:6:42:10|Input port bit 4 of uarto(12 downto 0) is unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom.vhd":42:6:42:10|Input port bit 1 of uarto(12 downto 0) is unused

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\dcom.vhd":43:6:43:9|Input ahbi is unused

@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":222:8:222:9|Trying to extract state machine for register r.state

Extracted state machine for register r.state

State machine has 3 reachable states with original encodings of:

00

01

10

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 103 to 94 of ahbi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 92 to 89 of ahbi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 56 to 51 of ahbi(139 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bit 49 of ahbi(139 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 47 to 36 of ahbi(139 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bit 15 of ahbi(139 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":61:4:61:7|Input port bits 13 to 0 of ahbi(139 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 0 to 3 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 132 to 135 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 264 to 267 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 396 to 399 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 528 to 531 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 660 to 663 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 792 to 795 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 924 to 927 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1056 to 1059 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1188 to 1191 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1320 to 1323 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1452 to 1455 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1584 to 1587 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1716 to 1719 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1848 to 1851 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\grlib\amba\apbctrl.vhd":64:4:64:7|Input port bits 1980 to 1983 of apbo(0 to 2111) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 117 to 82 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 48 to 24 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 15 to 13 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\gptimer.vhd":63:4:63:7|Input port bits 11 to 0 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\gptimer.vhd":65:4:65:7|Input port bits 2 to 1 of gpti(2 downto 0) are unused

@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Trying to extract state machine for register r.txstate

Extracted state machine for register r.txstate

State machine has 4 reachable states with original encodings of:

00

01

10

11

@N: CL201 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Trying to extract state machine for register r.rxstate

Extracted state machine for register r.rxstate

State machine has 5 reachable states with original encodings of:

00001

00010

00100

01000

10000

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 117 to 65 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 48 to 25 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused

@W: CL247 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bit 15 of apbi(117 downto 0) is unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\uart\apbuart.vhd":62:4:62:7|Input port bits 13 to 0 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 117 to 57 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 48 to 23 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 18 to 17 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 15 to 5 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":63:4:63:7|Input port bits 3 to 0 of apbi(117 downto 0) are unused

@W: CL246 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\..\..\lib\gaisler\misc\grgpio.vhd":65:4:65:8|Input port bits 95 to 7 of gpioi(95 downto 0) are unused

@W: CL157 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":154:3:154:15|Output led has undriven bits - a simulation mismatch is possible

@W: CL159 :"C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\leon3mp.vhd":59:4:59:8|Input urxd1 is unused

@END

Process took 0h:00m:34s realtime, 0h:00m:33s cputime

# Tue Jul 24 16:57:33 2012

###########################################################]

Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00

Product Version E-2010.09A-1

@N: MF249 |Running in 32-bit mode.

@N: MF258 |Gated clock conversion disabled

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":154:3:154:15|tristate driver led_4 on net led_4 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":154:3:154:15|tristate driver led_3 on net led_3 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":154:3:154:15|tristate driver led_2 on net led_2 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":154:3:154:15|tristate driver led_1 on net led_1 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri31 on net gpioi_tri31 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri30 on net gpioi_tri30 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri29 on net gpioi_tri29 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri28 on net gpioi_tri28 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri27 on net gpioi_tri27 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri26 on net gpioi_tri26 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri25 on net gpioi_tri25 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri24 on net gpioi_tri24 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri23 on net gpioi_tri23 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri22 on net gpioi_tri22 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri21 on net gpioi_tri21 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri20 on net gpioi_tri20 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri19 on net gpioi_tri19 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri18 on net gpioi_tri18 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri17 on net gpioi_tri17 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri16 on net gpioi_tri16 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri15 on net gpioi_tri15 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri14 on net gpioi_tri14 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri13 on net gpioi_tri13 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri12 on net gpioi_tri12 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri11 on net gpioi_tri11 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri10 on net gpioi_tri10 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri9 on net gpioi_tri9 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri8 on net gpioi_tri8 has its enable tied to GND (module leon3mp)

@W: MO111 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\leon3mp.vhd":180:20:180:23|tristate driver gpioi_tri7 on net gpioi_tri7 has its enable tied to GND (module leon3mp)

@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Sequential instance ua1.uart1.r\.extclk has been reduced to a combinational gate by constant propagation

@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Sequential instance mctrl2.sr1.r\.bexcn has been reduced to a combinational gate by constant propagation

@W: MO171 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Sequential instance mctrl2.sr1.r\.brdyn has been reduced to a combinational gate by constant propagation

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.echeck of view:PrimLib.sdffr(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance mctrl2\.sr1.rbdrive[31:0] of view:PrimLib.dffs(prim) because there are no references to its outputs

Available hyper_sources - for debug and ip models

None Found

@W:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd":124:4:124:7|Net ramclk appears to be a clock source which was not identfied. Assuming default frequency.

Finished RTL optimizations (Time elapsed 0h:00m:07s; Memory used current: 79MB peak: 84MB)

@N: MF176 |Default generator successful

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[0] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[1] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[2] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[3] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[4] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[5] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[6] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[7] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[8] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[9] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[10] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[11] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[15] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[16] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[17] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[18] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[19] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[20] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[21] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[22] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[23] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[25] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[26] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[27] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[28] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[29] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[30] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatam[31] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Sequential instance mctrl2.sr1.r.hresp[1] has been reduced to a combinational gate by constant propagation

@W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit mctrl2\.sr1.r\.hburst[2] is always 0, optimizing ...

@W: MO161 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Register bit mctrl2\.sr1.r\.hburst[1] is always 0, optimizing ...

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance mctrl2\.sr1.r\.romsn[1] of view:PrimLib.dffs(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Boundary register mctrl2\.sr1.r\.romsn[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance mctrl2\.sr1.r\.ramsn[1] of view:PrimLib.dffs(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Boundary register mctrl2\.sr1.r\.ramsn[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Removing sequential instance mctrl2\.sr1.r\.ramoen[1] of view:PrimLib.dffs(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1014:4:1014:5|Boundary register mctrl2\.sr1.r\.ramoen[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.address[31] of view:PrimLib.dff(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Boundary register mctrl2\.sr1.r\.address[31] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.address[30] of view:PrimLib.dff(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Boundary register mctrl2\.sr1.r\.address[30] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.address[29] of view:PrimLib.dff(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Boundary register mctrl2\.sr1.r\.address[29] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.address[28] of view:PrimLib.dff(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Boundary register mctrl2\.sr1.r\.address[28] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.address[27] of view:PrimLib.dff(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Boundary register mctrl2\.sr1.r\.address[27] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.address[26] of view:PrimLib.dff(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Boundary register mctrl2\.sr1.r\.address[26] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.address[25] of view:PrimLib.dff(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Boundary register mctrl2\.sr1.r\.address[25] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.address[24] of view:PrimLib.dff(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Boundary register mctrl2\.sr1.r\.address[24] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.address[23] of view:PrimLib.dff(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Boundary register mctrl2\.sr1.r\.address[23] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.address[22] of view:PrimLib.dff(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Boundary register mctrl2\.sr1.r\.address[22] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Removing sequential instance mctrl2\.sr1.r\.address[21] of view:PrimLib.dff(prim) because there are no references to its outputs

@A: BN291 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\esa\memoryctrl\mctrl.vhd":1010:4:1010:5|Boundary register mctrl2\.sr1.r\.address[21] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r\.hmasterlockd of view:PrimLib.dff(prim) because there are no references to its outputs

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[0] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[18] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[19] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[20] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[21] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[22] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[23] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[25] has been reduced to a combinational gate by constant propagation

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Sequential instance ahb0.r.hrdatas[27] has been reduced to a combinational gate by constant propagation

Encoding state machine gaisler.iu3(rtl)-r\.x\.rstate[0:3]

original code -> new code

00 -> 00

01 -> 01

10 -> 10

11 -> 11

@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un6_fe_npc_2[29:0]'

@N: MF176 |Default generator successful

@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un6_fe_npc_0[29:0]'

@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un6_fe_npc_1[29:0]'

@N: MF176 |Default generator successful

@N: MF179 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":392:9:392:30|Found 4 bit by 4 bit '<' comparator, 'comb\.irq_trap\.op_gt\.un2_irl'

Encoding state machine gaisler.mmu_icache(rtl)-r\.istate[0:2]

original code -> new code

00 -> 00

10 -> 01

11 -> 10

@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 8 bit incrementor, 'un1_r\.faddr[1:8]'

Encoding state machine gaisler.mmu_dcache(rtl)-r\.dstate[0:5]

original code -> new code

000000001 -> 000001

000000010 -> 000010

000001000 -> 000100

001000000 -> 001000

010000000 -> 010000

100000000 -> 100000

@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 8 bit incrementor, 'un1_r\.faddr[1:8]'

Encoding state machine gaisler.mmu_acache(rtl)-r\.bo[0:3]

original code -> new code

00 -> 00

01 -> 01

10 -> 10

11 -> 11

@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Found counter in view:gaisler.dsu3x(rtl) inst r\.cnt[2:0]

@N: MF176 |Default generator successful

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Sequential instance l3.dsugen.dsu0.x0.r.dsuen[0] has been reduced to a combinational gate by constant propagation

Encoding state machine gaisler.dcom_uart(rtl)-r\.txstate[0:2]

original code -> new code

00 -> 00

01 -> 01

10 -> 10

Encoding state machine gaisler.dcom_uart(rtl)-r\.rxstate[0:3]

original code -> new code

00 -> 00

01 -> 01

10 -> 10

11 -> 11

@N: MF179 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":392:9:392:30|Found 14 bit by 14 bit '<' comparator, 'uartop\.op_gt\.v\.brate2'

Encoding state machine gaisler.dcom(struct)-r\.state[0:5]

original code -> new code

000001 -> 000001

000010 -> 000010

000100 -> 000100

001000 -> 001000

010000 -> 010000

100000 -> 100000

@N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 6 bit decrementor, 'un5_newlen[5:0]'

@N: MF238 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":299:28:299:42|Found 30 bit incrementor, 'un5_newaddr[29:0]'

Encoding state machine grlib.apbctrl(rtl)-r\.state[0:2]

original code -> new code

00 -> 00

01 -> 01

10 -> 10

@N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 9 bit decrementor, 'un6_scaler[8:0]'

@N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 32 bit decrementor, 'un12_res[31:0]'

@N:"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Found counter in view:gaisler.apbuart(rtl) inst r\.irqcnt[5:0]

Encoding state machine gaisler.apbuart(rtl)-r\.txstate[0:3]

original code -> new code

00 -> 00

01 -> 01

10 -> 10

11 -> 11

Encoding state machine gaisler.apbuart(rtl)-r\.rxstate[0:4]

original code -> new code

00001 -> 00001

00010 -> 00010

00100 -> 00100

01000 -> 01000

10000 -> 10000

@N: MF239 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\stdlib\stdlib.vhd":345:28:345:42|Found 12 bit decrementor, 'un4_scaler[11:0]'

@W: MO129 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Sequential instance ua1.uart1.r.ctsn[0] has been reduced to a combinational gate by constant propagation

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[3], because it is equivalent to instance ahb0.r.hrdatas[2]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatam[24], because it is equivalent to instance ahb0.r.hrdatam[13]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatam[13], because it is equivalent to instance ahb0.r.hrdatam[12]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[6], because it is equivalent to instance ahb0.r.hrdatas[4]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[7], because it is equivalent to instance ahb0.r.hrdatas[4]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[8], because it is equivalent to instance ahb0.r.hrdatas[4]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[9], because it is equivalent to instance ahb0.r.hrdatas[4]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[11], because it is equivalent to instance ahb0.r.hrdatas[4]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[10], because it is equivalent to instance ahb0.r.hrdatas[4]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\ahbctrl.vhd":664:4:664:5|Removing sequential instance ahb0.r.hrdatas[17], because it is equivalent to instance ahb0.r.hrdatas[16]

Auto Dissolve of l3\.cpu\.0\.u0 (inst of view:gaisler.leon3s(rtl))

Finished factoring (Time elapsed 0h:00m:24s; Memory used current: 124MB peak: 125MB)

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\misc\ahbmst.vhd":166:10:166:11|Removing sequential instance dcomgen\.dcom0.ahbmst0.r\.start of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Removing sequential instance ua1\.uart1.r\.rtsn of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\misc\gptimer.vhd":282:8:282:9|Removing sequential instance gpt\.timer0.r\.wdog of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\misc\gptimer.vhd":282:8:282:9|Removing sequential instance gpt\.timer0.r\.wdogn of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\apbctrl.vhd":222:8:222:9|Removing sequential instance apb0.r\.haddr[1] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\grlib\amba\apbctrl.vhd":222:8:222:9|Removing sequential instance apb0.r\.haddr[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\irqmp.vhd":316:8:316:9|Removing sequential instance irqctrl\.irqctrl0.r\.cpurst[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\dsu3x.vhd":645:4:645:5|Removing sequential instance l3\.dsugen\.dsu0.x0.r\.pwd[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[3] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[2] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[1] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.wb\.asi[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.asi[4] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.asi[1] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[31] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[30] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[29] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[28] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[27] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[26] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[25] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[24] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[23] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[22] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[21] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[20] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[19] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[18] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[17] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[16] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[15] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[14] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[13] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[12] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[11] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[10] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[9] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[8] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[7] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[6] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[5] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[4] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[3] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[2] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[1] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.vaddr[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.diag_op of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dlock of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_dcache.vhd":1534:10:1534:11|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.su of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\mmu_icache.vhd":687:8:687:9|Removing sequential instance l3\.cpu\.0\.u0.p0.c0mmu.icache0.r\.su of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[31] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[30] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[29] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[28] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[27] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[26] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[25] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[24] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[23] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[22] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[21] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[20] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[19] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[18] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[17] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[16] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[15] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[14] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[13] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[12] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[11] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[10] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[9] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[8] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[7] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[6] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[5] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[4] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[3] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[2] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[1] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.w\.s\.asr18[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.dci\.asi[7] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.dci\.asi[6] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.dci\.asi[5] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[4] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[3] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[2] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[1] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.rs1[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[18] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[17] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[14] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[13] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[12] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[11] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[10] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[9] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[8] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[7] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[6] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[5] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.a\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[13] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[12] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[11] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[10] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.e\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.cnt[1] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.x\.ctrl\.cnt[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[18] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[17] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[16] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[15] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[14] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[13] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[12] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[11] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[10] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[9] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[8] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[7] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[6] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[5] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[4] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[3] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[2] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[1] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.ctrl\.inst[0] of view:PrimLib.dff(prim) because there are no references to its outputs

@N: BN116 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\leon3\iu3.vhd":2997:4:2997:5|Removing sequential instance l3\.cpu\.0\.u0.p0.iu0.r\.m\.su of view:PrimLib.dff(prim) because there are no references to its outputs

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\uart\dcom_uart.vhd":324:8:324:9|Removing sequential instance dcomgen.dcom0.dcom_uart0.r.rxf[0], because it is equivalent to instance ua1.uart1.r.rxf[0]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[0], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[0]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[1], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[1]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[2], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[2]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[3], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[3]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[4], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[4]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[5], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[5]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.raddr[6], because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfa2[6]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[0], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[0]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[1], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[1]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[2], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[2]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[3], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[3]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[4], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[4]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[5], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[5]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.waddr[6], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.waddr[6]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[0], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[0]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[1], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[1]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[2], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[2]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[3], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[3]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[4], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[4]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[5], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[5]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[6], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[6]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[7], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[7]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[8], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[8]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[9], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[9]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[10], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[10]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[11], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[11]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[12], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[12]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[13], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[13]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[14], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[14]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[15], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[15]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[16], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[16]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[17], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[17]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[18], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[18]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[19], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[19]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[20], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[20]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[21], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[21]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[22], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[22]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[23], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[23]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[24], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[24]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[25], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[25]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[26], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[26]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[27], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[27]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[28], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[28]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[29], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[29]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[30], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[30]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.datain[31], because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.datain[31]

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.renable, because it is equivalent to instance l3.cpu.0.u0.p0.iu0.r.a.rfe2

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\techmap\maps\syncram_2p.vhd":114:10:114:11|Removing sequential instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.r.write, because it is equivalent to instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.r.write

@W: BN132 :"c:\opt\grlib\grlib-gpl-1.1.0-b4108\designs\projet-blanc-m7a3p1k\..\..\lib\gaisler\uart\apbuart.vhd":537:8:537:9|Removing sequential instance ua1.uart1.r.rxf[1], because it is equivalent to instance dcomgen.dcom0.dcom_uart0.r.rxf[1]

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:24s; Memory used current: 118MB peak: 125MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:33s; Memory used current: 122MB peak: 130MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:34s; Memory used current: 124MB peak: 130MB)

Finished Early Timing Optimization (Time elapsed 0h:01m:45s; Memory used current: 119MB peak: 133MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:01m:46s; Memory used current: 116MB peak: 133MB)

Finished preparing to map (Time elapsed 0h:02m:05s; Memory used current: 171MB peak: 173MB)

High Fanout Net Report

**********************

Driver Instance / Pin Name Fanout, notes

--------------------------------------------------------------------------------------------------------------------------------

rst0.rstoutl / Q 271 : 17 asynchronous set/reset

ahb0.r.hmaster[0] / Q 42

dcomgen.dcom0.dcom_uart0.uartop.tmp / Y 59

apb0.r.haddr[2] / Q 76

apb0.r.haddr[3] / Q 30

apb0.r.pwdata[1] / Q 26

apb0.r.pwdata[2] / Q 25

apb0.r.pwdata[3] / Q 27

apb0.r.pwdata[4] / Q 28

apb0.r.pwdata[5] / Q 27

ahb0.r.cfgsel / Q 30

ahb0.r.hslave[0] / Q 40

ahb0.r.hslave[1] / Q 36

ahb0.r.hmasterd[0] / Q 32

l3.cpu.0.u0.rst / Q 167

l3.cpu.0.u0.p0.holdn / Y 808

l3.cpu.0.u0.p0.c0mmu.icache0.r.flush2 / Q 38

l3.cpu.0.u0.p0.c0mmu.dcache0.r.flush / Q 42

l3.cpu.0.u0.p0.iu0.r.d.inst_0[12] / Q 26

l3.cpu.0.u0.p0.iu0.r.d.inst_0[21] / Q 34

gpt.timer0.r.tsel[0] / Q 37

gpt.timer0.v.timers_1.value_2_sqmuxa / Y 32

gpt.timer0.v.timers_2.value_2_sqmuxa / Y 32

gpt.timer0.v.timers_2.value_1_sqmuxa / Y 33

gpt.timer0.comb.1.readdata_9_sn_m3 / Y 32

gpt.timer0.v.timers_2.value_0_sqmuxa / Y 33

gpt.timer0.readdata_1_sqmuxa_1 / Y 33

gpt.timer0.v.timers_1.value_1_sqmuxa / Y 33

gpio0.grgpio0.comb.readdata15 / Y 25

apb0.comb.v.prdata_1_0_a2_2[13] / Y 32

dcomgen.dcom0.dcom0.r.state[4] / Q 38

dcomgen.dcom0.dcom0.r.state[3] / Q 37

dcomgen.dcom0.dcom0.un1_v.data_0_sqmuxa_0_0 / Y 32

dcomgen.dcom0.dcom0.un1_r.state_4_0_0_0 / Y 31

dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_2[6] / Y 30

dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_3[6] / Y 30

irqctrl.irqctrl0.v.ipend_1_sqmuxa_i_o2_0_o2 / Y 25

l3.dsugen.dsu0.x0.un1_v.cnt3_2_1 / Y 32

l3.dsugen.dsu0.x0.comb.v.slv.hready33_0_o3 / Y 33

l3.dsugen.dsu0.x0.v.bmsk_1_sqmuxa_2_i_o2 / Y 35

l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp / Y 32

l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp / Y 32

l3.cpu.0.u0.p0.iu0.r.m.dci.dsuen / Q 28

l3.cpu.0.u0.p0.c0mmu.icache0.r.istate_tr3_1 / Y 39

l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.read_1 / Y 39

l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[0] / Y 39

l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[1] / Y 38

l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate[4] / Q 70

l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.mexc_0_sqmuxa / Y 32

l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.wb.data2_0_sqmuxa / Y 69

l3.cpu.0.u0.p0.c0mmu.dcache0.rdatav_0_1_sqmuxa_1_a2_0_a2 / Y 32

l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s0 / Y 32

l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s1 / Y 32

l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate_i[5] / Q 31

l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.data1_0_sqmuxa_i_o2_0 / Y 33

l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.v.xaddress_2_i_o2[4] / Y 39

l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.read_0_sqmuxa_1_0_o2 / Y 35

l3.cpu.0.u0.p0.c0mmu.dcache0.N_2456_i_i_o2 / Y 34

l3.cpu.0.u0.p0.c0mmu.dcache0.N_73_i_0_o2 / Y 59

l3.cpu.0.u0.p0.c0mmu.icache0.diagen_0_sqmuxa / Y 40

l3.cpu.0.u0.p0.c0mmu.icache0.r.istate[0] / Q 45

l3.cpu.0.u0.p0.iu0.r.x.npc[0] / Q 35

l3.cpu.0.u0.p0.iu0.r.x.npc[1] / Q 65

l3.cpu.0.u0.p0.iu0.r.a.rsel1[0] / Q 33

l3.cpu.0.u0.p0.iu0.r.a.rsel1[1] / Q 65

l3.cpu.0.u0.p0.iu0.r.a.rsel1[2] / Q 97

l3.cpu.0.u0.p0.iu0.r.e.aluop[0] / Q 46

l3.cpu.0.u0.p0.iu0.r.e.aluop[1] / Q 72

l3.cpu.0.u0.p0.iu0.r.e.aluop[2] / Q 42

l3.cpu.0.u0.p0.iu0.r.a.rsel2[0] / Q 33

l3.cpu.0.u0.p0.iu0.r.a.rsel2[1] / Q 66

l3.cpu.0.u0.p0.iu0.r.a.rsel2[2] / Q 97

l3.cpu.0.u0.p0.iu0.r.e.ldbp2 / Q 70

l3.cpu.0.u0.p0.iu0.r.e.invop2 / Q 64

l3.cpu.0.u0.p0.iu0.comb.diagread.un497_dbgunit / Y 35

l3.cpu.0.u0.p0.iu0.comb.logic_op.un1_r.e.mulstep / Y 32

l3.cpu.0.u0.p0.iu0.r.x.ctrl.ld / Q 33

l3.cpu.0.u0.p0.iu0.r.e.ldbp1 / Q 157

l3.cpu.0.u0.p0.iu0.comb.diagread.un462_dbgunit / Y 44

l3.cpu.0.u0.p0.iu0.comb.lock_gen.call_hold5_0_a2 / Y 35

l3.cpu.0.u0.p0.iu0.comb.alu_op.y08 / Y 32

l3.cpu.0.u0.p0.iu0.un1_r.x.ctrl.wy_1 / Y 32

l3.cpu.0.u0.p0.iu0.un1_r.e.ctrl.wy_1 / Y 32

l3.cpu.0.u0.p0.iu0.vir.addr_3_sqmuxa / Y 30

l3.cpu.0.u0.p0.iu0.comb.ex_sari_1_1 / Y 31

l3.cpu.0.u0.p0.iu0.data_0_sqmuxa / Y 32

l3.cpu.0.u0.p0.iu0.comb.logic_op.y14 / Y 35

l3.cpu.0.u0.p0.iu0.aluresult_0_sqmuxa_0_a2 / Y 32

l3.cpu.0.u0.p0.iu0.aluresult_3_sqmuxa_0_a2 / Y 32

l3.cpu.0.u0.p0.iu0.vir.addr_1_sqmuxa / Y 30

l3.cpu.0.u0.p0.iu0.vir.addr_2_sqmuxa / Y 30

l3.cpu.0.u0.p0.iu0.aluresult_7_sqmuxa_0_a2 / Y 32

l3.cpu.0.u0.p0.iu0.aluresult_10_sqmuxa_0_a2 / Y 32

l3.cpu.0.u0.p0.iu0.comb.misc_op.bpdata6 / Y 32

l3.cpu.0.u0.p0.iu0.r.e.shleft / Q 63

l3.cpu.0.u0.p0.iu0.edata_3_sqmuxa / Y 32

l3.cpu.0.u0.p0.iu0.fpcwr_6_sqmuxa / Y 28

l3.cpu.0.u0.p0.iu0.data_0_sqmuxa_2 / Y 32

l3.cpu.0.u0.p0.iu0.data_3_sqmuxa_1 / Y 28

l3.cpu.0.u0.p0.iu0.data_4_sqmuxa_1 / Y 30

l3.cpu.0.u0.p0.iu0.mresult2_1_sqmuxa / Y 32

l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_3 / Y 30

l3.cpu.0.u0.p0.iu0.mresult2_2_sqmuxa_1 / Y 32

l3.cpu.0.u0.p0.iu0.aluresult_1_sqmuxa / Y 32

l3.cpu.0.u0.p0.iu0.fpcwr_3_sqmuxa / Y 32

l3.cpu.0.u0.p0.iu0.fpcwr_8_sqmuxa / Y 30

l3.cpu.0.u0.p0.iu0.aluresult_2_sqmuxa / Y 32

l3.cpu.0.u0.p0.iu0.un1_aop2_1_sqmuxa_0 / Y 33

l3.cpu.0.u0.p0.iu0.xc_trap_address_2_sqmuxa / Y 30

l3.cpu.0.u0.p0.iu0.comb.ex_bpmiss / Y 41

l3.cpu.0.u0.p0.iu0.comb.ra_bpmiss_1 / Y 37

l3.cpu.0.u0.p0.iu0.comb.dcache_gen.jump / Y 32

l3.cpu.0.u0.p0.iu0.un1_vir.addr_0_sqmuxa / Y 30

l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_6 / Y 30

l3.cpu.0.u0.p0.iu0.v.w.s.s_3_sqmuxa / Y 42

l3.cpu.0.u0.p0.iu0.v.w.s.y_1_sqmuxa / Y 32

l3.cpu.0.u0.p0.iu0.v.w.s.y_2_sqmuxa / Y 32

l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_8 / Y 39

l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_10 / Y 32

l3.cpu.0.u0.p0.iu0.comb.un6_xc_exception / Y 30

l3.cpu.0.u0.p0.iu0.un2_de_hold_pc / Y 30

l3.cpu.0.u0.p0.iu0.un1_r.d.mexc_1_sqmuxa_1 / Y 33

l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_2_s3 / Y 30

l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_0_s1 / Y 30

l3.cpu.0.u0.p0.iu0.un1_de_branch_1 / Y 30

l3.cpu.0.u0.p0.iu0.un1_de_hold_pc_2 / Y 30

l3.cpu.0.u0.p0.iu0.comb.v.f.pc[10] / Y 30

l3.cpu.0.u0.p0.iu0.comb.dbg_cache.dci2.asis_sn_i0_i_0 / Y 60

l3.cpu.0.u0.p0.iu0.r.x.rstate[1] / Q 36

l3.cpu.0.u0.p0.iu0.r.x.rstate_s1_0_a2 / Y 39

l3.cpu.0.u0.p0.iu0.r.x.rstate_tr4_1 / Y 28

l3.cpu.0.u0.p0.iu0.aop1_1_sqmuxa_i / Y 34

l3.cpu.0.u0.p0.iu0.r.x.mexc_1_sqmuxa_i / Y 34

l3.cpu.0.u0.p0.iu0.un1_r.e.jmpl_i_o2 / Y 30

l3.cpu.0.u0.p0.iu0.comb.un1_r.m.ctrl.ld_i_a2_0 / Y 36

l3.cpu.0.u0.p0.iu0.pc_1_sqmuxa / Y 31

l3.cpu.0.u0.p0.iu0.data_5_sqmuxa / Y 31

l3.cpu.0.u0.p0.iu0.comb.logic_op.logicout_4_0_e[0] / Y 30

ahb0.comb.hready_1_iv / Y 44

gpt.timer0.v.timers_1.reload_1_sqmuxa / Y 32

gpt.timer0.v.timers_2.reload_1_sqmuxa / Y 32

ua1.uart1.v.brate_1_sqmuxa_0_o2 / Y 25

l3.dsugen.dsu0.x0.v.slv.hwrite_0_sqmuxa_i_0_o2 / Y 32

irqctrl.irqctrl0.comb.v.iforce_0_6_sn_m2_0 / Y 26

dcomgen.dcom0.dcom_uart0.uartop.un1_apbi / Y 26

mctrl2.sr1.v.writedata_0_sqmuxa / Y 32

l3.dsugen.dsu0.x0.un1_v.cnt3_i_a2_m1_e / Y 31

apb0.v.pwdata_1_sqmuxa_i_i_a8 / Y 32

dcomgen.dcom0.dcom_uart0.v.brate_0_sqmuxa / Y 38

l3.cpu.0.u0.p0.iu0.comb.un16_casaen_0 / Y 89

l3.cpu.0.u0.p0.iu0.xc_trap_address_1_sqmuxa_0 / Y 32

l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.rdatav_0_1_0_iv_0_a2_0_1[2] / Y 31

l3.cpu.0.u0.p0.c0mmu.a0.r.bo_s2_0_a2 / Y 33

l3.cpu.0.u0.p0.c0mmu.dcache0.N_2439_i_i / Y 25

l3.cpu.0.u0.p0.c0mmu.icache0.cdwrite_0_sqmuxa / Y 32

gpt.timer0.comb.v.timers_2.value_1_sn_m1_0_a2 / Y 32

gpt.timer0.comb.v.timers_1.value_1_sn_m1_0_a2 / Y 32

l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[1] / Y 33

l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[2] / Y 35

l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[3] / Y 39

l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[4] / Y 47

l3.cpu.0.u0.p0.iu0.aluresult_12_sqmuxa_i / Y 27

l3.cpu.0.u0.p0.iu0.aluresult_8_sqmuxa / Y 27

l3.cpu.0.u0.p0.iu0.comb.alu_op.aop2_i_a2_1_o2[24] / Y 33

l3.cpu.0.u0.p0.iu0.r.d.pc_1199_e / Y 31

l3.cpu.0.u0.p0.c0mmu.icache0.v.vaddress_0_sqmuxa_0_a2 / Y 61

================================================================================================================================

@N: FP130 |Promoting Net l3\.cpu\.0\.u0.holdn on CLKINT I_1300

@N: FP130 |Promoting Net rstn on CLKINT I_1301

@N: FP130 |Promoting Net l3\.cpu\.0\.u0.rst on CLKINT I_1302

@N: FP130 |Promoting Net l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1 on CLKINT I_1303

@N: FP130 |Promoting Net l3\.cpu\.0\.u0.p0.iu0.r\.a\.rsel2[2] on CLKINT I_1304

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.v.vaddress_0_sqmuxa_0_a2, fanout 61 segments 3

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.d.pc_1199_e, fanout 31 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.alu_op.aop2_i_a2_1_o2[24], fanout 33 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_8_sqmuxa, fanout 27 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_12_sqmuxa_i, fanout 27 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[4], fanout 47 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[3], fanout 39 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[2], fanout 35 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_shcnt_1[1], fanout 33 segments 2

Replicating Combinational Instance gpt.timer0.comb.v.timers_1.value_1_sn_m1_0_a2, fanout 32 segments 2

Replicating Combinational Instance gpt.timer0.comb.v.timers_2.value_1_sn_m1_0_a2, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.cdwrite_0_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.N_2439_i_i, fanout 25 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.a0.r.bo_s2_0_a2, fanout 33 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.rdatav_0_1_0_iv_0_a2_0_1[2], fanout 31 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.xc_trap_address_1_sqmuxa_0, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.un16_casaen_0, fanout 89 segments 4

Replicating Combinational Instance dcomgen.dcom0.dcom_uart0.v.brate_0_sqmuxa, fanout 38 segments 2

Replicating Combinational Instance apb0.v.pwdata_1_sqmuxa_i_i_a8, fanout 32 segments 2

Replicating Combinational Instance l3.dsugen.dsu0.x0.un1_v.cnt3_i_a2_m1_e, fanout 31 segments 2

Replicating Combinational Instance mctrl2.sr1.v.writedata_0_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance dcomgen.dcom0.dcom_uart0.uartop.un1_apbi, fanout 27 segments 2

Replicating Combinational Instance irqctrl.irqctrl0.comb.v.iforce_0_6_sn_m2_0, fanout 26 segments 2

Replicating Combinational Instance l3.dsugen.dsu0.x0.v.slv.hwrite_0_sqmuxa_i_0_o2, fanout 32 segments 2

Replicating Combinational Instance ua1.uart1.v.brate_1_sqmuxa_0_o2, fanout 25 segments 2

Replicating Combinational Instance gpt.timer0.v.timers_2.reload_1_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance gpt.timer0.v.timers_1.reload_1_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance ahb0.comb.hready_1_iv, fanout 44 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.logic_op.logicout_4_0_e[0], fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_5_sqmuxa, fanout 31 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.pc_1_sqmuxa, fanout 31 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.un1_r.m.ctrl.ld_i_a2_0, fanout 36 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.e.jmpl_i_o2, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.x.mexc_1_sqmuxa_i, fanout 34 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aop1_1_sqmuxa_i, fanout 35 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.x.rstate_tr4_1, fanout 28 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.r.x.rstate_s1_0_a2, fanout 39 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.rstate[1], fanout 38 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.dbg_cache.dci2.asis_sn_i0_i_0, fanout 61 segments 3

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.v.f.pc[10], fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_de_hold_pc_2, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_de_branch_1, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_0_s1, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un6_fe_npcsel_2_s3, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.d.mexc_1_sqmuxa_1, fanout 33 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un2_de_hold_pc, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.un6_xc_exception, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_10, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_8, fanout 39 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.v.w.s.y_2_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.v.w.s.y_1_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.v.w.s.s_3_sqmuxa, fanout 42 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_6, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_vir.addr_0_sqmuxa, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.dcache_gen.jump, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ra_bpmiss_1, fanout 37 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_bpmiss, fanout 42 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.xc_trap_address_2_sqmuxa, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_aop2_1_sqmuxa_0, fanout 33 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_2_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.fpcwr_8_sqmuxa, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.fpcwr_3_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_1_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.mresult2_2_sqmuxa_1, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.rstate_3, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.mresult2_1_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_4_sqmuxa_1, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_3_sqmuxa_1, fanout 28 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_0_sqmuxa_2, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.fpcwr_6_sqmuxa, fanout 28 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.edata_3_sqmuxa, fanout 32 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.shleft, fanout 63 segments 3

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.misc_op.bpdata6, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_10_sqmuxa_0_a2, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_7_sqmuxa_0_a2, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.vir.addr_2_sqmuxa, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.vir.addr_1_sqmuxa, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_3_sqmuxa_0_a2, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.aluresult_0_sqmuxa_0_a2, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.logic_op.y14, fanout 35 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.data_0_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.ex_sari_1_1, fanout 31 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.vir.addr_3_sqmuxa, fanout 30 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.e.ctrl.wy_1, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.un1_r.x.ctrl.wy_1, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.alu_op.y08, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.lock_gen.call_hold5_0_a2, fanout 35 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.diagread.un462_dbgunit, fanout 47 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.ctrl.ld, fanout 33 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.logic_op.un1_r.e.mulstep, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.diagread.un497_dbgunit, fanout 35 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.invop2, fanout 64 segments 3

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.ldbp2, fanout 74 segments 4

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel2[1], fanout 66 segments 3

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel2[0], fanout 33 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.aluop[2], fanout 44 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.aluop[1], fanout 74 segments 4

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.e.aluop[0], fanout 46 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel1[2], fanout 97 segments 5

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel1[1], fanout 65 segments 3

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.rsel1[0], fanout 33 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.npc[1], fanout 68 segments 3

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.x.npc[0], fanout 38 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.icache0.r.istate[0], fanout 45 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.diagen_0_sqmuxa, fanout 41 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.N_73_i_0_o2, fanout 60 segments 3

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.N_2456_i_i_o2, fanout 34 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.read_0_sqmuxa_1_0_o2, fanout 35 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.v.xaddress_2_i_o2[4], fanout 39 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.v.wb.data1_0_sqmuxa_i_o2_0, fanout 33 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate_i[5], fanout 34 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s1, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.edata_0_sqmuxa_s0, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.rdatav_0_1_sqmuxa_1_a2_0_a2, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.wb.data2_0_sqmuxa, fanout 70 segments 3

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.un1_v.mexc_0_sqmuxa, fanout 32 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.dcache0.r.dstate[4], fanout 71 segments 3

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[1], fanout 38 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_iv[0], fanout 39 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.dcache0.dctrl.read_1, fanout 41 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.c0mmu.icache0.r.istate_tr3_1, fanout 42 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.m.dci.dsuen, fanout 28 segments 2

Replicating Combinational Instance l3.cpu.0.u0.rf0.s1.dp.x0.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp, fanout 32 segments 2

Replicating Combinational Instance l3.cpu.0.u0.rf0.s1.dp.x1.wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp, fanout 32 segments 2

Replicating Combinational Instance l3.dsugen.dsu0.x0.v.bmsk_1_sqmuxa_2_i_o2, fanout 36 segments 2

Replicating Combinational Instance l3.dsugen.dsu0.x0.comb.v.slv.hready33_0_o3, fanout 33 segments 2

Replicating Combinational Instance l3.dsugen.dsu0.x0.un1_v.cnt3_2_1, fanout 32 segments 2

Replicating Combinational Instance irqctrl.irqctrl0.v.ipend_1_sqmuxa_i_o2_0_o2, fanout 25 segments 2

Replicating Combinational Instance dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_3[6], fanout 30 segments 2

Replicating Combinational Instance dcomgen.dcom0.dcom0.comb.v.addr_1_i_0_a2_2[6], fanout 30 segments 2

Replicating Combinational Instance dcomgen.dcom0.dcom0.un1_r.state_4_0_0_0, fanout 31 segments 2

Replicating Combinational Instance dcomgen.dcom0.dcom0.un1_v.data_0_sqmuxa_0_0, fanout 32 segments 2

Replicating Sequential Instance dcomgen.dcom0.dcom0.r.state[3], fanout 37 segments 2

Replicating Sequential Instance dcomgen.dcom0.dcom0.r.state[4], fanout 41 segments 2

Replicating Combinational Instance apb0.comb.v.prdata_1_0_a2_2[13], fanout 32 segments 2

Replicating Combinational Instance gpio0.grgpio0.comb.readdata15, fanout 25 segments 2

Replicating Combinational Instance gpt.timer0.v.timers_1.value_1_sqmuxa, fanout 33 segments 2

Replicating Combinational Instance gpt.timer0.readdata_1_sqmuxa_1, fanout 34 segments 2

Replicating Combinational Instance gpt.timer0.v.timers_2.value_0_sqmuxa, fanout 33 segments 2

Replicating Combinational Instance gpt.timer0.comb.1.readdata_9_sn_m3, fanout 32 segments 2

Replicating Combinational Instance gpt.timer0.v.timers_2.value_1_sqmuxa, fanout 33 segments 2

Replicating Combinational Instance gpt.timer0.v.timers_2.value_2_sqmuxa, fanout 32 segments 2

Replicating Combinational Instance gpt.timer0.v.timers_1.value_2_sqmuxa, fanout 32 segments 2

Replicating Sequential Instance gpt.timer0.r.tsel[0], fanout 37 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.d.inst_0[21], fanout 34 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.d.inst_0[12], fanout 26 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.dcache0.r.flush, fanout 42 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.c0mmu.icache0.r.flush2, fanout 38 segments 2

Replicating Sequential Instance ahb0.r.hmasterd[0], fanout 32 segments 2

Replicating Sequential Instance ahb0.r.hslave[1], fanout 36 segments 2

Replicating Sequential Instance ahb0.r.hslave[0], fanout 40 segments 2

Replicating Sequential Instance ahb0.r.cfgsel, fanout 30 segments 2

Replicating Sequential Instance apb0.r.pwdata[5], fanout 27 segments 2

Replicating Sequential Instance apb0.r.pwdata[4], fanout 28 segments 2

Replicating Sequential Instance apb0.r.pwdata[3], fanout 27 segments 2

Replicating Sequential Instance apb0.r.pwdata[2], fanout 25 segments 2

Replicating Sequential Instance apb0.r.pwdata[1], fanout 26 segments 2

Replicating Sequential Instance apb0.r.haddr[3], fanout 31 segments 2

Replicating Sequential Instance apb0.r.haddr[2], fanout 77 segments 4

Replicating Combinational Instance dcomgen.dcom0.dcom_uart0.uartop.tmp, fanout 59 segments 3

Replicating Sequential Instance ahb0.r.hmaster[0], fanout 43 segments 2

Replicating Combinational Instance l3.cpu.0.u0.p0.iu0.comb.un16_casaen_0_2, fanout 25 segments 2

Replicating Combinational Instance apb0.v.hready_0_sqmuxa_0_a3_0_a2, fanout 26 segments 2

Replicating Sequential Instance l3.cpu.0.u0.p0.iu0.r.a.ctrl.inst[21], fanout 25 segments 2

Finished technology mapping (Time elapsed 0h:02m:11s; Memory used current: 143MB peak: 208MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:02m:13s; Memory used current: 143MB peak: 208MB)

Added 0 Buffers

Added 186 Cells via replication

Added 54 Sequential Cells via replication

Added 132 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:02m:14s; Memory used current: 146MB peak: 208MB)

Writing Analyst data base C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\designs\Projet-Blanc-M7A3P1K\synthesis\leon3mp.srm

Finished Writing Netlist Databases (Time elapsed 0h:02m:16s; Memory used current: 134MB peak: 208MB)

Writing EDIF Netlist and constraint files

E-2010.09A-1

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:02m:19s; Memory used current: 139MB peak: 208MB)

@W: MT420 |Found inferred clock leon3mp|clk50MHz with period 10.00ns. A user-defined clock should be declared on object "p:clk50MHz"

@W: MT420 |Found inferred clock leon3mp|clkgen0.ap3_v.ramclk_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:ramclk"

##### START OF TIMING REPORT #####[

# Timing Report written on Tue Jul 24 16:59:54 2012

#

Top view: leon3mp

Library name: PA3

Operating conditions: COMWC-2 ( T = 70.0, V = 1.42, P = 1.30, tree_type = balanced_tree )

Requested Frequency: 100.0 MHz

Wire load mode: top

Wire load model: proasic3

Paths requested: 5

Constraint File(s):

@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..

Performance Summary

*******************

Worst slack in design: -14.774

Requested Estimated Requested Estimated Clock Clock

Starting Clock Frequency Frequency Period Period Slack Type Group

----------------------------------------------------------------------------------------------------------------------------------------------------

leon3mp|clk50MHz 100.0 MHz 537.7 MHz 10.000 1.860 8.140 inferred Inferred_clkgroup_0

leon3mp|clkgen0.ap3_v.ramclk_inferred_clock 100.0 MHz 40.4 MHz 10.000 24.773 -14.774 inferred Inferred_clkgroup_1

====================================================================================================================================================

Clock Relationships

*******************

Clocks | rise to rise | fall to fall | rise to fall | fall to rise

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

==================================================================================================================================================================================

Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.

'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

Interface Information

*********************

No IO constraint found

====================================

Detailed Report for Clock: leon3mp|clk50MHz

====================================

Starting Points with Worst Slack

********************************

Starting Arrival

Instance Reference Type Pin Net Time Slack

Clock

-----------------------------------------------------------------------------

lclk leon3mp|clk50MHz DFN1 Q lclk 0.550 8.140

=============================================================================

Ending Points with Worst Slack

******************************

Starting Required

Instance Reference Type Pin Net Time Slack

Clock

--------------------------------------------------------------------------------

lclk leon3mp|clk50MHz DFN1 D lclk_i 9.598 8.140

================================================================================

Worst Path Information

***********************

Path information for path number 1:

Requested Period: 10.000

- Setup time: 0.402

+ Clock delay at ending point: 0.000 (ideal)

= Required time: 9.598

- Propagation time: 1.458

- Clock delay at starting point: 0.000 (ideal)

= Slack (non-critical) : 8.140

Number of logic level(s): 1

Starting point: lclk / Q

Ending point: lclk / D

The start point is clocked by leon3mp|clk50MHz [rising] on pin CLK

The end point is clocked by leon3mp|clk50MHz [rising] on pin CLK

Instance / Net Pin Pin Arrival No. of

Name Type Name Dir Delay Time Fan Out(s)

-----------------------------------------------------------------------------

lclk DFN1 Q Out 0.550 0.550 -

lclk Net - - 0.288 - 2

lclk_RNO INV A In - 0.839 -

lclk_RNO INV Y Out 0.379 1.218 -

lclk_i Net - - 0.240 - 1

lclk DFN1 D In - 1.458 -

=============================================================================

Total path delay (propagation time + setup) of 1.860 is 1.332(71.6%) logic and 0.528(28.4%) route.

Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

====================================

Detailed Report for Clock: leon3mp|clkgen0.ap3_v.ramclk_inferred_clock

====================================

Starting Points with Worst Slack

********************************

Starting Arrival

Instance Reference Type Pin Net Time Slack

Clock

------------------------------------------------------------------------------------------------------------------------------------------------

l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[11] leon3mp|clkgen0.ap3_v.ramclk_inferred_clock DFN1E1 Q data_0[11] 0.550 -14.774

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1 leon3mp|clkgen0.ap3_v.ramclk_inferred_clock DFN1E0 Q ldbp1_0 0.550 -14.619

l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[7] leon3mp|clkgen0.ap3_v.ramclk_inferred_clock DFN1E1 Q data_0[7] 0.550 -14.527

l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[3] leon3mp|clkgen0.ap3_v.ramclk_inferred_clock DFN1E1 Q data_0[3] 0.550 -14.485

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1[11] leon3mp|clkgen0.ap3_v.ramclk_inferred_clock DFN1E0 Q op1[11] 0.550 -14.466

l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[6] leon3mp|clkgen0.ap3_v.ramclk_inferred_clock DFN1E1 Q data_0[6] 0.550 -14.311

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1[7] leon3mp|clkgen0.ap3_v.ramclk_inferred_clock DFN1E0 Q op1[7] 0.550 -14.253

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1[3] leon3mp|clkgen0.ap3_v.ramclk_inferred_clock DFN1E0 Q op1[3] 0.550 -14.211

l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[0] leon3mp|clkgen0.ap3_v.ramclk_inferred_clock DFN1E1 Q data_0[0] 0.550 -14.017

l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[14] leon3mp|clkgen0.ap3_v.ramclk_inferred_clock DFN1E1 Q data_0[14] 0.434 -13.997

================================================================================================================================================

Ending Points with Worst Slack

******************************

Starting Required

Instance Reference Type Pin Net Time Slack

Clock

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 leon3mp|clkgen0.ap3_v.ramclk_inferred_clock RAM512X18 WD10 xaddress_RNIE9I8VM1[18] 9.895 -14.774

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 leon3mp|clkgen0.ap3_v.ramclk_inferred_clock RAM512X18 WD9 xaddress_RNI1HH8VM1[17] 9.895 -14.450

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 leon3mp|clkgen0.ap3_v.ramclk_inferred_clock RAM512X18 WD15 xaddress_RNIFBR7VM1[23] 9.895 -14.450

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 leon3mp|clkgen0.ap3_v.ramclk_inferred_clock RAM512X18 WD8 xaddress_RNIH8G8VM1[16] 9.895 -14.432

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 leon3mp|clkgen0.ap3_v.ramclk_inferred_clock RAM512X18 WD12 newptag_2[20] 9.856 -14.292

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.1\.u0.u0 leon3mp|clkgen0.ap3_v.ramclk_inferred_clock RAM512X18 WD3 vdtdatain_0_1[21] 9.895 -14.247

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 leon3mp|clkgen0.ap3_v.ramclk_inferred_clock RAM512X18 WD13 xaddress_RNID0H8VM1[21] 9.895 -14.247

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 leon3mp|clkgen0.ap3_v.ramclk_inferred_clock RAM512X18 WD14 xaddress_RNIQOH8VM1[22] 9.895 -14.247

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.1\.u0.u0 leon3mp|clkgen0.ap3_v.ramclk_inferred_clock RAM512X18 WD2 vdtdatain_0_1[20] 9.895 -13.906

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.1\.u0.u0 leon3mp|clkgen0.ap3_v.ramclk_inferred_clock RAM512X18 WD5 vdtdatain_0_1[23] 9.895 -13.906

==============================================================================================================================================================================================================

Worst Path Information

***********************

Path information for path number 1:

Requested Period: 10.000

- Setup time: 0.105

+ Clock delay at ending point: 0.000 (ideal)

= Required time: 9.895

- Propagation time: 24.668

- Clock delay at starting point: 0.000 (ideal)

= Slack (critical) : -14.773

Number of logic level(s): 24

Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[11] / Q

Ending point: l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 / WD10

The start point is clocked by leon3mp|clkgen0.ap3_v.ramclk_inferred_clock [rising] on pin CLK

The end point is clocked by leon3mp|clkgen0.ap3_v.ramclk_inferred_clock [rising] on pin WCLK

Instance / Net Pin Pin Arrival No. of

Name Type Name Dir Delay Time Fan Out(s)

------------------------------------------------------------------------------------------------------------------------------------------------------

l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[11] DFN1E1 Q Out 0.550 0.550 -

data_0[11] Net - - 1.589 - 15

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIQCHD[11] MX2 B In - 2.139 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIQCHD[11] MX2 Y Out 0.427 2.566 -

op1_RNIQCHD[11] Net - - 1.555 - 14

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I12_G0N NOR2A A In - 4.121 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I12_G0N NOR2A Y Out 0.469 4.590 -

N430 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I71_Y_0 OR2 A In - 4.878 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I71_Y_0 OR2 Y Out 0.379 5.257 -

N530 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_un1_Y AO1C C In - 5.497 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_un1_Y AO1C Y Out 0.472 5.969 -

I129_un1_Y Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_Y OR2B B In - 6.209 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_Y OR2B Y Out 0.386 6.595 -

N592 Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_un1_Y NOR3A A In - 7.197 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_un1_Y NOR3A Y Out 0.479 7.676 -

I181_un1_Y Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_Y OR2 B In - 7.916 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_Y OR2 Y Out 0.483 8.399 -

N650_1 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y_0 AO1 C In - 8.687 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y_0 AO1 Y Out 0.472 9.160 -

ADD_33x33_fast_I272_Y_0 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I270_Y_0_a3 OAI1 B In - 9.448 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I270_Y_0_a3 OAI1 Y Out 0.414 9.862 -

N_71_i_1 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I270_Y_0_o3 OR2A A In - 10.102 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I270_Y_0_o3 OR2A Y Out 0.401 10.503 -

N786_1 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I311_Y_0 XNOR2 A In - 10.743 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I311_Y_0 XNOR2 Y Out 0.305 11.048 -

un6_ex_add_res_s0[21] Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.invop2_1_RNI18MQG1 MX2C B In - 11.288 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.invop2_1_RNI18MQG1 MX2C Y Out 0.427 11.715 -

N_8118 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNI78TJG2 MX2C B In - 11.955 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNI78TJG2 MX2C Y Out 0.437 12.393 -

eaddress[20] Net - - 0.884 - 4

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_0_RNIK8SN18 NOR3 C In - 13.277 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_0_RNIK8SN18 NOR3 Y Out 0.561 13.837 -

un1_addout_28_10_6 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIVJ4EBL NOR3B A In - 14.077 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIVJ4EBL NOR3B Y Out 0.497 14.574 -

un1_addout_28_10_9 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNID6SO1P OR2A A In - 14.815 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNID6SO1P OR2A Y Out 0.401 15.216 -

un1_addout_28_10 Net - - 1.327 - 11

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_2_a2_25_m2_e_0 OR2A B In - 16.542 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_2_a2_25_m2_e_0 OR2A Y Out 0.483 17.025 -

un1_addout_28 Net - - 0.955 - 5

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIQ1LUSN1_0 NOR2 A In - 17.980 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIQ1LUSN1_0 NOR2 Y Out 0.379 18.359 -

newptag_2_a2_3_a0_1[22] Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_sn_m2_i_o2_m4_0_a3_0_0 OR2 B In - 18.962 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_sn_m2_i_o2_m4_0_a3_0_0 OR2 Y Out 0.384 19.346 -

newptag_sn_m2_i_o2_m4_0_a3_0_0 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI0SALQP1_0 OR2 A In - 19.586 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI0SALQP1_0 OR2 Y Out 0.271 19.857 -

newptag_sn_m2_i_o2_N_8 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI2N6NQR1 OR2B A In - 20.097 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI2N6NQR1 OR2B Y Out 0.365 20.462 -

flush_0_RNI2N6NQR1 Net - - 1.690 - 18

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNI9NANQR1[4] NOR2A A In - 22.152 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNI9NANQR1[4] NOR2A Y Out 0.469 22.620 -

N_2867 Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNII7IOQR1[4] OR2B B In - 23.223 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNII7IOQR1[4] OR2B Y Out 0.469 23.691 -

N_2783 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNIE9I8VM1[18] OR3C C In - 23.931 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNIE9I8VM1[18] OR3C Y Out 0.497 24.428 -

xaddress_RNIE9I8VM1[18] Net - - 0.240 - 1

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 RAM512X18 WD10 In - 24.668 -

======================================================================================================================================================

Total path delay (propagation time + setup) of 24.773 is 10.981(44.3%) logic and 13.792(55.7%) route.

Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

Path information for path number 2:

Requested Period: 10.000

- Setup time: 0.105

+ Clock delay at ending point: 0.000 (ideal)

= Required time: 9.895

- Propagation time: 24.606

- Clock delay at starting point: 0.000 (ideal)

= Slack (non-critical) : -14.711

Number of logic level(s): 24

Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[11] / Q

Ending point: l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 / WD10

The start point is clocked by leon3mp|clkgen0.ap3_v.ramclk_inferred_clock [rising] on pin CLK

The end point is clocked by leon3mp|clkgen0.ap3_v.ramclk_inferred_clock [rising] on pin WCLK

Instance / Net Pin Pin Arrival No. of

Name Type Name Dir Delay Time Fan Out(s)

------------------------------------------------------------------------------------------------------------------------------------------------------

l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[11] DFN1E1 Q Out 0.550 0.550 -

data_0[11] Net - - 1.589 - 15

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIQCHD[11] MX2 B In - 2.139 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIQCHD[11] MX2 Y Out 0.427 2.566 -

op1_RNIQCHD[11] Net - - 1.555 - 14

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I12_G0N NOR2A A In - 4.121 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I12_G0N NOR2A Y Out 0.469 4.590 -

N430 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I71_Y_0 OR2 A In - 4.878 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I71_Y_0 OR2 Y Out 0.379 5.257 -

N530 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_un1_Y AO1C C In - 5.497 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_un1_Y AO1C Y Out 0.472 5.969 -

I129_un1_Y Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_Y OR2B B In - 6.209 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_Y OR2B Y Out 0.386 6.595 -

N592 Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_un1_Y NOR3A A In - 7.197 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_un1_Y NOR3A Y Out 0.479 7.676 -

I181_un1_Y Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_Y OR2 B In - 7.916 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_Y OR2 Y Out 0.483 8.399 -

N650_1 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y_0 AO1 C In - 8.687 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y_0 AO1 Y Out 0.472 9.160 -

ADD_33x33_fast_I272_Y_0 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y OR2 B In - 9.448 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y OR2 Y Out 0.483 9.931 -

N790 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I309_Y_0 XNOR2 A In - 10.171 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I309_Y_0 XNOR2 Y Out 0.305 10.476 -

un6_ex_add_res_s0[19] Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.invop2_1_RNIT39KC1 MX2C B In - 10.716 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.invop2_1_RNIT39KC1 MX2C Y Out 0.427 11.143 -

N_8108 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIK2LC92 MX2C B In - 11.383 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIK2LC92 MX2C Y Out 0.437 11.820 -

eaddress[18] Net - - 0.884 - 4

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_0_RNICB2GG6 NOR3 A In - 12.704 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_0_RNICB2GG6 NOR3 Y Out 0.365 13.069 -

un1_addout_28_10_4 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIS33O5A NOR3C C In - 13.309 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIS33O5A NOR3C Y Out 0.497 13.806 -

un1_addout_28_10_7 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIVJ4EBL NOR3B B In - 14.046 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIVJ4EBL NOR3B Y Out 0.466 14.512 -

un1_addout_28_10_9 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNID6SO1P OR2A A In - 14.752 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNID6SO1P OR2A Y Out 0.401 15.153 -

un1_addout_28_10 Net - - 1.327 - 11

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_2_a2_25_m2_e_0 OR2A B In - 16.480 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_2_a2_25_m2_e_0 OR2A Y Out 0.483 16.963 -

un1_addout_28 Net - - 0.955 - 5

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIQ1LUSN1_0 NOR2 A In - 17.918 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIQ1LUSN1_0 NOR2 Y Out 0.379 18.297 -

newptag_2_a2_3_a0_1[22] Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_sn_m2_i_o2_m4_0_a3_0_0 OR2 B In - 18.899 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_sn_m2_i_o2_m4_0_a3_0_0 OR2 Y Out 0.384 19.283 -

newptag_sn_m2_i_o2_m4_0_a3_0_0 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI0SALQP1_0 OR2 A In - 19.523 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI0SALQP1_0 OR2 Y Out 0.271 19.795 -

newptag_sn_m2_i_o2_N_8 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI2N6NQR1 OR2B A In - 20.035 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI2N6NQR1 OR2B Y Out 0.365 20.400 -

flush_0_RNI2N6NQR1 Net - - 1.690 - 18

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNI9NANQR1[4] NOR2A A In - 22.090 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNI9NANQR1[4] NOR2A Y Out 0.469 22.558 -

N_2867 Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNII7IOQR1[4] OR2B B In - 23.160 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNII7IOQR1[4] OR2B Y Out 0.469 23.629 -

N_2783 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNIE9I8VM1[18] OR3C C In - 23.869 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNIE9I8VM1[18] OR3C Y Out 0.497 24.366 -

xaddress_RNIE9I8VM1[18] Net - - 0.240 - 1

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 RAM512X18 WD10 In - 24.606 -

======================================================================================================================================================

Total path delay (propagation time + setup) of 24.711 is 10.919(44.2%) logic and 13.792(55.8%) route.

Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

Path information for path number 3:

Requested Period: 10.000

- Setup time: 0.105

+ Clock delay at ending point: 0.000 (ideal)

= Required time: 9.895

- Propagation time: 24.514

- Clock delay at starting point: 0.000 (ideal)

= Slack (non-critical) : -14.619

Number of logic level(s): 25

Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1 / Q

Ending point: l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 / WD10

The start point is clocked by leon3mp|clkgen0.ap3_v.ramclk_inferred_clock [rising] on pin CLK

The end point is clocked by leon3mp|clkgen0.ap3_v.ramclk_inferred_clock [rising] on pin WCLK

Instance / Net Pin Pin Arrival No. of

Name Type Name Dir Delay Time Fan Out(s)

------------------------------------------------------------------------------------------------------------------------------------------------------

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1 DFN1E0 Q Out 0.550 0.550 -

ldbp1_0 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_RNIMV81 CLKINT A In - 0.790 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_RNIMV81 CLKINT Y Out 0.130 0.920 -

ldbp1 Net - - 1.195 - 158

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIQCHD[11] MX2 S In - 2.116 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIQCHD[11] MX2 Y Out 0.296 2.412 -

op1_RNIQCHD[11] Net - - 1.555 - 14

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I12_G0N NOR2A A In - 3.966 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I12_G0N NOR2A Y Out 0.469 4.435 -

N430 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I71_Y_0 OR2 A In - 4.723 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I71_Y_0 OR2 Y Out 0.379 5.102 -

N530 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_un1_Y AO1C C In - 5.342 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_un1_Y AO1C Y Out 0.472 5.815 -

I129_un1_Y Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_Y OR2B B In - 6.055 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_Y OR2B Y Out 0.386 6.440 -

N592 Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_un1_Y NOR3A A In - 7.043 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_un1_Y NOR3A Y Out 0.479 7.521 -

I181_un1_Y Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_Y OR2 B In - 7.762 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_Y OR2 Y Out 0.483 8.244 -

N650_1 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y_0 AO1 C In - 8.533 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y_0 AO1 Y Out 0.472 9.005 -

ADD_33x33_fast_I272_Y_0 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I270_Y_0_a3 OAI1 B In - 9.293 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I270_Y_0_a3 OAI1 Y Out 0.414 9.707 -

N_71_i_1 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I270_Y_0_o3 OR2A A In - 9.947 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I270_Y_0_o3 OR2A Y Out 0.401 10.348 -

N786_1 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I311_Y_0 XNOR2 A In - 10.588 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I311_Y_0 XNOR2 Y Out 0.305 10.893 -

un6_ex_add_res_s0[21] Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.invop2_1_RNI18MQG1 MX2C B In - 11.134 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.invop2_1_RNI18MQG1 MX2C Y Out 0.427 11.560 -

N_8118 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNI78TJG2 MX2C B In - 11.801 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNI78TJG2 MX2C Y Out 0.437 12.238 -

eaddress[20] Net - - 0.884 - 4

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_0_RNIK8SN18 NOR3 C In - 13.122 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_0_RNIK8SN18 NOR3 Y Out 0.561 13.683 -

un1_addout_28_10_6 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIVJ4EBL NOR3B A In - 13.923 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIVJ4EBL NOR3B Y Out 0.497 14.420 -

un1_addout_28_10_9 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNID6SO1P OR2A A In - 14.660 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNID6SO1P OR2A Y Out 0.401 15.061 -

un1_addout_28_10 Net - - 1.327 - 11

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_2_a2_25_m2_e_0 OR2A B In - 16.387 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_2_a2_25_m2_e_0 OR2A Y Out 0.483 16.870 -

un1_addout_28 Net - - 0.955 - 5

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIQ1LUSN1_0 NOR2 A In - 17.826 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIQ1LUSN1_0 NOR2 Y Out 0.379 18.205 -

newptag_2_a2_3_a0_1[22] Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_sn_m2_i_o2_m4_0_a3_0_0 OR2 B In - 18.807 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_sn_m2_i_o2_m4_0_a3_0_0 OR2 Y Out 0.384 19.191 -

newptag_sn_m2_i_o2_m4_0_a3_0_0 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI0SALQP1_0 OR2 A In - 19.431 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI0SALQP1_0 OR2 Y Out 0.271 19.702 -

newptag_sn_m2_i_o2_N_8 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI2N6NQR1 OR2B A In - 19.942 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI2N6NQR1 OR2B Y Out 0.365 20.307 -

flush_0_RNI2N6NQR1 Net - - 1.690 - 18

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNI9NANQR1[4] NOR2A A In - 21.997 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNI9NANQR1[4] NOR2A Y Out 0.469 22.466 -

N_2867 Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNII7IOQR1[4] OR2B B In - 23.068 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNII7IOQR1[4] OR2B Y Out 0.469 23.537 -

N_2783 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNIE9I8VM1[18] OR3C C In - 23.777 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNIE9I8VM1[18] OR3C Y Out 0.497 24.274 -

xaddress_RNIE9I8VM1[18] Net - - 0.240 - 1

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 RAM512X18 WD10 In - 24.514 -

======================================================================================================================================================

Total path delay (propagation time + setup) of 24.619 is 10.980(44.6%) logic and 13.639(55.4%) route.

Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

Path information for path number 4:

Requested Period: 10.000

- Setup time: 0.105

+ Clock delay at ending point: 0.000 (ideal)

= Required time: 9.895

- Propagation time: 24.451

- Clock delay at starting point: 0.000 (ideal)

= Slack (non-critical) : -14.557

Number of logic level(s): 25

Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1 / Q

Ending point: l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 / WD10

The start point is clocked by leon3mp|clkgen0.ap3_v.ramclk_inferred_clock [rising] on pin CLK

The end point is clocked by leon3mp|clkgen0.ap3_v.ramclk_inferred_clock [rising] on pin WCLK

Instance / Net Pin Pin Arrival No. of

Name Type Name Dir Delay Time Fan Out(s)

------------------------------------------------------------------------------------------------------------------------------------------------------

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1 DFN1E0 Q Out 0.550 0.550 -

ldbp1_0 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_RNIMV81 CLKINT A In - 0.790 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp1_RNIMV81 CLKINT Y Out 0.130 0.920 -

ldbp1 Net - - 1.195 - 158

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIQCHD[11] MX2 S In - 2.116 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIQCHD[11] MX2 Y Out 0.296 2.412 -

op1_RNIQCHD[11] Net - - 1.555 - 14

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I12_G0N NOR2A A In - 3.966 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I12_G0N NOR2A Y Out 0.469 4.435 -

N430 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I71_Y_0 OR2 A In - 4.723 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I71_Y_0 OR2 Y Out 0.379 5.102 -

N530 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_un1_Y AO1C C In - 5.342 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_un1_Y AO1C Y Out 0.472 5.815 -

I129_un1_Y Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_Y OR2B B In - 6.055 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I129_Y OR2B Y Out 0.386 6.440 -

N592 Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_un1_Y NOR3A A In - 7.043 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_un1_Y NOR3A Y Out 0.479 7.521 -

I181_un1_Y Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_Y OR2 B In - 7.762 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I181_Y OR2 Y Out 0.483 8.244 -

N650_1 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y_0 AO1 C In - 8.533 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y_0 AO1 Y Out 0.472 9.005 -

ADD_33x33_fast_I272_Y_0 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y OR2 B In - 9.293 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I272_Y OR2 Y Out 0.483 9.776 -

N790 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I309_Y_0 XNOR2 A In - 10.016 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d0.ADD_33x33_fast_I309_Y_0 XNOR2 Y Out 0.305 10.321 -

un6_ex_add_res_s0[19] Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.invop2_1_RNIT39KC1 MX2C B In - 10.561 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.invop2_1_RNIT39KC1 MX2C Y Out 0.427 10.988 -

N_8108 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIK2LC92 MX2C B In - 11.228 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIK2LC92 MX2C Y Out 0.437 11.666 -

eaddress[18] Net - - 0.884 - 4

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_0_RNICB2GG6 NOR3 A In - 12.550 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_0_RNICB2GG6 NOR3 Y Out 0.365 12.914 -

un1_addout_28_10_4 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIS33O5A NOR3C C In - 13.154 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIS33O5A NOR3C Y Out 0.497 13.652 -

un1_addout_28_10_7 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIVJ4EBL NOR3B B In - 13.892 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIVJ4EBL NOR3B Y Out 0.466 14.358 -

un1_addout_28_10_9 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNID6SO1P OR2A A In - 14.598 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNID6SO1P OR2A Y Out 0.401 14.999 -

un1_addout_28_10 Net - - 1.327 - 11

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_2_a2_25_m2_e_0 OR2A B In - 16.325 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_2_a2_25_m2_e_0 OR2A Y Out 0.483 16.808 -

un1_addout_28 Net - - 0.955 - 5

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIQ1LUSN1_0 NOR2 A In - 17.763 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIQ1LUSN1_0 NOR2 Y Out 0.379 18.142 -

newptag_2_a2_3_a0_1[22] Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_sn_m2_i_o2_m4_0_a3_0_0 OR2 B In - 18.745 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_sn_m2_i_o2_m4_0_a3_0_0 OR2 Y Out 0.384 19.129 -

newptag_sn_m2_i_o2_m4_0_a3_0_0 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI0SALQP1_0 OR2 A In - 19.369 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI0SALQP1_0 OR2 Y Out 0.271 19.640 -

newptag_sn_m2_i_o2_N_8 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI2N6NQR1 OR2B A In - 19.880 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI2N6NQR1 OR2B Y Out 0.365 20.245 -

flush_0_RNI2N6NQR1 Net - - 1.690 - 18

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNI9NANQR1[4] NOR2A A In - 21.935 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNI9NANQR1[4] NOR2A Y Out 0.469 22.403 -

N_2867 Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNII7IOQR1[4] OR2B B In - 23.006 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNII7IOQR1[4] OR2B Y Out 0.469 23.474 -

N_2783 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNIE9I8VM1[18] OR3C C In - 23.714 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNIE9I8VM1[18] OR3C Y Out 0.497 24.211 -

xaddress_RNIE9I8VM1[18] Net - - 0.240 - 1

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 RAM512X18 WD10 In - 24.451 -

======================================================================================================================================================

Total path delay (propagation time + setup) of 24.557 is 10.918(44.5%) logic and 13.639(55.5%) route.

Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

Path information for path number 5:

Requested Period: 10.000

- Setup time: 0.105

+ Clock delay at ending point: 0.000 (ideal)

= Required time: 9.895

- Propagation time: 24.422

- Clock delay at starting point: 0.000 (ideal)

= Slack (non-critical) : -14.527

Number of logic level(s): 22

Starting point: l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[7] / Q

Ending point: l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 / WD10

The start point is clocked by leon3mp|clkgen0.ap3_v.ramclk_inferred_clock [rising] on pin CLK

The end point is clocked by leon3mp|clkgen0.ap3_v.ramclk_inferred_clock [rising] on pin WCLK

Instance / Net Pin Pin Arrival No. of

Name Type Name Dir Delay Time Fan Out(s)

------------------------------------------------------------------------------------------------------------------------------------------------------

l3\.cpu\.0\.u0.p0.iu0.r\.x\.data_0[7] DFN1E1 Q Out 0.550 0.550 -

data_0[7] Net - - 1.555 - 14

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIGRB4[7] MX2 B In - 2.105 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.op1_RNIGRB4[7] MX2 Y Out 0.427 2.532 -

op1_RNIGRB4[7] Net - - 1.589 - 15

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I8_P0N OR2 A In - 4.121 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I8_P0N OR2 Y Out 0.379 4.500 -

N419_0 Net - - 0.884 - 4

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I78_Y NOR2B B In - 5.384 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I78_Y NOR2B Y Out 0.469 5.853 -

N537_0 Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I140_Y OR2B B In - 6.455 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I140_Y OR2B Y Out 0.469 6.923 -

N603 Net - - 0.884 - 4

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I249_un1_Y NOR3A B In - 7.807 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I249_un1_Y NOR3A Y Out 0.269 8.076 -

I249_un1_Y_1 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I249_Y OR2 B In - 8.316 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I249_Y OR2 Y Out 0.483 8.799 -

N814_1 Net - - 0.288 - 2

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I265_un1_Y OR3C C In - 9.087 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I265_un1_Y OR3C Y Out 0.479 9.566 -

I265_un1_Y_0 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I265_Y NAND2 A In - 9.806 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I265_Y NAND2 Y Out 0.365 10.171 -

N776_1 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I316_Y_0 XNOR2 A In - 10.411 -

l3\.cpu\.0\.u0.p0.iu0.un6_ex_add_res_d1.ADD_33x33_fast_I316_Y_0 XNOR2 Y Out 0.365 10.775 -

un6_ex_add_res_s1_i[26] Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI684O63 MX2C A In - 11.015 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNI684O63 MX2C Y Out 0.424 11.440 -

eaddress[25] Net - - 0.884 - 4

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_0_RNICB2GG6 NOR3 C In - 12.324 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_0_RNICB2GG6 NOR3 Y Out 0.561 12.884 -

un1_addout_28_10_4 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIS33O5A NOR3C C In - 13.125 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_RNIS33O5A NOR3C Y Out 0.497 13.622 -

un1_addout_28_10_7 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIVJ4EBL NOR3B B In - 13.862 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_2_RNIVJ4EBL NOR3B Y Out 0.466 14.328 -

un1_addout_28_10_9 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNID6SO1P OR2A A In - 14.568 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNID6SO1P OR2A Y Out 0.401 14.969 -

un1_addout_28_10 Net - - 1.327 - 11

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_2_a2_25_m2_e_0 OR2A B In - 16.295 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_2_a2_25_m2_e_0 OR2A Y Out 0.483 16.778 -

un1_addout_28 Net - - 0.955 - 5

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIQ1LUSN1_0 NOR2 A In - 17.733 -

l3\.cpu\.0\.u0.p0.iu0.r\.e\.ldbp2_1_RNIQ1LUSN1_0 NOR2 Y Out 0.379 18.113 -

newptag_2_a2_3_a0_1[22] Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_sn_m2_i_o2_m4_0_a3_0_0 OR2 B In - 18.715 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.newptag_sn_m2_i_o2_m4_0_a3_0_0 OR2 Y Out 0.384 19.099 -

newptag_sn_m2_i_o2_m4_0_a3_0_0 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI0SALQP1_0 OR2 A In - 19.339 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI0SALQP1_0 OR2 Y Out 0.271 19.610 -

newptag_sn_m2_i_o2_N_8 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI2N6NQR1 OR2B A In - 19.850 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.flush_0_RNI2N6NQR1 OR2B Y Out 0.365 20.215 -

flush_0_RNI2N6NQR1 Net - - 1.690 - 18

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNI9NANQR1[4] NOR2A A In - 21.905 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNI9NANQR1[4] NOR2A Y Out 0.469 22.374 -

N_2867 Net - - 0.602 - 3

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNII7IOQR1[4] OR2B B In - 22.976 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.dstate_1_RNII7IOQR1[4] OR2B Y Out 0.469 23.444 -

N_2783 Net - - 0.240 - 1

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNIE9I8VM1[18] OR3C C In - 23.685 -

l3\.cpu\.0\.u0.p0.c0mmu.dcache0.r\.xaddress_RNIE9I8VM1[18] OR3C Y Out 0.497 24.182 -

xaddress_RNIE9I8VM1[18] Net - - 0.240 - 1

l3\.cpu\.0\.u0.cmem0.dme\.dtags0\.dt0\.0\.dtags0.proa3\.x0.r2p\.u0.a8\.x\.0\.u0.u0 RAM512X18 WD10 In - 24.422 -

======================================================================================================================================================

Total path delay (propagation time + setup) of 24.527 is 10.023(40.9%) logic and 14.504(59.1%) route.

Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------

Target Part: M7A3P1000_FBGA144_-2

Report for cell leon3mp.behavioral

Core Cell usage:

cell count area count*area

AND2 175 1.0 175.0

AND2A 5 1.0 5.0

AND3 191 1.0 191.0

AND3A 1 1.0 1.0

AO1 209 1.0 209.0

AO13 13 1.0 13.0

AO18 4 1.0 4.0

AO1A 124 1.0 124.0

AO1B 223 1.0 223.0

AO1C 97 1.0 97.0

AO1D 67 1.0 67.0

AOI1 75 1.0 75.0

AOI1A 8 1.0 8.0

AOI1B 532 1.0 532.0

AX1 5 1.0 5.0

AX1A 4 1.0 4.0

AX1B 10 1.0 10.0

AX1C 19 1.0 19.0

AX1D 10 1.0 10.0

AX1E 5 1.0 5.0

AXO2 1 1.0 1.0

AXO3 2 1.0 2.0

AXO5 2 1.0 2.0

AXO7 2 1.0 2.0

AXOI1 1 1.0 1.0

AXOI2 2 1.0 2.0

AXOI4 5 1.0 5.0

AXOI5 2 1.0 2.0

CLKINT 5 0.0 0.0

GND 66 0.0 0.0

INV 20 1.0 20.0

MAJ3 39 1.0 39.0

MIN3 11 1.0 11.0

MX2 1194 1.0 1194.0

MX2A 202 1.0 202.0

MX2B 184 1.0 184.0

MX2C 985 1.0 985.0

NAND2 61 1.0 61.0

NOR2 472 1.0 472.0

NOR2A 550 1.0 550.0

NOR2B 803 1.0 803.0

NOR3 196 1.0 196.0

NOR3A 218 1.0 218.0

NOR3B 210 1.0 210.0

NOR3C 586 1.0 586.0

OA1 129 1.0 129.0

OA1A 222 1.0 222.0

OA1B 73 1.0 73.0

OA1C 62 1.0 62.0

OAI1 72 1.0 72.0

OR2 428 1.0 428.0

OR2A 1074 1.0 1074.0

OR2B 1434 1.0 1434.0

OR3 177 1.0 177.0

OR3A 186 1.0 186.0

OR3B 240 1.0 240.0

OR3C 452 1.0 452.0

PLL 1 0.0 0.0

PLLINT 1 0.0 0.0

VCC 66 0.0 0.0

XA1 31 1.0 31.0

XA1A 43 1.0 43.0

XA1B 42 1.0 42.0

XA1C 6 1.0 6.0

XAI1 15 1.0 15.0

XAI1A 11 1.0 11.0

XNOR2 196 1.0 196.0

XNOR3 27 1.0 27.0

XO1 1 1.0 1.0

XO1A 3 1.0 3.0

XOR2 343 1.0 343.0

XOR3 40 1.0 40.0

ZOR3 1 1.0 1.0

DFI1E1P0 3 1.0 3.0

DFN1 632 1.0 632.0

DFN1C0 6 1.0 6.0

DFN1E0 1211 1.0 1211.0

DFN1E0P0 2 1.0 2.0

DFN1E1 387 1.0 387.0

DFN1E1P0 10 1.0 10.0

DFN1P0 2 1.0 2.0

RAM4K9 16 0.0 0.0

RAM512X18 8 0.0 0.0

----- ----------

TOTAL 15249 15086.0

IO Cell usage:

cell count

BIBUF 39

INBUF 4

OUTBUF 42

TRIBUFF 4

-----

TOTAL 89

Core Cells : 15086 of 24576 (61%)

IO Cells : 89

RAM/ROM Usage Summary

Block Rams : 24 of 32 (75%)

Mapper successful!

Process took 0h:02m:20s realtime, 0h:02m:20s cputime

# Tue Jul 24 16:59:55 2012

###########################################################]

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages