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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- package: uart
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-- File: uart.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: UART types and components
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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package uart is
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type uart_in_type is record
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rxd : std_ulogic;
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ctsn : std_ulogic;
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extclk : std_ulogic;
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end record;
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type uart_out_type is record
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rtsn : std_ulogic;
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txd : std_ulogic;
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scaler : std_logic_vector(31 downto 0);
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txen : std_ulogic;
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flow : std_ulogic;
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rxen : std_ulogic;
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end record;
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component apbuart
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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console : integer := 0;
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pirq : integer := 0;
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parity : integer := 1;
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flow : integer := 1;
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fifosize : integer range 1 to 32 := 1;
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abits : integer := 8;
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sbits : integer range 12 to 32 := 12);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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uarti : in uart_in_type;
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uarto : out uart_out_type);
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end component;
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component ahbuart
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generic (
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hindex : integer := 0;
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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uarti : in uart_in_type;
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uarto : out uart_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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ahbi : in ahb_mst_in_type;
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ahbo : out ahb_mst_out_type);
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end component;
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end;
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