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-----------------------------------------------------------------------------
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-- Package: multlib
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-- File: multlib.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: A set of multipliers generated from the Arithmetic Module
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-- Generator at Norwegian University of Science and Technology.
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------------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.std_logic_1164.all;
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package multlib is
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component mul_17_17
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generic (mulpipe : integer := 0);
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port (
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clk : in std_ulogic;
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holdn: in std_ulogic;
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x : in std_logic_vector(16 downto 0);
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y : in std_logic_vector(16 downto 0);
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p : out std_logic_vector(33 downto 0)
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);
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end component;
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component mul_33_9
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port (
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x : in std_logic_vector(32 downto 0);
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y : in std_logic_vector(8 downto 0);
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p : out std_logic_vector(41 downto 0)
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);
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end component;
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component mul_33_17
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port (
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x : in std_logic_vector(32 downto 0);
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y : in std_logic_vector(16 downto 0);
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p : out std_logic_vector(49 downto 0)
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);
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end component;
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component mul_33_33
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generic (mulpipe : integer := 0);
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port (
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clk : in std_ulogic;
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holdn: in std_ulogic;
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x : in std_logic_vector(32 downto 0);
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y : in std_logic_vector(32 downto 0);
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p : out std_logic_vector(65 downto 0)
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);
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end component;
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component add32
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port(
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x : in std_logic_vector(31 downto 0);
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y : in std_logic_vector(31 downto 0);
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ci : in std_ulogic;
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s : out std_logic_vector(31 downto 0);
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co : out std_ulogic
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);
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end component;
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end multlib;
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