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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: libproc3
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-- File: libproc3.vhd
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-- Author: Jiri Gaisler Gaisler Research
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-- Description: LEON3 proc3 component declaration
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.leon3.all;
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use gaisler.libcache.all;
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use gaisler.libiu.all;
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--library fpu;
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--use fpu.libfpu.all;
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package libproc3 is
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component proc3
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generic (
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hindex : integer := 0;
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fabtech : integer range 0 to NTECH := 0;
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memtech : integer range 0 to NTECH := 0;
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nwindows : integer range 2 to 32 := 8;
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dsu : integer range 0 to 1 := 0;
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fpu : integer range 0 to 15 := 0;
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v8 : integer range 0 to 63 := 0;
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cp : integer range 0 to 1 := 0;
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mac : integer range 0 to 1 := 0;
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pclow : integer range 0 to 2 := 2;
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notag : integer range 0 to 1 := 0;
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nwp : integer range 0 to 4 := 0;
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icen : integer range 0 to 1 := 0;
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irepl : integer range 0 to 3 := 2;
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isets : integer range 1 to 4 := 1;
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ilinesize : integer range 4 to 8 := 4;
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isetsize : integer range 1 to 256 := 1;
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isetlock : integer range 0 to 1 := 0;
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dcen : integer range 0 to 1 := 0;
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drepl : integer range 0 to 3 := 2;
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dsets : integer range 1 to 4 := 1;
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dlinesize : integer range 4 to 8 := 4;
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dsetsize : integer range 1 to 256 := 1;
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dsetlock : integer range 0 to 1 := 0;
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dsnoop : integer range 0 to 6 := 0;
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ilram : integer range 0 to 1 := 0;
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ilramsize : integer range 1 to 512 := 1;
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ilramstart: integer range 0 to 255 := 16#8e#;
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dlram : integer range 0 to 1 := 0;
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dlramsize : integer range 1 to 512 := 1;
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dlramstart: integer range 0 to 255 := 16#8f#;
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mmuen : integer range 0 to 1 := 0;
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itlbnum : integer range 2 to 64 := 8;
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dtlbnum : integer range 2 to 64 := 8;
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tlb_type : integer range 0 to 3 := 1;
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tlb_rep : integer range 0 to 1 := 0;
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lddel : integer range 1 to 2 := 2;
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disas : integer range 0 to 2 := 0;
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tbuf : integer range 0 to 64 := 0;
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pwd : integer range 0 to 2 := 0; -- power-down
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svt : integer range 0 to 1 := 0; -- single-vector trapping
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rstaddr : integer := 0;
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smp : integer range 0 to 15 := 0; -- support SMP systems
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cached : integer := 0;
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clk2x : integer := 0;
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scantest : integer := 0;
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mmupgsz : integer range 0 to 5 := 0;
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bp : integer range 0 to 5 := 1
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);
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port (
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clk : in std_ulogic;
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rstn : in std_ulogic;
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holdn : out std_ulogic;
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ahbi : in ahb_mst_in_type;
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ahbo : out ahb_mst_out_type;
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ahbsi : in ahb_slv_in_type;
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ahbso : in ahb_slv_out_vector;
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rfi : out iregfile_in_type;
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rfo : in iregfile_out_type;
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crami : out cram_in_type;
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cramo : in cram_out_type;
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tbi : out tracebuf_in_type;
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tbo : in tracebuf_out_type;
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fpi : out fpc_in_type;
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fpo : in fpc_out_type;
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cpi : out fpc_in_type;
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cpo : in fpc_out_type;
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irqi : in l3_irq_in_type;
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irqo : out l3_irq_out_type;
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dbgi : in l3_debug_in_type;
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dbgo : out l3_debug_out_type;
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hclk, sclk : in std_ulogic;
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hclken : in std_ulogic
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);
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end component;
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component grfpwx
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generic (fabtech : integer range 0 to NTECH := 0;
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memtech : integer range 0 to NTECH := 0;
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mul : integer range 0 to 3 := 0;
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pclow : integer range 0 to 2 := 2;
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dsu : integer := 0;
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disas : integer range 0 to 2 := 0;
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netlist : integer := 0;
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index : integer := 0);
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port (
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rst : in std_ulogic; -- Reset
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clk : in std_ulogic;
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holdn : in std_ulogic; -- pipeline hold
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cpi : in fpc_in_type;
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cpo : out fpc_out_type
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);
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end component;
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component mfpwx
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generic (tech : integer := 0;
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pclow : integer range 0 to 2 := 2;
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dsu : integer range 0 to 1 := 0;
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disas : integer range 0 to 2 := 0);
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port (
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rst : in std_ulogic; -- Reset
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clk : in std_ulogic;
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holdn : in std_ulogic; -- pipeline hold
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cpi : in fpc_in_type;
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cpo : out fpc_out_type
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);
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end component;
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component grlfpwx
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generic (tech : integer := 0;
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pclow : integer range 0 to 2 := 2;
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dsu : integer range 0 to 1 := 0;
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disas : integer range 0 to 2 := 0;
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pipe : integer := 0;
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netlist : integer := 0;
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index : integer := 0);
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port (
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rst : in std_ulogic; -- Reset
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clk : in std_ulogic;
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holdn : in std_ulogic; -- pipeline hold
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cpi : in fpc_in_type;
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cpo : out fpc_out_type
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);
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end component;
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end;
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