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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: leon3
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-- File: leon3.vhd
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-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
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-- Description: MMU component declaration
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.mmuconfig.all;
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use gaisler.mmuiface.all;
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package libmmu is
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component mmu
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generic (
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tech : integer range 0 to NTECH := 0;
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itlbnum : integer range 2 to 64 := 8;
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dtlbnum : integer range 2 to 64 := 8;
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tlb_type : integer range 0 to 3 := 1;
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tlb_rep : integer range 0 to 1 := 0;
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mmupgsz : integer range 0 to 5 := 0
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);
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port (
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rst : in std_logic;
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clk : in std_logic;
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mmudci : in mmudc_in_type;
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mmudco : out mmudc_out_type;
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mmuici : in mmuic_in_type;
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mmuico : out mmuic_out_type;
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mcmmo : in memory_mm_out_type;
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mcmmi : out memory_mm_in_type
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);
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end component;
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function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
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read : std_logic;
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lvl : std_logic_vector(1 downto 0);
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ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
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vaddr : std_logic_vector(31 downto 0)
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) return tlbcam_reg;
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procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
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isid : in mmu_idcache;
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su : in std_logic;
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read : in std_logic;
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fault_pro : out std_logic;
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fault_pri : out std_logic );
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procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
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mmctrl : in mmctrl_type1;
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LVL : in std_logic_vector(1 downto 0);
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PTE : in std_logic_vector(31 downto 0);
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data : in std_logic_vector(31 downto 0);
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transdata : out std_logic_vector(31 downto 0));
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function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
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read : std_logic;
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ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
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) return tlbcam_tfp;
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function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
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ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
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) return tlbcam_tfp;
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subtype mmu_gpsz_typ is integer range 0 to 3;
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function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
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mmctrl : in mmctrl_type1
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) return mmu_gpsz_typ;
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end;
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package body libmmu is
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procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
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isid : in mmu_idcache;
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su : in std_logic;
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read : in std_logic;
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fault_pro : out std_logic;
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fault_pri : out std_logic ) is
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variable c_isd : std_logic;
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begin
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fault_pro := '0';
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fault_pri := '0';
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-- use '0' == icache '1' == dcache
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if isid = id_icache then
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c_isd := '0';
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else
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c_isd := '1';
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end if;
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--# fault, todo: should we flush on a fault?
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case ACC is
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when "000" => fault_pro := (not c_isd) or (not read);
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when "001" => fault_pro := (not c_isd);
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when "010" => fault_pro := (not read);
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when "011" => null;
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when "100" => fault_pro := (c_isd);
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when "101" => fault_pro := (not c_isd) or ((not read) and (not su));
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when "110" => fault_pri := (not su);
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fault_pro := (not read);
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when "111" => fault_pri := (not su);
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when others => null;
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end case;
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end;
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procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
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mmctrl : in mmctrl_type1;
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LVL : in std_logic_vector(1 downto 0);
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PTE : in std_logic_vector(31 downto 0);
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data : in std_logic_vector(31 downto 0);
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transdata : out std_logic_vector(31 downto 0) ) is
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variable pagesize : integer range 0 to 3;
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begin
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--# merge data
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transdata := (others => '0');
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pagesize := MMU_getpagesize(mmupgsz, mmctrl);
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case pagesize is
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when 1 =>
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-- 8k
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case LVL is
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when LVL_PAGE => transdata := PTE(P8K_PTE_PPN32PAG_U downto P8K_PTE_PPN32PAG_D) & data(P8K_VA_OFFPAG_U downto P8K_VA_OFFPAG_D);
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when LVL_SEGMENT => transdata := PTE(P8K_PTE_PPN32SEG_U downto P8K_PTE_PPN32SEG_D) & data(P8K_VA_OFFSEG_U downto P8K_VA_OFFSEG_D);
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when LVL_REGION => transdata := PTE(P8K_PTE_PPN32REG_U downto P8K_PTE_PPN32REG_D) & data(P8K_VA_OFFREG_U downto P8K_VA_OFFREG_D);
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when LVL_CTX => transdata := data(P8K_VA_OFFCTX_U downto P8K_VA_OFFCTX_D);
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when others => transdata := (others => 'X');
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end case;
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when 2 =>
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-- 16k
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case LVL is
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when LVL_PAGE => transdata := PTE(P16K_PTE_PPN32PAG_U downto P16K_PTE_PPN32PAG_D) & data(P16K_VA_OFFPAG_U downto P16K_VA_OFFPAG_D);
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when LVL_SEGMENT => transdata := PTE(P16K_PTE_PPN32SEG_U downto P16K_PTE_PPN32SEG_D) & data(P16K_VA_OFFSEG_U downto P16K_VA_OFFSEG_D);
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when LVL_REGION => transdata := PTE(P16K_PTE_PPN32REG_U downto P16K_PTE_PPN32REG_D) & data(P16K_VA_OFFREG_U downto P16K_VA_OFFREG_D);
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when LVL_CTX => transdata := data(P16K_VA_OFFCTX_U downto P16K_VA_OFFCTX_D);
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when others => transdata := (others => 'X');
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end case;
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when 3 =>
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-- 32k
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case LVL is
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when LVL_PAGE => transdata := PTE(P32K_PTE_PPN32PAG_U downto P32K_PTE_PPN32PAG_D) & data(P32K_VA_OFFPAG_U downto P32K_VA_OFFPAG_D);
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when LVL_SEGMENT => transdata := PTE(P32K_PTE_PPN32SEG_U downto P32K_PTE_PPN32SEG_D) & data(P32K_VA_OFFSEG_U downto P32K_VA_OFFSEG_D);
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when LVL_REGION => transdata := PTE(P32K_PTE_PPN32REG_U downto P32K_PTE_PPN32REG_D) & data(P32K_VA_OFFREG_U downto P32K_VA_OFFREG_D);
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when LVL_CTX => transdata := data(P32K_VA_OFFCTX_U downto P32K_VA_OFFCTX_D);
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when others => transdata := (others => 'X');
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end case;
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when others =>
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-- 4k
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case LVL is
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when LVL_PAGE => transdata := PTE(PTE_PPN32PAG_U downto PTE_PPN32PAG_D) & data(VA_OFFPAG_U downto VA_OFFPAG_D);
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when LVL_SEGMENT => transdata := PTE(PTE_PPN32SEG_U downto PTE_PPN32SEG_D) & data(VA_OFFSEG_U downto VA_OFFSEG_D);
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when LVL_REGION => transdata := PTE(PTE_PPN32REG_U downto PTE_PPN32REG_D) & data(VA_OFFREG_U downto VA_OFFREG_D);
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when LVL_CTX => transdata := data(VA_OFFCTX_U downto VA_OFFCTX_D);
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when others => transdata := (others => 'X');
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end case;
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end case;
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end;
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function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
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read : std_logic;
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lvl : std_logic_vector(1 downto 0);
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ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
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vaddr : std_logic_vector(31 downto 0)
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) return tlbcam_reg is
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variable tlbcam_tagwrite : tlbcam_reg;
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begin
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tlbcam_tagwrite.ET := two_data(PT_ET_U downto PT_ET_D);
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tlbcam_tagwrite.ACC := two_data(PTE_ACC_U downto PTE_ACC_D);
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tlbcam_tagwrite.M := two_data(PTE_M) or (not read); -- tw : p-update modified
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tlbcam_tagwrite.R := '1';
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case tlbcam_tagwrite.ACC is -- tw : p-su ACC >= 6
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when "110" | "111" => tlbcam_tagwrite.SU := '1';
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when others => tlbcam_tagwrite.SU := '0';
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end case;
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tlbcam_tagwrite.VALID := '1';
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tlbcam_tagwrite.LVL := lvl;
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tlbcam_tagwrite.I1 := vaddr(VA_I1_U downto VA_I1_D);
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tlbcam_tagwrite.I2 := vaddr(VA_I2_U downto VA_I2_D);
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tlbcam_tagwrite.I3 := vaddr(VA_I3_U downto VA_I3_D);
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tlbcam_tagwrite.CTX := ctx;
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tlbcam_tagwrite.PPN := two_data(PTE_PPN_U downto PTE_PPN_D);
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tlbcam_tagwrite.C := two_data(PTE_C);
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return tlbcam_tagwrite;
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end;
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function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
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mmctrl : in mmctrl_type1
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) return mmu_gpsz_typ is
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variable pagesize : mmu_gpsz_typ;
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begin
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if mmupgsz = 4 then pagesize := conv_integer(mmctrl.pagesize); -- variable
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else pagesize := mmupgsz; end if;
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return pagesize;
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end;
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function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
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read : std_logic;
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ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
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) return tlbcam_tfp is
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variable mtag : tlbcam_tfp;
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begin
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mtag.TYP := (others => '0');
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mtag.I1 := vaddr(VA_I1_U downto VA_I1_D);
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mtag.I2 := vaddr(VA_I2_U downto VA_I2_D);
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mtag.I3 := vaddr(VA_I3_U downto VA_I3_D);
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mtag.CTX := ctx;
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mtag.M := not (read);
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return mtag;
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end;
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function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
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ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
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) return tlbcam_tfp is
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variable ftag : tlbcam_tfp;
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begin
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ftag.TYP := data(FPTY_U downto FPTY_D);
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ftag.I1 := data(FPA_I1_U downto FPA_I1_D);
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ftag.I2 := data(FPA_I2_U downto FPA_I2_D);
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ftag.I3 := data(FPA_I3_U downto FPA_I3_D);
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ftag.CTX := ctx;
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ftag.M := '0';
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return ftag;
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end;
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end;
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