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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.stdlib.all;
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package grethpkg is
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--gigabit sync types
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type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
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type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
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constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
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constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
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constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
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constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
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constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
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constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
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constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
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constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
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constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
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--receiver constants
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constant maxsizerx : std_logic_vector(15 downto 0) :=
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conv_std_logic_vector(1500, 16);
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constant minpload : std_logic_vector(10 downto 0) :=
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conv_std_logic_vector(60, 11);
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type ahb_fifo_in_type is record
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renable : std_ulogic;
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raddress : std_logic_vector(4 downto 0);
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write : std_ulogic;
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data : std_logic_vector(31 downto 0);
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waddress : std_logic_vector(4 downto 0);
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end record;
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type ahb_fifo_out_type is record
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data : std_logic_vector(31 downto 0);
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end record;
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type nchar_fifo_in_type is record
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renable : std_ulogic;
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raddress : std_logic_vector(5 downto 0);
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write : std_ulogic;
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data : std_logic_vector(8 downto 0);
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waddress : std_logic_vector(5 downto 0);
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end record;
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type nchar_fifo_out_type is record
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data : std_logic_vector(8 downto 0);
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end record;
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type rmapbuf_in_type is record
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renable : std_ulogic;
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raddress : std_logic_vector(7 downto 0);
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write : std_ulogic;
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data : std_logic_vector(7 downto 0);
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waddress : std_logic_vector(7 downto 0);
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end record;
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type rmapbuf_out_type is record
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data : std_logic_vector(7 downto 0);
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end record;
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type ahbc_mst_in_type is record
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hgrant : std_ulogic; -- bus grant
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hready : std_ulogic; -- transfer done
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hresp : std_logic_vector(1 downto 0); -- response type
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hrdata : std_logic_vector(31 downto 0); -- read data bus
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end record;
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type ahbc_mst_out_type is record
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hbusreq : std_ulogic; -- bus request
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hlock : std_ulogic; -- lock request
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htrans : std_logic_vector(1 downto 0); -- transfer type
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haddr : std_logic_vector(31 downto 0); -- address bus (byte)
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hwrite : std_ulogic; -- read/write
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hsize : std_logic_vector(2 downto 0); -- transfer size
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hburst : std_logic_vector(2 downto 0); -- burst type
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hprot : std_logic_vector(3 downto 0); -- protection control
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hwdata : std_logic_vector(31 downto 0); -- write data bus
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end record;
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type apbc_slv_in_type is record
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psel : std_ulogic; -- slave select
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penable : std_ulogic; -- strobe
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paddr : std_logic_vector(31 downto 0); -- address bus (byte)
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pwrite : std_ulogic; -- write
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pwdata : std_logic_vector(31 downto 0); -- write data bus
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end record;
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type apbc_slv_out_type is record
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prdata : std_logic_vector(31 downto 0); -- read data bus
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end record;
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type eth_tx_ahb_in_type is record
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req : std_ulogic;
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write : std_ulogic;
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addr : std_logic_vector(31 downto 0);
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data : std_logic_vector(31 downto 0);
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end record;
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type eth_tx_ahb_out_type is record
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grant : std_ulogic;
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data : std_logic_vector(31 downto 0);
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ready : std_ulogic;
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error : std_ulogic;
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retry : std_ulogic;
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end record;
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type eth_rx_ahb_in_type is record
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req : std_ulogic;
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write : std_ulogic;
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addr : std_logic_vector(31 downto 0);
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data : std_logic_vector(31 downto 0);
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end record;
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type eth_rx_ahb_out_type is record
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grant : std_ulogic;
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ready : std_ulogic;
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error : std_ulogic;
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retry : std_ulogic;
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data : std_logic_vector(31 downto 0);
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end record;
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type eth_rx_gbit_ahb_in_type is record
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req : std_ulogic;
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write : std_ulogic;
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addr : std_logic_vector(31 downto 0);
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data : std_logic_vector(31 downto 0);
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size : std_logic_vector(1 downto 0);
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end record;
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type gbit_host_tx_type is record
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full_duplex : std_ulogic;
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start : std_ulogic;
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read_ack : std_ulogic;
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data : std_logic_vector(31 downto 0);
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valid : std_ulogic;
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len : std_logic_vector(10 downto 0);
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rx_col : std_ulogic;
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rx_crs : std_ulogic;
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end record;
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type gbit_tx_host_type is record
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txd : std_logic_vector(3 downto 0);
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tx_en : std_ulogic;
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done : std_ulogic;
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read : std_ulogic;
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restart : std_ulogic;
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status : std_logic_vector(1 downto 0);
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end record;
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type gbit_rx_host_type is record
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sync_start : std_ulogic;
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done : std_ulogic;
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write : std_logic_vector(3 downto 0);
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dataout : data_sync_type;
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byte_count : std_logic_vector(10 downto 0);
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status : std_logic_vector(3 downto 0);
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gotframe : std_ulogic;
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mcasthash : std_logic_vector(5 downto 0);
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end record;
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type gbit_host_rx_type is record
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full_duplex : std_ulogic;
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gbit : std_ulogic;
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doneack : std_ulogic;
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writeack : std_logic_vector(3 downto 0);
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speed : std_ulogic;
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writeok : std_logic_vector(3 downto 0);
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rxenable : std_ulogic;
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rxd : std_logic_vector(7 downto 0);
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rx_dv : std_ulogic;
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rx_er : std_ulogic;
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rx_col : std_ulogic;
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rx_crs : std_ulogic;
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end record;
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type gbit_gtx_host_type is record
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txd : std_logic_vector(7 downto 0);
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tx_en : std_ulogic;
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tx_er : std_ulogic;
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done : std_ulogic;
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restart : std_ulogic;
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read : std_logic_vector(3 downto 0);
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status : std_logic_vector(2 downto 0);
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end record;
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type gbit_host_gtx_type is record
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rx_col : std_ulogic;
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rx_crs : std_ulogic;
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full_duplex : std_ulogic;
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burstmode : std_ulogic;
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txen : std_ulogic;
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start_sync : std_ulogic;
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readack : std_logic_vector(3 downto 0);
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valid : std_logic_vector(3 downto 0);
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data : data_sync_type;
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len : std_logic_vector(10 downto 0);
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end record;
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type host_tx_type is record
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rx_col : std_ulogic;
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rx_crs : std_ulogic;
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full_duplex : std_ulogic;
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start : std_ulogic;
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readack : std_ulogic;
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speed : std_ulogic;
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data : std_logic_vector(31 downto 0);
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valid : std_ulogic;
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len : std_logic_vector(10 downto 0);
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end record;
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type tx_host_type is record
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txd : std_logic_vector(3 downto 0);
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tx_en : std_ulogic;
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tx_er : std_ulogic;
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done : std_ulogic;
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read : std_ulogic;
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restart : std_ulogic;
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status : std_logic_vector(1 downto 0);
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end record;
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type rx_host_type is record
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dataout : std_logic_vector(31 downto 0);
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start : std_ulogic;
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done : std_ulogic;
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write : std_ulogic;
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status : std_logic_vector(3 downto 0);
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gotframe : std_ulogic;
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byte_count : std_logic_vector(10 downto 0);
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lentype : std_logic_vector(15 downto 0);
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mcasthash : std_logic_vector(5 downto 0);
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end record;
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type host_rx_type is record
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writeack : std_ulogic;
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doneack : std_ulogic;
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speed : std_ulogic;
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writeok : std_ulogic;
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rxd : std_logic_vector(3 downto 0);
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rx_dv : std_ulogic;
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rx_crs : std_ulogic;
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rx_er : std_ulogic;
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enable : std_ulogic;
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end record;
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component greth_rx is
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generic(
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nsync : integer range 1 to 2 := 2;
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rmii : integer range 0 to 1 := 0;
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multicast : integer range 0 to 1 := 0);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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rxi : in host_rx_type;
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rxo : out rx_host_type
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);
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end component;
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component greth_tx is
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generic(
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ifg_gap : integer := 24;
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attempt_limit : integer := 16;
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backoff_limit : integer := 10;
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nsync : integer range 1 to 2 := 2;
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rmii : integer range 0 to 1 := 0);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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txi : in host_tx_type;
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txo : out tx_host_type
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);
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end component;
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component eth_rstgen is
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generic(acthigh : integer := 0);
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port (
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rstin : in std_ulogic;
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clk : in std_ulogic;
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clklock : in std_ulogic;
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rstout : out std_ulogic;
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rstoutraw : out std_ulogic
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);
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end component;
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component greth_gbit_tx is
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generic(
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ifg_gap : integer := 24;
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attempt_limit : integer := 16;
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backoff_limit : integer := 10;
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nsync : integer range 1 to 2 := 2);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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txi : in gbit_host_tx_type;
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txo : out gbit_tx_host_type);
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end component;
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component greth_gbit_gtx is
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generic(
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ifg_gap : integer := 24;
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attempt_limit : integer := 16;
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backoff_limit : integer := 10;
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nsync : integer range 1 to 2 := 2);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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gtxi : in gbit_host_gtx_type;
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gtxo : out gbit_gtx_host_type
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);
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end component;
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component greth_gbit_rx is
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generic(
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multicast : integer range 0 to 1 := 0;
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nsync : integer range 1 to 2 := 2);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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rxi : in gbit_host_rx_type;
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rxo : out gbit_rx_host_type);
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end component;
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component eth_ahb_mst is
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbmi : in ahbc_mst_in_type;
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ahbmo : out ahbc_mst_out_type;
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tmsti : in eth_tx_ahb_in_type;
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tmsto : out eth_tx_ahb_out_type;
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rmsti : in eth_rx_ahb_in_type;
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rmsto : out eth_rx_ahb_out_type
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);
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end component;
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component eth_ahb_mst_gbit is
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbmi : in ahbc_mst_in_type;
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ahbmo : out ahbc_mst_out_type;
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tmsti : in eth_tx_ahb_in_type;
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tmsto : out eth_tx_ahb_out_type;
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rmsti : in eth_rx_gbit_ahb_in_type;
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rmsto : out eth_rx_ahb_out_type);
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end component;
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component eth_edcl_ahb_mst is
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbmi : in ahbc_mst_in_type;
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ahbmo : out ahbc_mst_out_type;
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tmsti : in eth_tx_ahb_in_type;
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tmsto : out eth_tx_ahb_out_type
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);
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end component;
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function mirror(din : in std_logic_vector) return std_logic_vector;
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function crc32_4(d : in std_logic_vector(3 downto 0);
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crc : in std_logic_vector(31 downto 0))
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return std_logic_vector;
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function crc16_2(d1 : in std_logic_vector(15 downto 0);
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d2 : in std_logic_vector(25 downto 0))
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return std_logic_vector;
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function crc16(d1 : in std_logic_vector(15 downto 0);
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d2 : in std_logic_vector(15 downto 0))
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return std_logic_vector;
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function validlen(len : in std_logic_vector(10 downto 0);
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bcnt : in std_logic_vector(10 downto 0);
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usesz : in std_ulogic)
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return std_ulogic;
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function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
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function setburstlength(fifosize : in integer) return integer;
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function calccrc(d : in std_logic_vector(3 downto 0);
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crc : in std_logic_vector(31 downto 0))
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return std_logic_vector;
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--16-bit one's complement adder
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function crcadder(d1 : in std_logic_vector(15 downto 0);
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d2 : in std_logic_vector(17 downto 0))
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return std_logic_vector;
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end package;
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package body grethpkg is
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function mirror(din : in std_logic_vector)
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return std_logic_vector is
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variable do : std_logic_vector(din'range);
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begin
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for i in 0 to din'length-1 loop
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do(din'high-i) := din(i+din'low);
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end loop;
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return do;
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end function;
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function crc32_4(d : in std_logic_vector(3 downto 0);
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crc : in std_logic_vector(31 downto 0))
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return std_logic_vector is
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variable ncrc : std_logic_vector(31 downto 0);
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variable tc : std_logic_vector(3 downto 0);
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begin
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tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
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tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
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ncrc(31) := crc(27);
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ncrc(30) := crc(26);
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ncrc(29) := tc(0) xor crc(25);
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ncrc(28) := tc(1) xor crc(24);
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ncrc(27) := tc(2) xor crc(23);
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ncrc(26) := tc(0) xor tc(3) xor crc(22);
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ncrc(25) := tc(0) xor tc(1) xor crc(21);
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ncrc(24) := tc(1) xor tc(2) xor crc(20);
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ncrc(23) := tc(2) xor tc(3) xor crc(19);
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ncrc(22) := tc(3) xor crc(18);
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ncrc(21) := crc(17);
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ncrc(20) := crc(16);
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ncrc(19) := tc(0) xor crc(15);
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ncrc(18) := tc(1) xor crc(14);
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ncrc(17) := tc(2) xor crc(13);
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ncrc(16) := tc(3) xor crc(12);
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ncrc(15) := tc(0) xor crc(11);
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ncrc(14) := tc(0) xor tc(1) xor crc(10);
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ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
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ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
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ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
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ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
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ncrc(9) := tc(1) xor tc(2) xor crc(5);
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ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
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ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
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ncrc(6) := tc(1) xor tc(2) xor crc(2);
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ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
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ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
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ncrc(3) := tc(0) xor tc(1) xor tc(2);
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ncrc(2) := tc(1) xor tc(2) xor tc(3);
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ncrc(1) := tc(2) xor tc(3);
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ncrc(0) := tc(3);
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return ncrc;
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end function;
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--16-bit one's complement adder
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function crc16(d1 : in std_logic_vector(15 downto 0);
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d2 : in std_logic_vector(15 downto 0))
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return std_logic_vector is
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variable vd1 : std_logic_vector(16 downto 0);
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variable vd2 : std_logic_vector(16 downto 0);
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variable sum : std_logic_vector(16 downto 0);
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begin
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vd1 := '0' & d1; vd2 := '0' & d2;
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sum := vd1 + vd2;
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sum(15 downto 0) := sum(15 downto 0) + sum(16);
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return sum(15 downto 0);
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end function;
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--16-bit one's complement adder for ip/tcp checksum detection
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function crc16_2(d1 : in std_logic_vector(15 downto 0);
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d2 : in std_logic_vector(25 downto 0))
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return std_logic_vector is
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variable vd1 : std_logic_vector(25 downto 0);
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variable vd2 : std_logic_vector(25 downto 0);
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variable sum : std_logic_vector(25 downto 0);
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begin
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vd1 := "0000000000" & d1; vd2 := d2;
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sum := vd1 + vd2;
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return sum;
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end function;
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function validlen(len : in std_logic_vector(10 downto 0);
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bcnt : in std_logic_vector(10 downto 0);
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usesz : in std_ulogic)
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return std_ulogic is
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variable valid : std_ulogic;
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begin
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valid := '1';
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if usesz = '1' then
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if len > minpload then
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if bcnt /= len then
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valid := '0';
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end if;
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else
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if bcnt /= minpload then
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valid := '0';
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end if;
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end if;
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end if;
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return valid;
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end function;
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function setburstlength(fifosize : in integer) return integer is
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begin
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if fifosize <= 64 then
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return fifosize/2;
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else
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return 32;
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end if;
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end function;
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function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
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begin
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if (edcl /= 0) and (ebufsize > fifosize) then
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return ebufsize;
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else
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return fifosize;
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end if;
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end function;
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function calccrc(d : in std_logic_vector(3 downto 0);
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crc : in std_logic_vector(31 downto 0))
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return std_logic_vector is
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variable ncrc : std_logic_vector(31 downto 0);
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variable tc : std_logic_vector(3 downto 0);
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begin
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tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
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tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
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ncrc(31) := crc(27);
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ncrc(30) := crc(26);
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ncrc(29) := tc(0) xor crc(25);
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ncrc(28) := tc(1) xor crc(24);
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ncrc(27) := tc(2) xor crc(23);
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ncrc(26) := tc(0) xor tc(3) xor crc(22);
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ncrc(25) := tc(0) xor tc(1) xor crc(21);
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ncrc(24) := tc(1) xor tc(2) xor crc(20);
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ncrc(23) := tc(2) xor tc(3) xor crc(19);
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ncrc(22) := tc(3) xor crc(18);
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ncrc(21) := crc(17);
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ncrc(20) := crc(16);
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ncrc(19) := tc(0) xor crc(15);
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ncrc(18) := tc(1) xor crc(14);
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ncrc(17) := tc(2) xor crc(13);
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ncrc(16) := tc(3) xor crc(12);
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ncrc(15) := tc(0) xor crc(11);
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ncrc(14) := tc(0) xor tc(1) xor crc(10);
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ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
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ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
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ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
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ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
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ncrc(9) := tc(1) xor tc(2) xor crc(5);
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ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
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ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
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ncrc(6) := tc(1) xor tc(2) xor crc(2);
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ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
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ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
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ncrc(3) := tc(0) xor tc(1) xor tc(2);
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ncrc(2) := tc(1) xor tc(2) xor tc(3);
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ncrc(1) := tc(2) xor tc(3);
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ncrc(0) := tc(3);
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return ncrc;
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end function;
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--16-bit one's complement adder
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function crcadder(d1 : in std_logic_vector(15 downto 0);
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d2 : in std_logic_vector(17 downto 0))
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return std_logic_vector is
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variable vd1 : std_logic_vector(17 downto 0);
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variable vd2 : std_logic_vector(17 downto 0);
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variable sum : std_logic_vector(17 downto 0);
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begin
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vd1 := "00" & d1; vd2 := d2;
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sum := vd1 + vd2;
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return sum;
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end function;
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end package body;
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