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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: allmul
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-- File: allmul.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Multiplier components
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package allmul is
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component mul_dw is
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generic (
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a_width : positive := 2; -- multiplier word width
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b_width : positive := 2; -- multiplicand word width
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num_stages : positive := 2; -- number of pipeline stages
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stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
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);
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port(a : in std_logic_vector(a_width-1 downto 0);
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b : in std_logic_vector(b_width-1 downto 0);
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clk : in std_logic;
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en : in std_logic;
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sign : in std_logic;
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product : out std_logic_vector(a_width+b_width-1 downto 0));
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end component;
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component gen_mult_pipe
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generic (
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a_width : positive; -- multiplier word width
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b_width : positive; -- multiplicand word width
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num_stages : positive := 2; -- number of pipeline stages
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stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
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port (
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clk : in std_logic; -- register clock
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en : in std_logic; -- register enable
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tc : in std_logic; -- '0' : unsigned, '1' : signed
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a : in std_logic_vector(a_width-1 downto 0); -- multiplier
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b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
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product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
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end component;
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component axcel_mul_33x33_signed
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generic (
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pipe: Integer := 0);
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port (
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a: in Std_Logic_Vector(32 downto 0);
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b: in Std_Logic_Vector(32 downto 0);
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en: in Std_Logic;
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clk: in Std_Logic;
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p: out Std_Logic_Vector(65 downto 0));
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end component;
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end;
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