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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: allddr
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-- File: allddr.vhd
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-- Author: David Lindh, Jiri Gaisler - Gaisler Research
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-- Description: DDR input/output registers
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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package allddr is
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component unisim_iddr_reg is
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generic ( tech : integer := virtex4);
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port(
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Q1 : out std_ulogic;
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Q2 : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic
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);
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end component;
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component gen_iddr_reg
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port (
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Q1 : out std_ulogic;
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Q2 : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component ec_oddr_reg
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port (
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Q : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D1 : in std_ulogic;
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D2 : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component unisim_oddr_reg
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generic ( tech : integer := virtex4);
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port (
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Q : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D1 : in std_ulogic;
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D2 : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component gen_oddr_reg
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port (
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Q : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D1 : in std_ulogic;
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D2 : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component axcel_oddr_reg is
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port(
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Q : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D1 : in std_ulogic;
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D2 : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component axcel_iddr_reg is
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port(
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Q1 : out std_ulogic;
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Q2 : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component nextreme_oddr_reg
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port(
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CK : in std_ulogic;
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DH : in std_ulogic;
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DL : in std_ulogic;
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DOE : in std_ulogic;
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Q : out std_ulogic;
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OE : out std_ulogic;
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RSTB : in std_ulogic);
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end component;
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component nextreme_iddr_reg
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port(
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CK : in std_ulogic;
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D : in std_ulogic;
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QH : out std_ulogic;
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QL : out std_ulogic;
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RSTB : in std_ulogic);
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end component;
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component apa3_oddr_reg is
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port(
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Q : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D1 : in std_ulogic;
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D2 : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component apa3_iddr_reg is
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port(
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Q1 : out std_ulogic;
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Q2 : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component apa3e_oddr_reg is
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port(
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Q : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D1 : in std_ulogic;
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D2 : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component apa3e_iddr_reg is
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port(
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Q1 : out std_ulogic;
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Q2 : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component apa3l_oddr_reg is
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port(
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Q : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D1 : in std_ulogic;
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D2 : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component apa3l_iddr_reg is
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port(
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Q1 : out std_ulogic;
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Q2 : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component spartan3e_ddr_phy
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generic (MHz : integer := 100; rstdelay : integer := 200;
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dbits : integer := 16; clk_mul : integer := 2 ;
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clk_div : integer := 2; rskew : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_logic; -- input clock
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clkout : out std_ulogic; -- DDR state clock
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clkread : out std_ulogic; -- DDR read clock
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lock : out std_ulogic; -- DCM locked
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ddr_clk : out std_logic_vector(2 downto 0);
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ddr_clkb : out std_logic_vector(2 downto 0);
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ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke : out std_logic_vector(1 downto 0);
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ddr_csb : out std_logic_vector(1 downto 0);
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
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addr : in std_logic_vector (13 downto 0); -- data mask
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ba : in std_logic_vector ( 1 downto 0); -- data mask
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dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
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oen : in std_ulogic;
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dqs : in std_ulogic;
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dqsoen : in std_ulogic;
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rasn : in std_ulogic;
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casn : in std_ulogic;
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wen : in std_ulogic;
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csn : in std_logic_vector(1 downto 0);
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cke : in std_logic_vector(1 downto 0)
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);
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end component;
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component virtex4_ddr_phy
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generic (MHz : integer := 100; rstdelay : integer := 200;
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dbits : integer := 16; clk_mul : integer := 2 ;
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clk_div : integer := 2; rskew : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_logic; -- input clock
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clkout : out std_ulogic; -- system clock
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lock : out std_ulogic; -- DCM locked
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ddr_clk : out std_logic_vector(2 downto 0);
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ddr_clkb : out std_logic_vector(2 downto 0);
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ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke : out std_logic_vector(1 downto 0);
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ddr_csb : out std_logic_vector(1 downto 0);
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
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addr : in std_logic_vector (13 downto 0); -- data mask
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ba : in std_logic_vector ( 1 downto 0); -- data mask
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dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
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oen : in std_ulogic;
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dqs : in std_ulogic;
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dqsoen : in std_ulogic;
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rasn : in std_ulogic;
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casn : in std_ulogic;
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wen : in std_ulogic;
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csn : in std_logic_vector(1 downto 0);
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cke : in std_logic_vector(1 downto 0);
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ck : in std_logic_vector(2 downto 0)
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);
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end component;
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component virtex2_ddr_phy
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generic (MHz : integer := 100; rstdelay : integer := 200;
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dbits : integer := 16; clk_mul : integer := 2 ;
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clk_div : integer := 2; rskew : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_logic; -- input clock
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clkout : out std_ulogic; -- system clock
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lock : out std_ulogic; -- DCM locked
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ddr_clk : out std_logic_vector(2 downto 0);
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ddr_clkb : out std_logic_vector(2 downto 0);
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ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke : out std_logic_vector(1 downto 0);
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ddr_csb : out std_logic_vector(1 downto 0);
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
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addr : in std_logic_vector (13 downto 0); -- data mask
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ba : in std_logic_vector ( 1 downto 0); -- data mask
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dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
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oen : in std_ulogic;
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dqs : in std_ulogic;
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dqsoen : in std_ulogic;
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rasn : in std_ulogic;
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casn : in std_ulogic;
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wen : in std_ulogic;
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csn : in std_logic_vector(1 downto 0);
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cke : in std_logic_vector(1 downto 0)
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);
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end component;
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component stratixii_ddr_phy
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generic (MHz : integer := 100; rstdelay : integer := 200;
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dbits : integer := 16; clk_mul : integer := 2 ;
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clk_div : integer := 2);
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port (
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rst : in std_ulogic;
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clk : in std_logic; -- input clock
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clkout : out std_ulogic; -- system clock
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lock : out std_ulogic; -- DCM locked
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ddr_clk : out std_logic_vector(2 downto 0);
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ddr_clkb : out std_logic_vector(2 downto 0);
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ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke : out std_logic_vector(1 downto 0);
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ddr_csb : out std_logic_vector(1 downto 0);
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
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addr : in std_logic_vector (13 downto 0); -- data mask
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ba : in std_logic_vector ( 1 downto 0); -- data mask
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dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
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oen : in std_ulogic;
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dqs : in std_ulogic;
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dqsoen : in std_ulogic;
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rasn : in std_ulogic;
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casn : in std_ulogic;
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wen : in std_ulogic;
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csn : in std_logic_vector(1 downto 0);
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cke : in std_logic_vector(1 downto 0)
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);
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end component;
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component cycloneiii_ddr_phy
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generic (MHz : integer := 100; rstdelay : integer := 200;
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dbits : integer := 16; clk_mul : integer := 2 ;
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clk_div : integer := 2; rskew : integer := 0);
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|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
|
|
|
addr : in std_logic_vector (13 downto 0); -- data mask
|
|
|
ba : in std_logic_vector ( 1 downto 0); -- data mask
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(1 downto 0);
|
|
|
cke : in std_logic_vector(1 downto 0)
|
|
|
);
|
|
|
|
|
|
end component;
|
|
|
|
|
|
component generic_ddr_phy
|
|
|
generic (MHz : integer := 100; rstdelay : integer := 200;
|
|
|
dbits : integer := 16; clk_mul : integer := 2 ;
|
|
|
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0);
|
|
|
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
|
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
|
|
|
addr : in std_logic_vector (13 downto 0); -- data mask
|
|
|
ba : in std_logic_vector ( 1 downto 0); -- data mask
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(1 downto 0);
|
|
|
cke : in std_logic_vector(1 downto 0);
|
|
|
ck : in std_logic_vector(2 downto 0);
|
|
|
moben : in std_logic
|
|
|
);
|
|
|
|
|
|
end component;
|
|
|
|
|
|
component tsmc90_tci_ddr_phy
|
|
|
generic (MHz : integer := 100; rstdelay : integer := 200;
|
|
|
dbits : integer := 16);
|
|
|
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clk90_sigi_0 : in std_logic;
|
|
|
rclk_sigi_1 : in std_logic;
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
--ddr_clk_fb_out : out std_logic;
|
|
|
--ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqsin : in std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
|
|
|
ddr_dqsout : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
|
|
|
ddr_dqsoen : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
|
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
|
|
ddr_dqin : in std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
ddr_dqout : out std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
ddr_dqoen : out std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
|
|
|
addr : in std_logic_vector (13 downto 0); -- ddr address
|
|
|
ba : in std_logic_vector ( 1 downto 0); -- ddr bank address
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(1 downto 0);
|
|
|
cke : in std_logic_vector(1 downto 0);
|
|
|
ck : in std_logic_vector(2 downto 0);
|
|
|
moben : in std_logic;
|
|
|
conf : in std_logic_vector(63 downto 0);
|
|
|
tstclkout : out std_logic_vector(3 downto 0)
|
|
|
);
|
|
|
|
|
|
end component;
|
|
|
|
|
|
component virtex5_ddr2_phy
|
|
|
generic (
|
|
|
MHz : integer := 100; rstdelay : integer := 200;
|
|
|
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
|
|
|
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
|
|
|
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
|
|
|
ddelayb6 : integer := 0; ddelayb7 : integer := 0; cbdelayb0: integer := 0;
|
|
|
cbdelayb1 : integer := 0; cbdelayb2 : integer := 0; cbdelayb3: integer := 0;
|
|
|
numidelctrl : integer := 4; norefclk : integer := 0;
|
|
|
tech : integer := virtex5; eightbanks : integer range 0 to 1 := 0;
|
|
|
dqsse : integer range 0 to 1 := 0;
|
|
|
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
|
|
|
cben : integer := 0; chkbits : integer := 8; ctrl2en : integer := 0);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkref200 : in std_logic; -- input 200MHz clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(nclk-1 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
|
|
|
ddr_cke : out std_logic_vector(ncs-1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(ncs-1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
|
|
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
|
|
|
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
ddr_odt : out std_logic_vector(ncs-1 downto 0);
|
|
|
|
|
|
addr : in std_logic_vector (abits-1 downto 0); -- ddr addr
|
|
|
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(ncs-1 downto 0);
|
|
|
cke : in std_logic_vector(ncs-1 downto 0);
|
|
|
cal_en : in std_logic_vector(dbits/8-1 downto 0);
|
|
|
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
|
|
|
cal_rst : in std_logic;
|
|
|
odt : in std_logic_vector(ncs-1 downto 0);
|
|
|
|
|
|
ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
|
|
|
ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0) := (others => 'Z');
|
|
|
ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0) := (others => 'Z');
|
|
|
ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0) := (others => 'Z');
|
|
|
cbdqin : out std_logic_vector(chkbits*2-1 downto 0);
|
|
|
cbdqout : in std_logic_vector(chkbits*2-1 downto 0) := (others => '0');
|
|
|
cbdm : in std_logic_vector(chkbits/4-1 downto 0) := (others => '1');
|
|
|
cbcal_en : in std_logic_vector(chkbits/8-1 downto 0) := (others => '0');
|
|
|
cbcal_inc : in std_logic_vector(chkbits/8-1 downto 0) := (others => '0');
|
|
|
|
|
|
-- Copy of control signals for 2nd DIMM
|
|
|
ddr_web2 : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb2 : out std_ulogic; -- ddr ras
|
|
|
ddr_casb2 : out std_ulogic; -- ddr cas
|
|
|
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
|
|
|
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0) -- ddr bank address
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component stratixii_ddr2_phy
|
|
|
generic (MHz : integer := 100; rstdelay : integer := 200;
|
|
|
dbits : integer := 16; clk_mul : integer := 2 ;
|
|
|
clk_div : integer := 2; eightbanks : integer range 0 to 1 := 0);
|
|
|
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- PLL locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
ddr_odt : out std_logic_vector(1 downto 0);
|
|
|
|
|
|
addr : in std_logic_vector (13 downto 0); -- data mask
|
|
|
ba : in std_logic_vector ( 2 downto 0); -- data mask
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(1 downto 0);
|
|
|
cke : in std_logic_vector(1 downto 0);
|
|
|
cal_en : in std_logic_vector(dbits/8-1 downto 0);
|
|
|
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
|
|
|
cal_rst : in std_logic;
|
|
|
odt : in std_logic_vector(1 downto 0)
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component stratixiii_ddr2_phy
|
|
|
generic (
|
|
|
MHz : integer := 100; rstdelay : integer := 200;
|
|
|
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
|
|
|
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
|
|
|
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
|
|
|
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
|
|
|
numidelctrl : integer := 4; norefclk : integer := 0;
|
|
|
tech : integer := stratix3; rskew : integer := 0;
|
|
|
eightbanks : integer range 0 to 1 := 0);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkref200 : in std_logic; -- input 200MHz clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
|
|
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
|
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
ddr_odt : out std_logic_vector(1 downto 0);
|
|
|
|
|
|
addr : in std_logic_vector (13 downto 0); -- ddr addrees
|
|
|
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(1 downto 0);
|
|
|
cke : in std_logic_vector(1 downto 0);
|
|
|
cal_en : in std_logic_vector(dbits/8-1 downto 0);
|
|
|
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
|
|
|
cal_pll : in std_logic_vector(1 downto 0);
|
|
|
cal_rst : in std_logic;
|
|
|
odt : in std_logic_vector(1 downto 0);
|
|
|
oct : in std_logic
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component spartan3a_ddr2_phy
|
|
|
generic (MHz : integer := 125; rstdelay : integer := 200;
|
|
|
dbits : integer := 16; clk_mul : integer := 2;
|
|
|
clk_div : integer := 2; tech : integer := spartan3;
|
|
|
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0);
|
|
|
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
|
|
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
|
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
ddr_odt : out std_logic_vector(1 downto 0);
|
|
|
|
|
|
addr : in std_logic_vector (13 downto 0);
|
|
|
ba : in std_logic_vector ( 2 downto 0);
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(1 downto 0);
|
|
|
cke : in std_logic_vector(1 downto 0);
|
|
|
cal_pll : in std_logic_vector(1 downto 0);
|
|
|
odt : in std_logic_vector(1 downto 0)
|
|
|
);
|
|
|
end component;
|
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|
|
|
|
component easic90_ddr2_phy
|
|
|
generic (
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|
tech : integer;
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|
MHz : integer;
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|
clk_mul : integer;
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|
|
clk_div : integer;
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|
dbits : integer;
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|
|
rstdelay : integer := 200;
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|
|
eightbanks : integer range 0 to 1 := 0);
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|
|
port (
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|
|
rstn : in std_logic;
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|
|
clk : in std_logic;
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|
|
clkout : out std_ulogic;
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|
|
lock : out std_ulogic;
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_clk_fb_out : out std_ulogic;
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic;
|
|
|
ddr_rasb : out std_ulogic;
|
|
|
ddr_casb : out std_ulogic;
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0);
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0);
|
|
|
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0);
|
|
|
ddr_ad : out std_logic_vector (13 downto 0);
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0);
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0);
|
|
|
ddr_odt : out std_logic_vector(1 downto 0);
|
|
|
addr : in std_logic_vector (13 downto 0);
|
|
|
ba : in std_logic_vector ( 2 downto 0);
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0);
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0);
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0);
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(1 downto 0);
|
|
|
cke : in std_logic_vector(1 downto 0);
|
|
|
odt : in std_logic_vector(1 downto 0);
|
|
|
dqs_gate : in std_ulogic);
|
|
|
end component;
|
|
|
|
|
|
component spartan6_ddr2_phy
|
|
|
generic (MHz : integer := 125; rstdelay : integer := 200;
|
|
|
dbits : integer := 16; clk_mul : integer := 2;
|
|
|
clk_div : integer := 2; tech : integer := spartan3;
|
|
|
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0);
|
|
|
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
|
|
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
|
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
ddr_odt : out std_logic_vector(1 downto 0);
|
|
|
|
|
|
addr : in std_logic_vector (13 downto 0);
|
|
|
ba : in std_logic_vector ( 2 downto 0);
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(1 downto 0);
|
|
|
cke : in std_logic_vector(1 downto 0);
|
|
|
cal_pll : in std_logic_vector(1 downto 0);
|
|
|
odt : in std_logic_vector(1 downto 0)
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component generic_ddr2_phy
|
|
|
generic (MHz : integer := 100; rstdelay : integer := 200;
|
|
|
dbits : integer := 16; clk_mul : integer := 2 ;
|
|
|
clk_div : integer := 2; rskew : integer := 0;
|
|
|
eightbanks: integer := 0; abits: integer := 14;
|
|
|
cben: integer := 0; chkbits: integer := 8);
|
|
|
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
|
|
ddr_clk_fb_out : out std_logic;
|
|
|
ddr_clk_fb : in std_logic;
|
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
|
|
|
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
ddr_odt : out std_logic_vector(1 downto 0);
|
|
|
|
|
|
addr : in std_logic_vector (abits-1 downto 0); -- data mask
|
|
|
ba : in std_logic_vector (2 downto 0); -- data mask
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(1 downto 0);
|
|
|
cke : in std_logic_vector(1 downto 0);
|
|
|
ck : in std_logic_vector(2 downto 0);
|
|
|
odt : in std_logic_vector(1 downto 0);
|
|
|
|
|
|
ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
|
|
|
ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0) := (others => 'Z');
|
|
|
ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0) := (others => 'Z');
|
|
|
ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0) := (others => 'Z');
|
|
|
cbdqin : out std_logic_vector(chkbits*2-1 downto 0);
|
|
|
cbdqout : in std_logic_vector(chkbits*2-1 downto 0) := (others => '0');
|
|
|
cbdm : in std_logic_vector(chkbits/4-1 downto 0) := (others => '1');
|
|
|
cbcal_en : in std_logic_vector(chkbits/8-1 downto 0) := (others => '0');
|
|
|
cbcal_inc : in std_logic_vector(chkbits/8-1 downto 0) := (others => '0')
|
|
|
);
|
|
|
|
|
|
end component;
|
|
|
|
|
|
component n2x_ddr2_phy is
|
|
|
generic (
|
|
|
MHz : integer := 100;
|
|
|
rstdelay : integer := 200;
|
|
|
dbits : integer := 16;
|
|
|
clk_mul : integer := 2;
|
|
|
clk_div : integer := 2;
|
|
|
norefclk : integer := 0;
|
|
|
eightbanks : integer range 0 to 1 := 0;
|
|
|
dqsse : integer range 0 to 1 := 0;
|
|
|
abits : integer := 14;
|
|
|
nclk : integer := 3;
|
|
|
ncs : integer := 2;
|
|
|
ctrl2en : integer := 0);
|
|
|
port (
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_logic; -- input clock
|
|
|
clk270d : in std_logic; -- input clock shifted 270 degrees
|
|
|
-- for operating without PLL
|
|
|
clkout : out std_ulogic; -- system clock
|
|
|
lock : out std_ulogic; -- DCM locked
|
|
|
|
|
|
ddr_clk : out std_logic_vector(nclk-1 downto 0);
|
|
|
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
|
|
|
ddr_cke : out std_logic_vector(ncs-1 downto 0);
|
|
|
ddr_csb : out std_logic_vector(ncs-1 downto 0);
|
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
|
|
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
|
|
|
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
|
|
|
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
|
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
|
|
ddr_odt : out std_logic_vector(ncs-1 downto 0);
|
|
|
|
|
|
addr : in std_logic_vector (abits-1 downto 0); -- ddr address
|
|
|
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
|
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
|
|
oen : in std_ulogic;
|
|
|
dqs : in std_ulogic;
|
|
|
dqsoen : in std_ulogic;
|
|
|
rasn : in std_ulogic;
|
|
|
casn : in std_ulogic;
|
|
|
wen : in std_ulogic;
|
|
|
csn : in std_logic_vector(ncs-1 downto 0);
|
|
|
cke : in std_logic_vector(ncs-1 downto 0);
|
|
|
odt : in std_logic_vector(ncs-1 downto 0);
|
|
|
read_pend : in std_logic_vector(7 downto 0);
|
|
|
regwdata : in std_logic_vector(63 downto 0);
|
|
|
regwrite : in std_logic_vector(1 downto 0);
|
|
|
regrdata : out std_logic_vector(63 downto 0);
|
|
|
|
|
|
-- Copy of control signals for 2nd DIMM
|
|
|
ddr_web2 : out std_ulogic; -- ddr write enable
|
|
|
ddr_rasb2 : out std_ulogic; -- ddr ras
|
|
|
ddr_casb2 : out std_ulogic; -- ddr cas
|
|
|
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
|
|
|
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0) -- ddr bank address
|
|
|
);
|
|
|
|
|
|
end component;
|
|
|
|
|
|
end;
|
|
|
|
