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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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--============================================================================--
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-- Design unit : WildCard Package (package declaration)
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--
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-- File name : wild.vhd
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--
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-- Purpose : WildCard Package
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--
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-- Library : gaisler
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--
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-- Authors : Aeroflex Gaisler AB
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--
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-- Contact : mailto:support@gaisler.com
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-- http://www.gaisler.com
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--
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-- Disclaimer : All information is provided "as is", there is no warranty that
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-- the information is correct or suitable for any purpose,
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-- neither implicit nor explicit.
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--------------------------------------------------------------------------------
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-- Version Author Date Changes
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--
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-- 0.1 SH 1 Jan 2008 New version
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.Std_Logic_1164.all;
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library IEEE;
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use IEEE.Std_Logic_1164.all;
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library grlib;
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use grlib.amba.all;
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package Wild is
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-----------------------------------------------------------------------------
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-- Name Key:
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-- =========
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-- _AS : Address Strobe
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-- _DS : Data Strobe
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-- _WR : Write Select
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-- _CS : Chip Select
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-- _OE : Output Enable
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-- _n : Active low signals (must be last part of name)
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--
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-- Name Width Dir* Description
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-- ==================== ===== ==== =====================================
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-- Addr_Data 32 I Shared address/data bus input
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-- AS_n 1 I Address strobe
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-- DS_n 1 I Data strobe
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-- WR_n 1 I Write select
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-- CS_n 1 I PE chip select
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-- Reg_n 1 I Register mode select
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-- Ack_n 1 O Acknowledge strobe
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-- Addr_Data 32 O Shared address/data bus output
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-- Addr_Data_OE_n 1 O Address/data bus output enable
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-- Int_Req_n 1 O Interrupt request
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-- DMA_0_Data_OK_n 1 O DMA channel 0 data OK flag
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-- DMA_0_Burst_OK_n 1 O DMA channel 0 burst OK flag
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-- DMA_1_Data_OK_n 1 O DMA channel 1 data OK flag
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-- DMA_1_Burst_OK_n 1 O DMA channel 1 burst OK flag
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-- Reg_Data_OK_n 1 O Register space data OK flag
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-- Reg_Burst_OK_n 1 O Register space burst OK flag
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-- Force_K_Clk_n 1 O Forces K_Clk to run when active
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-----------------------------------------------------------------------------
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type LAD_In_Type is record
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Addr_Data: Std_Logic_Vector(31 downto 0); -- Shared address/data bus
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AS_n: Std_Logic; -- Address strobe
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DS_n: Std_Logic; -- Data strobe
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WR_n: Std_Logic; -- Write select
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CS_n: Std_Logic; -- Chip select
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Reg_n: Std_Logic; -- Register select
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end record;
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type LAD_Out_Type is record
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Addr_Data: Std_Logic_Vector(31 downto 0); -- Shared address/data bus output
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Addr_Data_OE_n: Std_Logic_Vector(31 downto 0); -- Address/data bus output enable
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Ack_n: Std_Logic; -- Acknowledge strobe
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Int_Req_n: Std_Logic; -- Interrupt request
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DMA_0_Data_OK_n: Std_Logic; -- DMA chan 0 data OK flag
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DMA_0_Burst_OK: Std_Logic; -- DMA chan 0 burst OK flag
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DMA_1_Data_OK_n: Std_Logic; -- DMA chan 1 data OK flag
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DMA_1_Burst_OK: Std_Logic; -- DMA chan 1 burst OK flag
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Reg_Data_OK_n: Std_Logic; -- Reg space data OK flag
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Reg_Burst_OK: Std_Logic; -- Reg space burst OK flag
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Force_K_Clk_n: Std_Logic; -- K_Clk forced-run select
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Reserved: Std_Logic; -- Reserved for future use
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end record;
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component Wild2AHB is
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generic (
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hindex: in Integer := 0;
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burst: in Integer := 0;
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syncrst: in Integer := 0);
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port (
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rstkn: in Std_ULogic;
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clkk: in Std_ULogic;
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rstfn: in Std_ULogic;
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clkf: in Std_ULogic;
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ahbmi: in AHB_Mst_In_Type;
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ahbmo: out AHB_Mst_Out_Type;
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ladi: in LAD_In_Type;
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lado: out LAD_Out_Type);
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end component;
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end package Wild; --==========================================================--
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