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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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library techmap;
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use techmap.gencomp.all;
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package spacewire is
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type grspw_in_type is record
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d : std_logic_vector(3 downto 0);
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dv : std_logic_vector(3 downto 0);
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s : std_logic_vector(1 downto 0);
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dconnect : std_logic_vector(3 downto 0);
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tickin : std_ulogic;
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tickinraw : std_ulogic;
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timein : std_logic_vector(7 downto 0);
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clkdiv10 : std_logic_vector(7 downto 0);
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rmapen : std_ulogic;
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dcrstval : std_logic_vector(9 downto 0);
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timerrstval : std_logic_vector(11 downto 0);
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end record;
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type grspw_out_type is record
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d : std_logic_vector(3 downto 0);
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s : std_logic_vector(3 downto 0);
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tickout : std_ulogic;
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tickoutraw : std_ulogic;
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tickindone : std_ulogic;
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timeout : std_logic_vector(7 downto 0);
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linkdis : std_ulogic;
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rmapact : std_ulogic;
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rxdataout : std_logic_vector(8 downto 0);
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rxdav : std_ulogic;
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loopback : std_ulogic;
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end record;
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constant grspw_in_none : grspw_in_type :=
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((others => '0'), (others => '0'), (others => '0'),
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(others => '0'), '0', '0', (others => '0'), (others => '0'), '0',
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(others => '0'), (others => '0'));
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constant grspw_out_none : grspw_out_type :=
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((others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
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'0', '0', (others => '0'), '0', '0');
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type grspw_codec_in_type is record
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--spw
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d : std_logic_vector(3 downto 0);
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dv : std_logic_vector(3 downto 0);
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dconnect : std_logic_vector(3 downto 0);
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--link fsm
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linkdisabled : std_ulogic;
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linkstart : std_ulogic;
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autostart : std_ulogic;
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portsel : std_ulogic;
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noportforce : std_ulogic;
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rdivisor : std_logic_vector(7 downto 0);
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idivisor : std_logic_vector(7 downto 0);
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--rx iface
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rxiread : std_ulogic;
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rxififorst : std_ulogic;
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--tx iface
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txiwrite : std_ulogic;
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txichar : std_logic_vector(8 downto 0);
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txififorst : std_ulogic;
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--time iface
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tickin : std_ulogic;
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timein : std_logic_vector(7 downto 0);
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end record;
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type grspw_codec_out_type is record
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--spw
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do : std_logic_vector(3 downto 0);
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so : std_logic_vector(3 downto 0);
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--link fsm
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state : std_logic_vector(2 downto 0);
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actport : std_ulogic;
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dconnecterr : std_ulogic;
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crederr : std_ulogic;
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escerr : std_ulogic;
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parerr : std_ulogic;
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--rx iface
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rxicharav : std_ulogic;
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rxicharcnt : std_logic_vector(11 downto 0);
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rxichar : std_logic_vector(8 downto 0);
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--tx iface
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txicharcnt : std_logic_vector(11 downto 0);
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txifull : std_ulogic;
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txiempty : std_ulogic;
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txififorst : std_ulogic;
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--time iface
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tickin_done : std_ulogic;
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tickout : std_ulogic;
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timeout : std_logic_vector(7 downto 0);
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merror : std_ulogic;
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end record;
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type grspw_dma_in_type is record
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--rx iface
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rxiread : std_ulogic;
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--tx iface
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txiwrite : std_ulogic;
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txichar : std_logic_vector(8 downto 0);
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txififorst : std_ulogic;
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--internal time iface
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itickin : std_ulogic;
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itimein : std_logic_vector(7 downto 0);
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--time iface
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tickin : std_ulogic;
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timein : std_logic_vector(7 downto 0);
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rmapen : std_ulogic;
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end record;
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type grspw_dma_out_type is record
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--rx iface
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rxicharav : std_ulogic;
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rxichar : std_logic_vector(8 downto 0);
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--tx iface
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txicharcnt : std_logic_vector(11 downto 0);
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txifull : std_ulogic;
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txififorst : std_ulogic;
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--internal time iface
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itickout : std_ulogic;
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itimeout : std_logic_vector(7 downto 0);
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--time iface
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tickin_done : std_ulogic;
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tickout : std_ulogic;
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timeout : std_logic_vector(7 downto 0);
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merror : std_ulogic;
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end record;
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type grspw_fifo_in_type is record
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enbridge : std_ulogic;
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--rx iface
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rxiread : std_ulogic;
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--tx iface
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txiwrite : std_ulogic;
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txichar : std_logic_vector(8 downto 0);
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txififorst : std_ulogic;
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--internal time iface
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itickin : std_ulogic;
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itimein : std_logic_vector(7 downto 0);
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--time iface
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tickin : std_ulogic;
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timein : std_logic_vector(7 downto 0);
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enexttime : std_ulogic;
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rmapen : std_ulogic;
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--external interface
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etxwrite : std_ulogic;
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etxchar : std_logic_vector(8 downto 0);
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erxread : std_ulogic;
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end record;
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type grspw_fifo_out_type is record
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--rx iface
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rxicharcnt : std_logic_vector(11 downto 0);
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rxicharav : std_ulogic;
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rxichar : std_logic_vector(8 downto 0);
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--tx iface
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txicharcnt : std_logic_vector(11 downto 0);
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txifull : std_ulogic;
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txififorst : std_ulogic;
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--internal time iface
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itickout : std_ulogic;
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itimeout : std_logic_vector(7 downto 0);
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ienexttime : std_ulogic;
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--time iface
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tickin_done : std_ulogic;
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tickout : std_ulogic;
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timeout : std_logic_vector(7 downto 0);
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--external interface
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erxcharav : std_ulogic;
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erxaempty : std_ulogic;
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etxfull : std_ulogic;
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etxafull : std_ulogic;
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erxchar : std_logic_vector(8 downto 0);
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merror : std_ulogic;
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end record;
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type grspw_router_fifo_char_type is array (0 to 30) of std_logic_vector(8 downto 0);
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type grspw_router_time_type is array (0 to 30) of std_logic_vector(7 downto 0);
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type grspw_router_in_type is record
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rmapen : std_logic_vector(30 downto 0);
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idivisor : std_logic_vector(7 downto 0);
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txwrite : std_logic_vector(30 downto 0);
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txchar : grspw_router_fifo_char_type;
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rxread : std_logic_vector(30 downto 0);
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tickin : std_logic_vector(30 downto 0);
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timein : grspw_router_time_type;
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reload : std_logic_vector(31 downto 0);
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reloadn : std_logic_vector(9 downto 0);
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timeren : std_ulogic;
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timecodeen : std_ulogic;
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cfglock : std_ulogic;
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selfaddren : std_ulogic;
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linkstartreq : std_ulogic;
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autodconnect : std_ulogic;
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instanceid : std_logic_vector(7 downto 0);
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enbridge : std_logic_vector(30 downto 0);
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enexttime : std_logic_vector(30 downto 0);
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end record;
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type grspw_router_out_type is record
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rxcharav : std_logic_vector(30 downto 0);
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rxaempty : std_logic_vector(30 downto 0);
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txfull : std_logic_vector(30 downto 0);
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txafull : std_logic_vector(30 downto 0);
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rxchar : grspw_router_fifo_char_type;
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tickout : std_logic_vector(30 downto 0);
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timeout : grspw_router_time_type;
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merror : std_ulogic;
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gerror : std_ulogic;
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lerror : std_ulogic;
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linkrun : std_logic_vector(30 downto 0);
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--debug
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tick : std_ulogic;
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timetx : std_logic_vector(5 downto 0);
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s0currport : std_logic_vector(3 downto 0);
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s1currport : std_logic_vector(3 downto 0);
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s0charav : std_ulogic;
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s1charav : std_ulogic;
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rtvalid : std_ulogic;
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pevalid : std_ulogic;
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s1char : std_logic_vector(8 downto 0);
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p0insel : std_logic_vector(3 downto 0);
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p0rxactive : std_ulogic;
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p0txactive : std_ulogic;
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p0active : std_ulogic;
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p0headerdel : std_ulogic;
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p0spill : std_ulogic;
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p0charav : std_ulogic;
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p0invaddr : std_ulogic;
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p0bufav : std_ulogic;
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p0pktdist : std_ulogic;
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p0ports : std_logic_vector(12 downto 0);
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p1insel : std_logic_vector(3 downto 0);
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p1rxactive : std_ulogic;
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p1txactive : std_ulogic;
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p1active : std_ulogic;
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p1headerdel : std_ulogic;
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p1spill : std_ulogic;
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p1charav : std_ulogic;
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p1invaddr : std_ulogic;
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p1bufav : std_ulogic;
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p1pktdist : std_ulogic;
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p1ports : std_logic_vector(12 downto 0);
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rmapstate : std_logic_vector(4 downto 0);
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rmapen : std_logic_vector(30 downto 0);
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idivisor : std_logic_vector(7 downto 0);
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end record;
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constant grspw_router_in_none : grspw_router_in_type :=
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((others => '0'), (others => '0'), (others => '0'), (others => (others => '0')),
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(others => '0'), (others => '0'), (others => (others => '0')), (others => '0'),
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(others => '0'), '0', '0', '0', '0', '0', '0', (others => '0'), (others => '0'),
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(others => '0'));
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constant grspw_router_out_none : grspw_router_out_type :=
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((others => '0'), (others => '0'), (others => '0'), (others => '0'),
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(others => (others => '0')), (others => '0'), (others => (others => '0')), '0',
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'0', '0', (others => '0'), '0', (others => '0'), (others => '0'), (others => '0'),
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'0', '0', '0', '0', (others => '0'), (others => '0'), '0', '0', '0', '0', '0',
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'0', '0', '0', '0', (others => '0'), (others => '0'), '0', '0', '0', '0', '0',
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'0', '0', '0', '0', (others => '0'), (others => '0'), (others => '0'),
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(others => '0'));
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type spw_ahb_mst_out_vector is array (natural range <>) of
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ahb_mst_out_type;
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type spw_apb_slv_out_vector is array (natural range <>) of
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apb_slv_out_type;
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component grspw2_phy is
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generic(
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scantest : integer;
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tech : integer;
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input_type : integer --0=xor, 1=sample sdr, 2=sample ddr, 3=aeroflex phy
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);
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port(
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rstn : in std_ulogic;
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rxclki : in std_ulogic;
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rxclkin : in std_ulogic;
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nrxclki : in std_ulogic;
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di : in std_ulogic;
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si : in std_ulogic; --used as df when input_type=3
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do : out std_logic_vector(1 downto 0);
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dov : out std_logic_vector(1 downto 0);
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dconnect : out std_logic_vector(1 downto 0);
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rxclko : out std_ulogic;
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testrst : in std_ulogic := '0';
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testen : in std_ulogic := '0'
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);
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end component;
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component grspw2 is
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generic(
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tech : integer range 0 to NTECH := inferred;
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hindex : integer range 0 to NAHBMST-1 := 0;
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pindex : integer range 0 to NAPBSLV-1 := 0;
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paddr : integer range 0 to 16#FFF# := 0;
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pmask : integer range 0 to 16#FFF# := 16#FFF#;
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pirq : integer range 0 to NAHBIRQ-1 := 0;
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rmap : integer range 0 to 1 := 0;
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rmapcrc : integer range 0 to 1 := 0;
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fifosize1 : integer range 4 to 32 := 32;
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fifosize2 : integer range 16 to 64 := 64;
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rxclkbuftype : integer range 0 to 2 := 0;
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rxunaligned : integer range 0 to 1 := 0;
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rmapbufs : integer range 2 to 8 := 4;
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ft : integer range 0 to 2 := 0;
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scantest : integer range 0 to 1 := 0;
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techfifo : integer range 0 to 1 := 1;
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ports : integer range 1 to 2 := 1;
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dmachan : integer range 1 to 4 := 1;
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memtech : integer range 0 to NTECH := DEFMEMTECH;
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input_type : integer range 0 to 3 := 0;
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output_type : integer range 0 to 2 := 0;
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rxtx_sameclk : integer range 0 to 1 := 0;
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netlist : integer range 0 to 1 := 0
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);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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rxclk0 : in std_ulogic;
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rxclk1 : in std_ulogic;
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txclk : in std_ulogic;
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txclkn : in std_ulogic;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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swni : in grspw_in_type;
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swno : out grspw_out_type
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);
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end component;
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component grspw is
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generic(
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tech : integer range 0 to NTECH := DEFFABTECH;
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hindex : integer range 0 to NAHBMST-1 := 0;
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pindex : integer range 0 to NAPBSLV-1 := 0;
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paddr : integer range 0 to 16#FFF# := 0;
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pmask : integer range 0 to 16#FFF# := 16#FFF#;
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pirq : integer range 0 to NAHBIRQ-1 := 0;
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sysfreq : integer := 10000;
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usegen : integer range 0 to 1 := 1;
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nsync : integer range 1 to 2 := 1;
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rmap : integer range 0 to 2 := 0;
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rmapcrc : integer range 0 to 1 := 0;
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fifosize1 : integer range 4 to 32 := 32;
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fifosize2 : integer range 16 to 64 := 64;
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rxclkbuftype : integer range 0 to 2 := 0;
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rxunaligned : integer range 0 to 1 := 0;
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rmapbufs : integer range 2 to 8 := 4;
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ft : integer range 0 to 2 := 0;
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scantest : integer range 0 to 1 := 0;
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techfifo : integer range 0 to 1 := 1;
|
|
|
netlist : integer range 0 to 1 := 0;
|
|
|
ports : integer range 1 to 2 := 1;
|
|
|
memtech : integer range 0 to NTECH := DEFMEMTECH;
|
|
|
nodeaddr : integer range 0 to 255 := 254;
|
|
|
destkey : integer range 0 to 255 := 0
|
|
|
);
|
|
|
port(
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
txclk : in std_ulogic;
|
|
|
ahbmi : in ahb_mst_in_type;
|
|
|
ahbmo : out ahb_mst_out_type;
|
|
|
apbi : in apb_slv_in_type;
|
|
|
apbo : out apb_slv_out_type;
|
|
|
swni : in grspw_in_type;
|
|
|
swno : out grspw_out_type);
|
|
|
end component;
|
|
|
|
|
|
type grspw_in_type_vector is array (natural range <>) of grspw_in_type;
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|
type grspw_out_type_vector is array (natural range <>) of grspw_out_type;
|
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|
|
|
|
component grspwm is
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|
|
generic(
|
|
|
tech : integer range 0 to NTECH := DEFFABTECH;
|
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|
hindex : integer range 0 to NAHBMST-1 := 0;
|
|
|
pindex : integer range 0 to NAPBSLV-1 := 0;
|
|
|
paddr : integer range 0 to 16#FFF# := 0;
|
|
|
pmask : integer range 0 to 16#FFF# := 16#FFF#;
|
|
|
pirq : integer range 0 to NAHBIRQ-1 := 0;
|
|
|
sysfreq : integer := 10000;
|
|
|
usegen : integer range 0 to 1 := 1;
|
|
|
nsync : integer range 1 to 2 := 1;
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|
|
rmap : integer range 0 to 2 := 0;
|
|
|
rmapcrc : integer range 0 to 1 := 0;
|
|
|
fifosize1 : integer range 4 to 32 := 32;
|
|
|
fifosize2 : integer range 16 to 64 := 64;
|
|
|
rxclkbuftype : integer range 0 to 2 := 0;
|
|
|
rxunaligned : integer range 0 to 1 := 0;
|
|
|
rmapbufs : integer range 2 to 8 := 4;
|
|
|
ft : integer range 0 to 2 := 0;
|
|
|
scantest : integer range 0 to 1 := 0;
|
|
|
techfifo : integer range 0 to 1 := 1;
|
|
|
netlist : integer range 0 to 1 := 0;
|
|
|
ports : integer range 1 to 2 := 1;
|
|
|
dmachan : integer range 1 to 4 := 1;
|
|
|
memtech : integer range 0 to NTECH := DEFMEMTECH;
|
|
|
spwcore : integer range 1 to 2 := 2;
|
|
|
input_type : integer range 0 to 3 := 0;
|
|
|
output_type : integer range 0 to 2 := 0;
|
|
|
rxtx_sameclk : integer range 0 to 1 := 0
|
|
|
);
|
|
|
port(
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
rxclk0 : in std_ulogic;
|
|
|
rxclk1 : in std_ulogic;
|
|
|
txclk : in std_ulogic;
|
|
|
txclkn : in std_ulogic;
|
|
|
ahbmi : in ahb_mst_in_type;
|
|
|
ahbmo : out ahb_mst_out_type;
|
|
|
apbi : in apb_slv_in_type;
|
|
|
apbo : out apb_slv_out_type;
|
|
|
swni : in grspw_in_type;
|
|
|
swno : out grspw_out_type
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component grspw_codec is
|
|
|
generic(
|
|
|
ports : integer range 1 to 2 := 1;
|
|
|
input_type : integer range 0 to 3 := 0;
|
|
|
output_type : integer range 0 to 2 := 0;
|
|
|
rxtx_sameclk : integer range 0 to 1 := 0;
|
|
|
fifosize : integer range 16 to 2048 := 64;
|
|
|
tech : integer;
|
|
|
scantest : integer range 0 to 1 := 0;
|
|
|
techfifo : integer range 0 to 1 := 0;
|
|
|
ft : integer range 0 to 2 := 0
|
|
|
);
|
|
|
port(
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
rxclk0 : in std_ulogic;
|
|
|
rxclk1 : in std_ulogic;
|
|
|
txclk : in std_ulogic;
|
|
|
txclkn : in std_ulogic;
|
|
|
testen : in std_ulogic;
|
|
|
testrst : in std_ulogic;
|
|
|
lii : in grspw_codec_in_type;
|
|
|
lio : out grspw_codec_out_type
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component grspwrouter is
|
|
|
generic(
|
|
|
input_type : integer range 0 to 3 := 0;
|
|
|
output_type : integer range 0 to 2 := 0;
|
|
|
rxtx_sameclk : integer range 0 to 1 := 0;
|
|
|
fifosize : integer range 16 to 2048 := 64;
|
|
|
tech : integer;
|
|
|
scantest : integer range 0 to 1 := 0;
|
|
|
techfifo : integer range 0 to 1 := 0;
|
|
|
ft : integer range 0 to 2 := 0;
|
|
|
spwen : integer range 0 to 1 := 1;
|
|
|
ambaen : integer range 0 to 1 := 0;
|
|
|
fifoen : integer range 0 to 1 := 0;
|
|
|
spwports : integer range 0 to 31 := 2;
|
|
|
ambaports : integer range 0 to 16 := 0;
|
|
|
fifoports : integer range 0 to 31 := 0;
|
|
|
arbitration : integer range 0 to 1 := 0; --0=rrobin, 1=priority
|
|
|
rmap : integer range 0 to 16#FFFF# := 0;
|
|
|
rmapcrc : integer range 0 to 16#FFFF# := 0;
|
|
|
fifosize2 : integer range 4 to 32 := 32;
|
|
|
almostsize : integer range 1 to 32 := 8;
|
|
|
rxunaligned : integer range 0 to 16#FFFF# := 0;
|
|
|
rmapbufs : integer range 2 to 8 := 4;
|
|
|
dmachan : integer range 1 to 4 := 1;
|
|
|
hindex : integer range 0 to NAHBMST-1 := 0;
|
|
|
pindex : integer range 0 to NAPBSLV-1 := 0;
|
|
|
paddr : integer range 0 to 16#FFF# := 0;
|
|
|
pmask : integer range 0 to 16#FFF# := 16#FFF#;
|
|
|
pirq : integer range 0 to NAHBIRQ-1 := 0;
|
|
|
cfghindex : integer range 0 to NAHBSLV-1 := 0;
|
|
|
cfghaddr : integer range 0 to 16#FFF# := 0;
|
|
|
cfghmask : integer range 0 to 16#FFF# := 16#FF0#;
|
|
|
ahbslven : integer range 0 to 1 := 0;
|
|
|
timerbits : integer range 0 to 31 := 0;
|
|
|
pnp : integer range 0 to 1 := 0;
|
|
|
autoscrub : integer range 0 to 1 := 0;
|
|
|
sim : integer range 0 to 1 := 0;
|
|
|
dualport : integer range 0 to 1 := 0;
|
|
|
charcntbits : integer range 0 to 32 := 0;
|
|
|
pktcntbits : integer range 0 to 32 := 0;
|
|
|
prescalermin : integer := 250
|
|
|
);
|
|
|
port(
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
rxclk : in std_logic_vector(spwports*(1+dualport)-spwen downto 0);
|
|
|
txclk : in std_ulogic;
|
|
|
txclkn : in std_ulogic;
|
|
|
testen : in std_ulogic;
|
|
|
testrst : in std_ulogic;
|
|
|
testin : in std_ulogic;
|
|
|
di : in std_logic_vector(spwports*(2+2*dualport)-spwen downto 0);
|
|
|
dvi : in std_logic_vector(spwports*(2+2*dualport)-spwen downto 0);
|
|
|
dconnect : in std_logic_vector(spwports*(2+2*dualport)-spwen downto 0);
|
|
|
do : out std_logic_vector(spwports*(2+2*dualport)-spwen downto 0);
|
|
|
so : out std_logic_vector(spwports*(2+2*dualport)-spwen downto 0);
|
|
|
ahbmi : in ahb_mst_in_type;
|
|
|
ahbmo : out spw_ahb_mst_out_vector(0 to ambaports*ambaen-ambaen);
|
|
|
apbi : in apb_slv_in_type;
|
|
|
apbo : out spw_apb_slv_out_vector(0 to ambaports*ambaen-ambaen);
|
|
|
ahbsi : in ahb_slv_in_type;
|
|
|
ahbso : out ahb_slv_out_type;
|
|
|
ri : in grspw_router_in_type;
|
|
|
ro : out grspw_router_out_type
|
|
|
);
|
|
|
end component grspwrouter;
|
|
|
|
|
|
component grspw2_dma is
|
|
|
generic(
|
|
|
hindex : integer range 0 to NAHBMST-1 := 0;
|
|
|
pindex : integer range 0 to NAPBSLV-1:= 0;
|
|
|
pirq : integer range 0 to NAHBIRQ-1 := 0;
|
|
|
paddr : integer range 0 to 16#FFF# := 0;
|
|
|
pmask : integer range 0 to 16#FFF# := 16#FFF#;
|
|
|
rmap : integer range 0 to 1 := 0;
|
|
|
rmapcrc : integer range 0 to 1 := 0;
|
|
|
fifosize1 : integer range 4 to 32 := 32;
|
|
|
fifosize2 : integer range 16 to 2048 := 64;
|
|
|
rxunaligned : integer range 0 to 1 := 0;
|
|
|
rmapbufs : integer range 2 to 8 := 4;
|
|
|
scantest : integer range 0 to 1 := 0;
|
|
|
dmachan : integer range 1 to 4 := 1;
|
|
|
tech : integer range 0 to NTECH := inferred;
|
|
|
techfifo : integer range 0 to 1 := 1;
|
|
|
ft : integer range 0 to 2 := 0
|
|
|
);
|
|
|
port(
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
--ahb mst
|
|
|
ahbmi : in ahb_mst_in_type;
|
|
|
ahbmo : out ahb_mst_out_type;
|
|
|
--apb
|
|
|
apbi : in apb_slv_in_type;
|
|
|
apbo : out apb_slv_out_type;
|
|
|
--link
|
|
|
lii : in grspw_dma_in_type;
|
|
|
lio : out grspw_dma_out_type;
|
|
|
testrst : in std_ulogic := '0';
|
|
|
testen : in std_ulogic := '0'
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component grspw2_fifo is
|
|
|
generic(
|
|
|
fifosize : integer range 16 to 2048 := 64;
|
|
|
almostsize : integer range 1 to 32 := 8;
|
|
|
scantest : integer range 0 to 1 := 0;
|
|
|
tech : integer range 0 to NTECH := inferred;
|
|
|
techfifo : integer range 0 to 1 := 1;
|
|
|
ft : integer range 0 to 2 := 0
|
|
|
);
|
|
|
port(
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
--link
|
|
|
lii : in grspw_fifo_in_type;
|
|
|
lio : out grspw_fifo_out_type;
|
|
|
testrst : in std_ulogic := '0';
|
|
|
testen : in std_ulogic := '0'
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
end package;
|
|
|
|
