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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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-- pragma translate_off
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use std.textio.all;
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-- pragma translate_on
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library lpp;
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use lpp.lpp_amba.all;
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package lpp_uart is
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component UART is
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generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
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port(
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clk : in std_logic; --! Horloge a 25Mhz du systeme
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reset : in std_logic; --! Reset du systeme
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TXD : out std_logic; --! Transmission, cote PC
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RXD : in std_logic; --! Reception, cote PC
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Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
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NwDat : out std_logic; --! Flag, Nouvelle donnee presente
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ACK : in std_logic; --! Flag, Reponse au flag precedent
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Send : in std_logic; --! Flag, Demande d'envoi sur le bus
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Sended : out std_logic; --! Flag, Envoi termine
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BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
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RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Current read word
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WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
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);
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end component;
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component Shift_Reg is
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generic(
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Data_sz : integer := 10 --! Width of the shift register
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);
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port(
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Sclk : in std_logic; --! Serial clock
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SIN : in std_logic; --! Serial data in
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SOUT : out std_logic; --! Serial data out
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Serialize : in std_logic; --! Launch serialization
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Serialized : out std_logic; --! Serialization complete
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D : in std_logic_vector(Data_sz-1 downto 0); --! Parallel data to be shifted out
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Q : out std_logic_vector(Data_sz-1 downto 0) --! Unserialized data
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);
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end component;
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component BaudGen is
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port(
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clk : in std_logic;
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reset : in std_logic;
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Capture : in std_logic;
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Bclk : out std_logic;
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RXD : in std_logic;
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BTrigger : out std_logic_vector(11 downto 0)
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);
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end component;
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component APB_UART is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8;
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Data_sz : integer := 8);
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port (
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clk : in std_logic;
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rst : in std_logic;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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TXD : out std_logic;
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RXD : in std_logic
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);
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end component;
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end lpp_uart;
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