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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: libiu
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-- File: libiu.vhd
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-- Author: Jiri Gaisler Gaisler Research
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-- Description: LEON3 IU types and components
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.leon3.all;
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use gaisler.arith.all;
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use gaisler.mmuconfig.all;
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--library fpu;
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--use fpu.libfpu.all;
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package libiu is
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constant RDBITS : integer := 32;
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constant IDBITS : integer := 32;
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subtype cword is std_logic_vector(IDBITS-1 downto 0);
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type cdatatype is array (0 to 3) of cword;
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--type ctagpartype is array (0 to 3) of std_logic_vector(1 downto 0);
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--type cdatapartype is array (0 to 3) of std_logic_vector(3 downto 0);
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--type cvalidtype is array (0 to 3) of std_logic_vector(7 downto 0);
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type cpartype is array (0 to 3) of std_logic_vector(3 downto 0); -- byte parity
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type iregfile_in_type is record
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raddr1 : std_logic_vector(9 downto 0); -- read address 1
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raddr2 : std_logic_vector(9 downto 0); -- read address 2
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waddr : std_logic_vector(9 downto 0); -- write address
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wdata : std_logic_vector(31 downto 0); -- write data
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ren1 : std_ulogic; -- read 1 enable
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ren2 : std_ulogic; -- read 2 enable
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wren : std_ulogic; -- write enable
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diag : std_logic_vector(3 downto 0); -- write data
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end record;
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type iregfile_out_type is record
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data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
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data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
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end record;
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type cctrltype is record
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burst : std_ulogic; -- icache burst enable
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dfrz : std_ulogic; -- dcache freeze enable
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ifrz : std_ulogic; -- icache freeze enable
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dsnoop : std_ulogic; -- data cache snooping
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dcs : std_logic_vector(1 downto 0); -- dcache state
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ics : std_logic_vector(1 downto 0); -- icache state
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end record;
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type icache_in_type is record
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rpc : std_logic_vector(31 downto 0); -- raw address (npc)
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fpc : std_logic_vector(31 downto 0); -- latched address (fpc)
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dpc : std_logic_vector(31 downto 0); -- latched address (dpc)
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rbranch : std_ulogic; -- Instruction branch
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fbranch : std_ulogic; -- Instruction branch
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inull : std_ulogic; -- instruction nullify
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su : std_ulogic; -- super-user
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flush : std_ulogic; -- flush icache
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flushl : std_ulogic; -- flush line
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fline : std_logic_vector(31 downto 3); -- flush line offset
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pnull : std_ulogic;
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end record;
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type icache_out_type is record
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data : cdatatype;
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set : std_logic_vector(1 downto 0);
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mexc : std_ulogic;
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hold : std_ulogic;
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flush : std_ulogic; -- flush in progress
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diagrdy : std_ulogic; -- diagnostic access ready
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diagdata : std_logic_vector(IDBITS-1 downto 0);-- diagnostic data
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mds : std_ulogic; -- memory data strobe
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cfg : std_logic_vector(31 downto 0);
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idle : std_ulogic; -- idle mode
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cstat : l3_cstat_type;
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end record;
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type icdiag_in_type is record
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addr : std_logic_vector(31 downto 0); -- memory stage address
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enable : std_ulogic;
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read : std_ulogic;
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tag : std_ulogic;
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ctx : std_ulogic;
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flush : std_ulogic;
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ilramen : std_ulogic;
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cctrl : cctrltype;
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pflush : std_ulogic;
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pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
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pflushtyp : std_ulogic;
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ilock : std_logic_vector(0 to 3);
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scanen : std_ulogic;
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end record;
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type dcache_in_type is record
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asi : std_logic_vector(7 downto 0);
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maddress : std_logic_vector(31 downto 0);
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eaddress : std_logic_vector(31 downto 0);
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edata : std_logic_vector(31 downto 0);
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size : std_logic_vector(1 downto 0);
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enaddr : std_ulogic;
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eenaddr : std_ulogic;
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nullify : std_ulogic;
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lock : std_ulogic;
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read : std_ulogic;
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write : std_ulogic;
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flush : std_ulogic;
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flushl : std_ulogic; -- flush line
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dsuen : std_ulogic;
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msu : std_ulogic; -- memory stage supervisor
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esu : std_ulogic; -- execution stage supervisor
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intack : std_ulogic;
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end record;
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type dcache_out_type is record
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data : cdatatype;
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set : std_logic_vector(1 downto 0);
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mexc : std_ulogic;
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hold : std_ulogic;
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mds : std_ulogic;
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werr : std_ulogic;
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icdiag : icdiag_in_type;
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cache : std_ulogic;
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idle : std_ulogic; -- idle mode
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scanen : std_ulogic;
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testen : std_ulogic;
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end record;
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component iu3
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generic (
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nwin : integer range 2 to 32 := 8;
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isets : integer range 1 to 4 := 1;
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dsets : integer range 1 to 4 := 1;
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fpu : integer range 0 to 15 := 0;
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v8 : integer range 0 to 63 := 0;
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cp, mac : integer range 0 to 1 := 0;
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dsu : integer range 0 to 1 := 0;
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nwp : integer range 0 to 4 := 0;
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pclow : integer range 0 to 2 := 2;
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notag : integer range 0 to 1 := 0;
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index : integer range 0 to 15:= 0;
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lddel : integer range 1 to 2 := 2;
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irfwt : integer range 0 to 1 := 0;
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disas : integer range 0 to 2 := 0;
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tbuf : integer range 0 to 64 := 0; -- trace buf size in kB (0 - no trace buffer)
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pwd : integer range 0 to 2 := 0; -- power-down
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svt : integer range 0 to 1 := 0; -- single-vector trapping
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rstaddr : integer := 0;
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smp : integer range 0 to 15 := 0; -- support SMP systems
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fabtech : integer range 0 to NTECH := 0;
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clk2x : integer := 0;
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bp : integer := 1
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);
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port (
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clk : in std_ulogic;
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rstn : in std_ulogic;
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holdn : in std_ulogic;
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ici : out icache_in_type;
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ico : in icache_out_type;
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dci : out dcache_in_type;
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dco : in dcache_out_type;
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rfi : out iregfile_in_type;
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rfo : in iregfile_out_type;
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irqi : in l3_irq_in_type;
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irqo : out l3_irq_out_type;
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dbgi : in l3_debug_in_type;
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dbgo : out l3_debug_out_type;
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muli : out mul32_in_type;
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mulo : in mul32_out_type;
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divi : out div32_in_type;
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divo : in div32_out_type;
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fpo : in fpc_out_type;
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fpi : out fpc_in_type;
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cpo : in fpc_out_type;
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cpi : out fpc_in_type;
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tbo : in tracebuf_out_type;
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tbi : out tracebuf_in_type;
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sclk : in std_ulogic
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);
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end component;
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-- disassembly dummy module
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component cpu_disasx is
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port (
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clk : in std_ulogic;
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rstn : in std_ulogic;
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dummy : out std_ulogic;
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inst : in std_logic_vector(31 downto 0);
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pc : in std_logic_vector(31 downto 2);
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result: in std_logic_vector(31 downto 0);
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index : in std_logic_vector(3 downto 0);
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wreg : in std_ulogic;
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annul : in std_ulogic;
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holdn : in std_ulogic;
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pv : in std_ulogic;
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trap : in std_ulogic;
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disas : in std_ulogic);
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end component;
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end;
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