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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: libdcom
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-- File: libdcom.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Types, functions and components for DSU uart
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library gaisler;
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use gaisler.uart.all;
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use gaisler.misc.all;
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package libdcom is
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type dcom_uart_in_type is record
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read : std_ulogic;
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write : std_ulogic;
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data : std_logic_vector(7 downto 0);
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end record;
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type dcom_uart_out_type is record
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dready : std_ulogic;
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tsempty : std_ulogic;
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thempty : std_ulogic;
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lock : std_ulogic;
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enable : std_ulogic;
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data : std_logic_vector(7 downto 0);
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end record;
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component dcom_uart
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ui : in uart_in_type;
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uo : out uart_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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uarti : in dcom_uart_in_type;
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uarto : out dcom_uart_out_type
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);
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end component;
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component dcom
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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dmai : out ahb_dma_in_type;
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dmao : in ahb_dma_out_type;
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uarti : out dcom_uart_in_type;
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uarto : in dcom_uart_out_type;
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ahbi : in ahb_mst_in_type
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);
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end component;
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-- pragma translate_off
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procedure rxc(signal rxd : in std_logic; d: out std_logic_vector;
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txperiod : time);
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procedure rxi(signal rxd : in std_logic; d: out std_logic_vector;
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txperiod : time; lresp : boolean);
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procedure txc(signal txd : out std_logic; td : integer;
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txperiod : time);
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procedure txa(signal txd : out std_logic; td1, td2, td3, td4 : integer;
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txperiod : time);
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procedure txi(signal rxd : in std_logic; signal txd : out std_logic;
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td1, td2, td3, td4 : integer; txperiod : time;
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lresp : boolean);
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-- pragma translate_on
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end;
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-- pragma translate_off
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package body libdcom is
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procedure rxc(signal rxd : in std_logic; d: out std_logic_vector;
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txperiod : time) is
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variable rxdata : std_logic_vector(7 downto 0);
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begin
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wait until rxd = '0'; wait for TXPERIOD/2;
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for i in 0 to 7 loop wait for TXPERIOD; rxdata(i):= rxd; end loop;
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wait for TXPERIOD ;
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d := rxdata;
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end;
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procedure rxi(signal rxd : in std_logic; d: out std_logic_vector;
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txperiod : time; lresp : boolean) is
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variable rxdata : std_logic_vector(31 downto 0);
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variable resp : std_logic_vector(7 downto 0);
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begin
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for i in 3 downto 0 loop
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rxc(rxd, rxdata((i*8 +7) downto i*8), txperiod);
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end loop;
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d := rxdata;
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if LRESP then
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rxc(rxd, resp, txperiod);
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-- print("RESP : 0x" & tosth(resp));
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end if;
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end;
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procedure txc(signal txd : out std_logic; td : integer;
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txperiod : time) is
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variable txdata : std_logic_vector(10 downto 0);
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begin
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txdata := "11" & conv_std_logic_vector(td, 8) & '0';
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for i in 0 to 10 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
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end;
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procedure txa(signal txd : out std_logic; td1, td2, td3, td4 : integer;
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txperiod : time) is
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variable txdata : std_logic_vector(43 downto 0);
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begin
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txdata := "11" & conv_std_logic_vector(td4, 8) & '0'
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& "11" & conv_std_logic_vector(td3, 8) & '0'
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& "11" & conv_std_logic_vector(td2, 8) & '0'
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& "11" & conv_std_logic_vector(td1, 8) & '0';
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for i in 0 to 43 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
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end;
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procedure txi(signal rxd : in std_logic; signal txd : out std_logic;
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td1, td2, td3, td4 : integer; txperiod : time;
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lresp : boolean) is
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variable txdata : std_logic_vector(43 downto 0);
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begin
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txdata := "11" & conv_std_logic_vector(td4, 8) & '0'
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& "11" & conv_std_logic_vector(td3, 8) & '0'
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& "11" & conv_std_logic_vector(td2, 8) & '0'
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& "11" & conv_std_logic_vector(td1, 8) & '0';
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for i in 0 to 43 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
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if LRESP then
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rxc(rxd, txdata(7 downto 0), txperiod);
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-- print("RESP : 0x" & tosth(txdata(7 downto 0)));
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end if;
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end;
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end;
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-- pragma translate_on
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