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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package general_purpose is
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component Clk_divider is
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generic(OSC_freqHz : integer := 50000000;
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TargetFreq_Hz : integer := 50000);
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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clk_divided : out STD_LOGIC);
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end component;
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component Adder is
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generic(
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Input_SZ_A : integer := 16;
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Input_SZ_B : integer := 16
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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clr : in std_logic;
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add : in std_logic;
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OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
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OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
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RES : out std_logic_vector(Input_SZ_A-1 downto 0)
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);
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end component;
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component ADDRcntr is
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port(
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clk : in std_logic;
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reset : in std_logic;
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count : in std_logic;
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clr : in std_logic;
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Q : out std_logic_vector(7 downto 0)
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);
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end component;
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component ALU is
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generic(
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Arith_en : integer := 1;
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Logic_en : integer := 1;
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Input_SZ_1 : integer := 16;
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Input_SZ_2 : integer := 9
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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ctrl : in std_logic_vector(3 downto 0);
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OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
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OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
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RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
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);
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end component;
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component MAC is
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generic(
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Input_SZ_A : integer := 8;
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Input_SZ_B : integer := 8
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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clr_MAC : in std_logic;
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MAC_MUL_ADD : in std_logic_vector(1 downto 0);
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OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
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OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
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RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
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);
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end component;
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component MAC_CONTROLER is
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port(
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ctrl : in std_logic_vector(1 downto 0);
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MULT : out std_logic;
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ADD : out std_logic;
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MACMUX_sel : out std_logic;
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MACMUX2_sel : out std_logic
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);
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end component;
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component MAC_MUX is
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generic(
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Input_SZ_A : integer := 16;
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Input_SZ_B : integer := 16
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);
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port(
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sel : in std_logic;
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INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
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INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
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INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
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INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
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OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
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OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
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);
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end component;
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component MAC_MUX2 is
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generic(Input_SZ : integer := 16);
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port(
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sel : in std_logic;
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RES1 : in std_logic_vector(Input_SZ-1 downto 0);
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RES2 : in std_logic_vector(Input_SZ-1 downto 0);
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RES : out std_logic_vector(Input_SZ-1 downto 0)
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);
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end component;
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component MAC_REG is
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generic(size : integer := 16);
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port(
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reset : in std_logic;
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clk : in std_logic;
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D : in std_logic_vector(size-1 downto 0);
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Q : out std_logic_vector(size-1 downto 0)
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);
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end component;
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component MUX2 is
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generic(Input_SZ : integer := 16);
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port(
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sel : in std_logic;
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IN1 : in std_logic_vector(Input_SZ-1 downto 0);
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IN2 : in std_logic_vector(Input_SZ-1 downto 0);
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RES : out std_logic_vector(Input_SZ-1 downto 0)
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);
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end component;
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component Multiplier is
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generic(
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Input_SZ_A : integer := 16;
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Input_SZ_B : integer := 16
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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mult : in std_logic;
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OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
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OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
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RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
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);
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end component;
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component REG is
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generic(size : integer := 16 ; initial_VALUE : integer := 0);
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port(
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reset : in std_logic;
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clk : in std_logic;
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D : in std_logic_vector(size-1 downto 0);
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Q : out std_logic_vector(size-1 downto 0)
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);
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end component;
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component RShifter is
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generic(
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Input_SZ : integer := 16;
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shift_SZ : integer := 4
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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shift : in std_logic;
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OP : in std_logic_vector(Input_SZ-1 downto 0);
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cnt : in std_logic_vector(shift_SZ-1 downto 0);
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RES : out std_logic_vector(Input_SZ-1 downto 0)
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);
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end component;
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end;
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