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----------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2004 GAISLER RESEARCH
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- See the file COPYING for the full details of the license.
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--
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-----------------------------------------------------------------------------
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-- package: cancomp
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-- File: cancomp.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Opencores CAN core components
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package cancomp is
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component can_top
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port(
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rst : IN std_logic;
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addr : IN std_logic_vector(7 DOWNTO 0);
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data_in : IN std_logic_vector(7 DOWNTO 0);
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data_out : OUT std_logic_vector(7 DOWNTO 0);
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cs : IN std_logic;
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we : IN std_logic;
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clk_i : in std_logic;
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rx_i : in std_logic;
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tx_o : out std_logic;
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bus_off_on : out std_logic;
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irq_on : out std_logic;
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clkout_o : out std_logic;
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q_dp_64x8 : in std_logic_vector(7 downto 0);
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data_64x8 : out std_logic_vector(7 downto 0);
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wren_64x8 : out std_logic;
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rden_64x8 : out std_logic;
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wraddress_64x8 : out std_logic_vector(5 downto 0);
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rdaddress_64x8 : out std_logic_vector(5 downto 0);
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q_dp_64x4 : in std_logic_vector(3 downto 0);
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data_64x4 : out std_logic_vector(3 downto 0);
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wren_64x4x1 : out std_logic;
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wraddress_64x4x1: out std_logic_vector(5 downto 0);
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rdaddress_64x4x1: out std_logic_vector(5 downto 0);
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q_dp_64x1 : in std_logic;
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data_64x1 : out std_logic
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);
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end component;
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component can_top_sync
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port(
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rst : IN std_logic;
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addr : IN std_logic_vector(7 DOWNTO 0);
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data_in : IN std_logic_vector(7 DOWNTO 0);
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data_out : OUT std_logic_vector(7 DOWNTO 0);
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cs : IN std_logic;
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we : IN std_logic;
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clk_i : in std_logic;
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rx_i : in std_logic;
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tx_o : out std_logic;
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bus_off_on : out std_logic;
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irq_on : out std_logic;
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clkout_o : out std_logic;
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q_dp_64x8 : in std_logic_vector(7 downto 0);
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data_64x8 : out std_logic_vector(7 downto 0);
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wren_64x8 : out std_logic;
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rden_64x8 : out std_logic;
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wraddress_64x8 : out std_logic_vector(5 downto 0);
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rdaddress_64x8 : out std_logic_vector(5 downto 0);
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q_dp_64x4 : in std_logic_vector(3 downto 0);
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data_64x4 : out std_logic_vector(3 downto 0);
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wren_64x4x1 : out std_logic;
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wraddress_64x4x1: out std_logic_vector(5 downto 0);
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rdaddress_64x4x1: out std_logic_vector(5 downto 0);
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q_dp_64x1 : in std_logic;
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data_64x1 : out std_logic
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);
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end component;
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end;
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