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-- TOP_GSE.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library lpp;
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use lpp.lpp_usb.all;
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use lpp.Rocket_PCM_Encoder.all;
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use lpp.iir_filter.all;
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use lpp.general_purpose.all;
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library techmap;
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use techmap.gencomp.all;
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use work.config.all;
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entity TOP_EGSE2 is
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generic(WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64;Simu : integer :=0);
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port(
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Clock : in std_logic;
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reset : in std_logic;
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DataRTX : in std_logic;
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DataRTX_echo : out std_logic;
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SCLK : out std_logic;
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Gate : out std_logic;
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Major_Frame : out std_logic;
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Minor_Frame : out std_logic;
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if_clk : out STD_LOGIC;
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flagb : in STD_LOGIC;
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slwr : out STD_LOGIC;
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slrd : out std_logic;
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pktend : out STD_LOGIC;
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sloe : out STD_LOGIC;
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fdbusw : out std_logic_vector (7 downto 0);
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fifoadr : out std_logic_vector (1 downto 0);
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BUS0 : out std_logic;
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BUS12 : out std_logic;
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BUS13 : out std_logic;
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BUS14 : out std_logic
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);
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end TOP_EGSE2;
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architecture ar_TOP_EGSE2 of TOP_EGSE2 is
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component CLKINT
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port( A : in std_logic := 'U';
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Y : out std_logic
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);
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end component;
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signal clk : std_logic;
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signal clk_48 : std_logic;
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signal sclkint : std_logic;
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signal RaZ : std_logic;
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signal rstn : std_logic;
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signal WordCount : integer range 0 to WordCnt-1;
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signal WordClk : std_logic;
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signal MinFCnt : integer range 0 to MinFCount-1;
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signal MinF : std_logic;
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signal MinFclk : std_logic;
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signal MajF : std_logic;
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signal GateLF : std_logic;
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signal GateHF : std_logic;
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signal GateDC : std_logic;
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signal GateR : std_logic;
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signal Gateint : std_logic;
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signal NwDat : std_logic;
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signal NwDatR : std_logic;
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signal DATA : std_logic_vector(WordSize-1 downto 0);
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signal MinFVector : std_logic_vector(WordSize-1 downto 0);
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Signal PROTO_WEN : std_logic;
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Signal PROTO_DATAIN : std_logic_vector (WordSize-1 downto 0);
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Signal PROTO_FULL : std_logic;
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Signal PROTO_WR : std_logic;
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Signal PROTO_DATAOUT : std_logic_vector (WordSize-1 downto 0);
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Signal clk80 : std_logic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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begin
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DataRTX_echo <= DataRTX; --P48
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ck_int0 : CLKINT
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port map(Clock,clk_48);
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RaZ <= cgo.clklock;
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CLKGEN : entity clkgen
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generic map(
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tech => CFG_CLKTECH,
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clk_mul => CFG_CLKMUL,
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clk_div => CFG_CLKDIV,
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freq => BOARDFREQ, -- clock frequency in KHz
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clk_odiv => CFG_OCLKDIV, -- Proasic3/Fusion output divider clkA
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clkb_odiv => CFG_OCLKDIV, -- Proasic3/Fusion output divider clkB
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clkc_odiv => CFG_OCLKDIV) -- Proasic3/Fusion output divider clkC
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port map(
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clkin => clk_48,
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pciclkin => '0',
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clk => clk, -- main clock
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clkn => open, -- inverted main clock
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clk2x => open, -- 2x clock
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sdclk => open, -- SDRAM clock
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pciclk => open, -- PCI clock
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cgi => cgi,
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cgo => cgo,
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clk4x => open, -- 4x clock
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clk1xu => open, -- unscaled 1X clock
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clk2xu => open, -- unscaled 2X clock
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clkb => clk80, -- Proasic3/Fusion clkB
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clkc => open); -- Proasic3/Fusion clkC
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gene3_3M : entity Clk_Divider2
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generic map(N => 10)
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port map(
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clk_in => clk,
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clk_out => sclkint
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);
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Wcounter : entity Word_Cntr
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generic map(WordSize => WordSize ,N => WordCnt)
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port map(
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Sclk => Sclkint,
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reset => rstn,
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WordClk => WordClk,
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Cnt_out => WordCount
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);
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MFGEN0 : entity work.MinF_Gen
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generic map(WordCnt => WordCnt)
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port map(
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clk => Sclkint,
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reset => rstn,
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WordCnt_in => WordCount,
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WordClk => WordClk,
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MinF_Clk => MinF
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);
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MinFcounter : entity Word_Cntr
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generic map(WordSize => WordCnt ,N => MinFCount)
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port map(
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Sclk => WordClk,
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reset => rstn,
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WordClk => MinFclk,
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Cnt_out => MinFCnt
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);
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MFGEN1 : entity work.MajF_Gen
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generic map(WordCnt => WordCnt,MinFCount => MinFCount)
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port map(
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clk => Sclkint,
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reset => rstn,
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WordCnt_in => WordCount,
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MinfCnt_in => MinFCnt,
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WordClk => WordClk,
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MajF_Clk => MajF
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);
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LFGATEGEN0 : entity work.LF_GATE_GEN
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generic map(WordCnt => WordCnt)
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port map(
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clk => Sclkint,
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Wcount => WordCount,
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Gate => GateLF
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);
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DCGATEGEN0 : entity work.DC_GATE_GEN
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generic map(WordCnt => WordCnt)
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port map(
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clk => Sclkint,
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Wcount => WordCount,
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Gate => GateDC
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);
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--GateDC <= '0';
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--GateLF <= '0';
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HFGATEGEN0 :
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GateHF <= '1' when WordCount = 120 else
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'1' when WordCount = 121 else '0';
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SD0 : entity Serial_driver2
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generic map(Sz => WordSize)
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port map(
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Sclk => Sclkint,
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rstn => rstn,
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Sdata => DataRTX,
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Gate => GateR,
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NwDat => NwDat,
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Data => DATA
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);
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proto: entity work.ICI_EGSE_PROTOCOL
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generic map(WordSize => WordSize,WordCnt => WordCnt,MinFCount => MinFCount,Simu => 0)
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port map(
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clk => clk,
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-- reset => not MinF,
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reset => rstn,
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WEN => PROTO_WEN,
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MinfCnt_in => MinfCnt,
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WordCnt_in => WordCount,
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DATAIN => PROTO_DATAIN,
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FULL => PROTO_FULL,
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WR => PROTO_WR,
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DATAOUT => PROTO_DATAOUT
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);
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USB2: entity work.FX2_WithFIFO
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generic map(CFG_MEMTECH,use_RAM)
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port map(
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clk => clk,
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if_clk => if_clk,
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reset => rstn,
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flagb => flagb,
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slwr => slwr,
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slrd => slrd,
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pktend => pktend,
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sloe => sloe,
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fdbusw => fdbusw,
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fifoadr => fifoadr,
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FULL => PROTO_FULL,
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wen => PROTO_WR,
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Data => PROTO_DATAOUT
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);
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rstn <= reset and RaZ;
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SCLK <= Sclkint;
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Major_Frame <= MajF;
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Minor_Frame <= MinF;
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--Minor_Frame <= MinFclk;
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gateint <= GateDC or GateLF or GateHF;
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Gate <= gateint;
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process(Sclkint,rstn)
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begin
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if rstn = '0' then
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GateR <= '0';
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elsif Sclkint'event and Sclkint = '0' then
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GateR <= Gateint;
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end if;
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end process;
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BUS0 <= WordClk;
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BUS12 <= MinFVector(0);
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--BUS13 <= MinFclk;
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--BUS14 <= '1' when WordCount = 0 else '0';
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BUS13 <= MinF;
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BUS14 <= MajF;
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MinFVector <= std_logic_vector(TO_UNSIGNED(MinfCnt,WordSize));
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process(clk,rstn)
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begin
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if rstn = '0' then
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PROTO_DATAIN <= (others => '0');
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PROTO_WEN <= '1';
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elsif clk'event and clk = '1' then
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NwDatR <= NwDat;
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if NwDat = '1' and NwDatR = '0' then
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-- PROTO_DATAIN <= std_logic_vector(unsigned(PROTO_DATAIN) + 1 );
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PROTO_DATAIN <= DATA;
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PROTO_WEN <= '0';
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else
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PROTO_WEN <= '1';
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end if;
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end if;
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end process;
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end ar_TOP_EGSE2;
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