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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY std;
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USE std.textio.ALL;
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LIBRARY lpp;
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USE lpp.cic_pkg.ALL;
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USE lpp.chirp_pkg.ALL;
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USE lpp.lpp_fft.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.iir_filter.ALL;
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ENTITY testbench IS
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GENERIC (
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input_file_name_f0 : STRING := "input_data_f0.txt";
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input_file_name_f1 : STRING := "input_data_f1.txt";
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input_file_name_f2 : STRING := "input_data_f2.txt";
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output_file_name_f0 : STRING := "output_data_f0.txt";
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output_file_name_f1 : STRING := "output_data_f1.txt";
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output_file_name_f2 : STRING := "output_data_f2.txt");
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END;
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ARCHITECTURE behav OF testbench IS
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COMPONENT data_read_with_timer
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GENERIC (
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input_file_name : STRING;
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NB_CHAR_PER_DATA : INTEGER;
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NB_CYCLE_TIMER : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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end_of_file : OUT STD_LOGIC;
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data_out_val : OUT STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0));
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END COMPONENT;
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COMPONENT data_write_with_burstCounter
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GENERIC (
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OUTPUT_FILE_NAME : STRING;
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NB_CHAR_PER_DATA : INTEGER;
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BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0));
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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burst_valid : IN STD_LOGIC;
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burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_ren : OUT STD_LOGIC;
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data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
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close_file : IN STD_LOGIC);
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END COMPONENT;
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL rstn : STD_LOGIC;
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SIGNAL start : STD_LOGIC;
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-- IN
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SIGNAL sample_valid : STD_LOGIC;
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SIGNAL fft_read : STD_LOGIC;
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SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL sample_load : STD_LOGIC;
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-- OUT
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SIGNAL fft_pong : STD_LOGIC;
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SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL fft_data_valid : STD_LOGIC;
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SIGNAL fft_ready : STD_LOGIC;
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SIGNAL fft_component_number : INTEGER;
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SIGNAL end_of_sim : STD_LOGIC := '0';
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-----------------------------------------------------------------------------
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-- DATA GEN
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-----------------------------------------------------------------------------
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CONSTANT NB_CYCLE_f0 : INTEGER := 1017; -- 25MHz / 24576Hz
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CONSTANT NB_CYCLE_f1 : INTEGER := 6103; -- 25MHz / 4096Hz
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CONSTANT NB_CYCLE_f2 : INTEGER := 97656; -- 25MHz / 256Hz
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SIGNAL data_counter_f0 : INTEGER;
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SIGNAL data_counter_f1 : INTEGER;
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SIGNAL data_counter_f2 : INTEGER;
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SIGNAL sample_f0_wen : STD_LOGIC;
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SIGNAL sample_f1_wen : STD_LOGIC;
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SIGNAL sample_f2_wen : STD_LOGIC;
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SIGNAL sample_f0_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f1_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f2_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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-----------------------------------------------------------------------------
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-- TIME
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-----------------------------------------------------------------------------
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SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
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SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL time_counter : INTEGER;
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SIGNAL new_fine_time : STD_LOGIC := '0';
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SIGNAL new_fine_time_reg : STD_LOGIC := '0';
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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SIGNAL end_of_file : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL data_out_val : STD_LOGIC_VECTOR(2 DOWNTO 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL dma_fifo_burst_valid : STD_LOGIC; --TODO
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SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
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SIGNAL dma_fifo_ren : STD_LOGIC; --TODO
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SIGNAL dma_fifo_ren_f0 : STD_LOGIC; --TODO
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SIGNAL dma_fifo_ren_f1 : STD_LOGIC; --TODO
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SIGNAL dma_fifo_ren_f2 : STD_LOGIC; --TODO
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SIGNAL dma_buffer_new : STD_LOGIC; --TODOx
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SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
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SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
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SIGNAL dma_buffer_full : STD_LOGIC; --TODO
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SIGNAL dma_buffer_full_err : STD_LOGIC; --TODO
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SIGNAL ready_matrix_f0 : STD_LOGIC; -- TODO
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SIGNAL ready_matrix_f1 : STD_LOGIC; -- TODO
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SIGNAL ready_matrix_f2 : STD_LOGIC; -- TODO
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SIGNAL status_ready_matrix_f0 : STD_LOGIC; -- TODO
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SIGNAL status_ready_matrix_f1 : STD_LOGIC; -- TODO
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SIGNAL status_ready_matrix_f2 : STD_LOGIC; -- TODO
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SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
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SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
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SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
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SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
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SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
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SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
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SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
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SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
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SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
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-----------------------------------------------------------------------------
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SIGNAL dma_ren_counter : INTEGER;
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SIGNAL dma_output_counter : INTEGER;
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-----------------------------------------------------------------------------
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CONSTANT BASE_ADDR_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"01000000";
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CONSTANT BASE_ADDR_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"10000000";
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CONSTANT BASE_ADDR_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"11000000";
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-----------------------------------------------------------------------------
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SIGNAL close_file : STD_LOGIC := '0';
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BEGIN
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-----------------------------------------------------------------------------
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clk <= NOT clk AFTER 20 ns;
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new_fine_time <= NOT new_fine_time AFTER 15258 ns;
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PROCESS
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BEGIN -- PROCESS
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WAIT UNTIL clk = '1';
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close_file <= '0';
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rstn <= '0';
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start <= '0';
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WAIT UNTIL clk = '1';
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rstn <= '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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start <= '1';
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WHILE NOT (end_of_file = "111") LOOP
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WAIT UNTIL clk = '1';
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END LOOP;
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REPORT "*** END READ FILE ***";-- SEVERITY failure;
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WAIT FOR 3 ms;
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close_file <= '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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end_of_sim <= '1';
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WAIT FOR 100 ns;
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REPORT "*** END SIMULATION ***" SEVERITY failure;
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WAIT;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- TIME
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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start_date <= X"0000000" & "001";
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coarse_time <= (OTHERS => '0');
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fine_time <= (OTHERS => '0');
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time_counter <= 0;
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new_fine_time_reg <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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new_fine_time_reg <= new_fine_time;
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IF start = '1' THEN
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IF coarse_time(30 downto 0) = X"0000000" & "000" THEN
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coarse_time(30 downto 0) <= start_date;
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ELSE
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IF new_fine_time = NOT new_fine_time_reg THEN
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IF fine_time = X"FFFF" THEN
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coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(coarse_time) + 1);
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fine_time <= (OTHERS => '0');
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ELSE
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fine_time <= STD_LOGIC_VECTOR(UNSIGNED(fine_time) + 1);
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- DATA IN
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-----------------------------------------------------------------------------
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data_read_with_timer_f0 : data_read_with_timer
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GENERIC MAP (input_file_name_f0, 4*5, NB_CYCLE_f0)
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PORT MAP (clk, rstn, end_of_file(0), data_out_val(0), sample_f0_wdata(16*5-1 downto 0));
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sample_f0_wen <= NOT data_out_val(0);
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data_read_with_timer_f1 : data_read_with_timer
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GENERIC MAP (input_file_name_f1, 4*5, NB_CYCLE_f1)
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PORT MAP (clk, rstn, end_of_file(1), data_out_val(1), sample_f1_wdata(16*5-1 downto 0));
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sample_f1_wen <= NOT data_out_val(1);
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data_read_with_timer_f2 : data_read_with_timer
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GENERIC MAP (input_file_name_f2, 4*5, NB_CYCLE_f2)
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PORT MAP (clk, rstn, end_of_file(2), data_out_val(2), sample_f2_wdata(16*5-1 downto 0));
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sample_f2_wen <= NOT data_out_val(2);
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-----------------------------------------------------------------------------
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-- DATA OUT
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-----------------------------------------------------------------------------
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--dma_fifo_burst_valid -- in
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--dma_fifo_data -- in
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--dma_fifo_ren -- OUT
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--dma_fifo_ren <= '0';
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--PROCESS (clk, rstn)
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--BEGIN -- PROCESS
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-- IF rstn = '0' THEN -- asynchronous reset (active low)
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-- dma_ren_counter <= 0;
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-- dma_fifo_ren <= '1';
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-- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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-- dma_fifo_ren <= '1';
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-- IF dma_ren_counter = 0 AND dma_fifo_burst_valid = '1' THEN
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-- dma_ren_counter <= 16;
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-- END IF;
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-- IF dma_ren_counter > 0 THEN
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-- dma_ren_counter <= dma_ren_counter - 1;
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-- dma_fifo_ren <= '0';
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-- END IF;
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-- END IF;
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--END PROCESS;
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data_write_with_burstCounter_0: data_write_with_burstCounter
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GENERIC MAP (
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OUTPUT_FILE_NAME => output_file_name_f0,
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NB_CHAR_PER_DATA => 32/4,
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BASE_ADDR => BASE_ADDR_F0)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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burst_addr => dma_buffer_addr,
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burst_valid => dma_fifo_burst_valid,
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data_ren => dma_fifo_ren_f0,
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data => dma_fifo_data,
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close_file => close_file);
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data_write_with_burstCounter_1: data_write_with_burstCounter
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GENERIC MAP (
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OUTPUT_FILE_NAME => output_file_name_f1,
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NB_CHAR_PER_DATA => 32/4,
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BASE_ADDR => BASE_ADDR_F1)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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burst_addr => dma_buffer_addr,
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burst_valid => dma_fifo_burst_valid,
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data_ren => dma_fifo_ren_f1,
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data => dma_fifo_data,
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close_file => close_file);
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data_write_with_burstCounter_2: data_write_with_burstCounter
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GENERIC MAP (
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OUTPUT_FILE_NAME => output_file_name_f2,
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NB_CHAR_PER_DATA => 32/4,
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BASE_ADDR => BASE_ADDR_F2)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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burst_addr => dma_buffer_addr,
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burst_valid => dma_fifo_burst_valid,
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data_ren => dma_fifo_ren_f2,
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data => dma_fifo_data,
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close_file => close_file);
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dma_fifo_ren <= dma_fifo_ren_f0 AND dma_fifo_ren_f1 AND dma_fifo_ren_f2;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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dma_buffer_full <= '0';
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dma_buffer_full_err <= '0';
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dma_output_counter <= 0;
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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dma_buffer_full <= '0';
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IF dma_buffer_new = '1' THEN
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dma_output_counter <= to_integer(UNSIGNED(dma_buffer_length));
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END IF;
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IF dma_fifo_ren = '0' THEN
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IF dma_output_counter = 1 THEN
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dma_buffer_full <= '1';
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dma_output_counter <= 0;
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ELSE
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dma_output_counter <= dma_output_counter - 1;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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--dma_buffer_new -- in
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--dma_buffer_addr -- in
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--dma_buffer_length -- in
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--dma_buffer_full -- out
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--dma_buffer_full_err -- OUT
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-- dma_buffer_full <= '0';
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-- dma_buffer_full_err <= '0';
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-----------------------------------------------------------------------------
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-- BUFFER CONFIGURATION and INFORMATION
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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status_ready_matrix_f0 <= '0';
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status_ready_matrix_f1 <= '0';
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status_ready_matrix_f2 <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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status_ready_matrix_f0 <= ready_matrix_f0;
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status_ready_matrix_f1 <= ready_matrix_f1;
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status_ready_matrix_f2 <= ready_matrix_f2;
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END IF;
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END PROCESS;
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addr_matrix_f0 <= BASE_ADDR_F0;
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addr_matrix_f1 <= BASE_ADDR_F1;
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addr_matrix_f2 <= BASE_ADDR_F2;
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length_matrix_f0 <= "00" & X"000C80";
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length_matrix_f1 <= "00" & X"000C80";
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length_matrix_f2 <= "00" & X"000C80";
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sample_f0_wen_v <= sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen;
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sample_f1_wen_v <= sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen;
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sample_f2_wen_v <= sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen;
|
|
|
|
|
|
sample_f0_time <= coarse_time & fine_time;
|
|
|
sample_f1_time <= coarse_time & fine_time;
|
|
|
sample_f2_time <= coarse_time & fine_time;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- DUT
|
|
|
-----------------------------------------------------------------------------
|
|
|
lpp_lfr_ms_1 : lpp_lfr_ms
|
|
|
GENERIC MAP (
|
|
|
Mem_use => use_RAM)
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
run => '1',
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- TIME
|
|
|
-----------------------------------------------------------------------------
|
|
|
start_date => start_date,
|
|
|
coarse_time => coarse_time,
|
|
|
-- fine_time => fine_time,
|
|
|
|
|
|
-------------------------------------------------------------------------
|
|
|
-- DATA IN
|
|
|
-------------------------------------------------------------------------
|
|
|
sample_f0_wen => sample_f0_wen_v, --
|
|
|
sample_f0_wdata => sample_f0_wdata,
|
|
|
sample_f0_time => sample_f0_time,
|
|
|
sample_f1_wen => sample_f1_wen_v,
|
|
|
sample_f1_wdata => sample_f1_wdata,
|
|
|
sample_f1_time => sample_f1_time,
|
|
|
sample_f2_wen => sample_f2_wen_v,
|
|
|
sample_f2_wdata => sample_f2_wdata,
|
|
|
sample_f2_time => sample_f2_time,
|
|
|
|
|
|
-------------------------------------------------------------------------
|
|
|
-- DMA OUT
|
|
|
-------------------------------------------------------------------------
|
|
|
dma_fifo_burst_valid => dma_fifo_burst_valid, --out
|
|
|
dma_fifo_data => dma_fifo_data, --out
|
|
|
dma_fifo_ren => dma_fifo_ren, --in
|
|
|
dma_buffer_new => dma_buffer_new, --out
|
|
|
dma_buffer_addr => dma_buffer_addr, --out
|
|
|
dma_buffer_length => dma_buffer_length, --out
|
|
|
dma_buffer_full => dma_buffer_full, --in
|
|
|
dma_buffer_full_err => dma_buffer_full_err, --in
|
|
|
|
|
|
-------------------------------------------------------------------------
|
|
|
-- BUFFER CONFIGURATION and INFORMATION
|
|
|
-------------------------------------------------------------------------
|
|
|
ready_matrix_f0 => ready_matrix_f0, --out
|
|
|
ready_matrix_f1 => ready_matrix_f1, --out
|
|
|
ready_matrix_f2 => ready_matrix_f2, --out
|
|
|
|
|
|
error_buffer_full => OPEN,
|
|
|
error_input_fifo_write => OPEN,
|
|
|
|
|
|
status_ready_matrix_f0 => status_ready_matrix_f0, --in
|
|
|
status_ready_matrix_f1 => status_ready_matrix_f1, --in
|
|
|
status_ready_matrix_f2 => status_ready_matrix_f2, --in
|
|
|
|
|
|
addr_matrix_f0 => addr_matrix_f0, --in
|
|
|
addr_matrix_f1 => addr_matrix_f1, --in
|
|
|
addr_matrix_f2 => addr_matrix_f2, --in
|
|
|
|
|
|
length_matrix_f0 => length_matrix_f0, --in
|
|
|
length_matrix_f1 => length_matrix_f1, --in
|
|
|
length_matrix_f2 => length_matrix_f2, --in
|
|
|
|
|
|
matrix_time_f0 => matrix_time_f0, --out
|
|
|
matrix_time_f1 => matrix_time_f1, --out
|
|
|
matrix_time_f2 => matrix_time_f2, --out
|
|
|
|
|
|
debug_vector => OPEN);
|
|
|
|
|
|
END;
|
|
|
|
