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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity HeaderBuilder is
27 generic(
28 Data_sz : integer := 32);
29 port(
30 clkm : in std_logic;
31 rstn : in std_logic;
32
33 pong : in std_logic;
34 Statu : in std_logic_vector(3 downto 0);
35 Matrix_Type : in std_logic_vector(1 downto 0);
36 Matrix_Write : in std_logic;
37 Valid : out std_logic;
38
39 dataIN : in std_logic_vector((2*Data_sz)-1 downto 0);
40 emptyIN : in std_logic_vector(1 downto 0);
41 RenOUT : out std_logic_vector(1 downto 0);
42
43 dataOUT : out std_logic_vector(Data_sz-1 downto 0);
44 emptyOUT : out std_logic;
45 RenIN : in std_logic;
46
47 header : out std_logic_vector(Data_sz-1 DOWNTO 0);
48 header_val : out std_logic;
49 header_ack : in std_logic
50 );
51 end entity;
52
53
54 architecture ar_HeaderBuilder of HeaderBuilder is
55
56 signal Matrix_Param : std_logic_vector(3 downto 0);
57 signal Write_reg : std_logic;
58 signal Data_cpt : integer;
59 signal MAX : integer;
60
61
62 begin
63
64 process (clkm,rstn)
65 begin
66 if(rstn='0')then
67 Valid <= '0';
68 Write_reg <= '0';
69 Data_cpt <= 0;
70 MAX <= 0;
71
72
73 elsif(clkm' event and clkm='1')then
74 Write_reg <= Matrix_Write;
75
76 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
77 MAX <= 128;
78 else
79 MAX <= 256;
80 end if;
81
82 if(Write_reg = '0' and Matrix_Write = '1')then
83 if(Data_cpt = MAX)then
84 Data_cpt <= 0;
85 Valid <= '1';
86 header_val <= '1';
87 else
88 Data_cpt <= Data_cpt + 1;
89 Valid <= '0';
90 end if;
91 end if;
92
93 if(header_ack = '1')then
94 header_val <= '0';
95 end if;
96
97 end if;
98 end process;
99
100 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
101
102 header(1 downto 0) <= Matrix_Type;
103 header(5 downto 2) <= Matrix_Param;
104
105 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
106 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
107
108 RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1';
109
110 end architecture; No newline at end of file
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@@ -0,0 +1,61
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
32 package lpp_Header is
33
34 component HeaderBuilder is
35 generic(
36 Data_sz : integer := 32);
37 port(
38 clkm : in std_logic;
39 rstn : in std_logic;
40
41 pong : in std_logic;
42 Statu : in std_logic_vector(3 downto 0);
43 Matrix_Type : in std_logic_vector(1 downto 0);
44 Matrix_Write : in std_logic;
45 Valid : out std_logic;
46
47 dataIN : in std_logic_vector((2*Data_sz)-1 downto 0);
48 emptyIN : in std_logic_vector(1 downto 0);
49 RenOUT : out std_logic_vector(1 downto 0);
50
51 dataOUT : out std_logic_vector(Data_sz-1 downto 0);
52 emptyOUT : out std_logic;
53 RenIN : in std_logic;
54
55 header : out std_logic_vector(Data_sz-1 DOWNTO 0);
56 header_val : out std_logic;
57 header_ack : in std_logic
58 );
59 end component;
60
61 end; No newline at end of file
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@@ -194,6 +194,8 signal SM_FlagError : std_logic;
194 194 signal SM_Pong : std_logic;
195 195 signal SM_Read : std_logic_vector(4 downto 0);
196 196 signal SM_Write : std_logic_vector(1 downto 0);
197 signal SM_ReUse : std_logic_vector(4 downto 0);
198 signal SM_Param : std_logic_vector(3 downto 0);
197 199 signal SM_Data : std_logic_vector(63 downto 0);
198 200
199 201 signal Dma_acq : std_logic;
@@ -211,7 +213,6 signal DEMU_Empty : std_logic_vector(4
211 213 signal DEMU_Data : std_logic_vector(79 downto 0);
212 214
213 215 -- ACQ
214
215 216 signal sample_val : STD_LOGIC;
216 217 signal sample : Samples(8-1 DOWNTO 0);
217 218
@@ -315,30 +316,29 led(1 downto 0) <= gpio(1 downto 0);
315 316 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
316 317 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
317 318
318 DIGITAL_acquisition : ADS7886_drvr
319 GENERIC MAP (
320 ChanelCount => 8,
321 ncycle_cnv_high => 79,
322 ncycle_cnv => 500)
323 PORT MAP (
324 cnv_clk => clk50MHz, --
325 cnv_rstn => rstn, --
326 cnv_run => '1', --
327 cnv => CNV_CH1, --
328 clk => clkm, --
329 rstn => rstn, --
330 sck => SCK_CH1, --
331 sdo => SDO_CH1, --
332 sample => sample,
333 sample_val => sample_val);
319 -- DIGITAL_acquisition : ADS7886_drvr
320 -- GENERIC MAP (
321 -- ChanelCount => 8,
322 -- ncycle_cnv_high => 79,
323 -- ncycle_cnv => 500)
324 -- PORT MAP (
325 -- cnv_clk => clk50MHz, --
326 -- cnv_rstn => rstn, --
327 -- cnv_run => '1', --
328 -- cnv => CNV_CH1, --
329 -- clk => clkm, --
330 -- rstn => rstn, --
331 -- sck => SCK_CH1, --
332 -- sdo => SDO_CH1, --
333 -- sample => sample,
334 -- sample_val => sample_val);
334 335 --
335 TopACQ_WenF0 <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
336 TopACQ_DataF0 <= sample(4) & sample(3) & sample(2) & sample(1) & sample(0);
336 --TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val;
337 --TopACQ_DataF0 <= E & D & C & B & A;
338
337 339 --
338 TEST(0) <= TopACQ_WenF0(1);
339 TEST(1) <= SDO_CH1(1);
340 --
341 --
340 --TEST(0) <= TopACQ_WenF0(1);
341 --TEST(1) <= SDO_CH1(1);
342 342 --
343 343 --process(clkm,rstn)
344 344 --begin
@@ -351,18 +351,18 TEST(1) <= SDO_CH1(1);
351 351 -- end if;
352 352 --end process;
353 353
354 -- TopACQ : lpp_top_acq
355 -- port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
354 TopACQ : lpp_top_acq
355 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
356 356
357 357 Bias_Fails <= '0';
358 358 --- FIFO IN -------------------------------------------------------------
359 359
360 MemOut : APB_FIFO
361 generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0)
362 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9));
363 -- Memf0 : lppFIFOxN
364 -- generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
365 -- port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
360 -- MemOut : APB_FIFO
361 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0)
362 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9));
363 Memf0 : lppFIFOxN
364 generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
365 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
366 366
367 367 Memf1 : lppFIFOxN
368 368 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
@@ -396,7 +396,7 Bias_Fails <= '0';
396 396
397 397 MemInt : lppFIFOxN
398 398 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
399 port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
399 port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
400 400 --
401 401 -- MemIn : APB_FIFO
402 402 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
@@ -406,13 +406,13 Bias_Fails <= '0';
406 406
407 407 SM0 : MatriceSpectrale
408 408 generic map(Input_SZ => 16,Result_SZ => 32)
409 port map(clkm,rstn,FifoINT_Full,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Write,SM_Read,SM_Data);
409 port map(clkm,rstn,FifoINT_Full,FFT_ReUse,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data);
410 410
411 411 Dma_acq <= '1';
412 412
413 -- MemOut : APB_FIFO
414 -- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
415 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
413 MemOut : APB_FIFO
414 generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
415 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
416 416
417 417 ----- FIFO -------------------------------------------------------------
418 418
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@@ -41,6 +41,7 port(
41 41 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
42 42 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
43 43
44 WorkFreq : out std_logic_vector(1 downto 0);
44 45 Read_DEMUX : out std_logic_vector(14 downto 0);
45 46 Empty : out std_logic_vector(4 downto 0);
46 47 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
@@ -59,6 +60,7 constant Dummy_Read : std_logic_vector(4
59 60
60 61 signal Countf0 : integer;
61 62 signal Countf1 : integer;
63 signal i : integer;
62 64
63 65 begin
64 66 process(clk,rstn)
@@ -66,8 +68,9 begin
66 68 if(rstn='0')then
67 69 ect <= e0;
68 70 load_reg <= '0';
69 Countf0 <= 5;
71 Countf0 <= 0;
70 72 Countf1 <= 0;
73 i <= 0;
71 74
72 75 elsif(clk'event and clk='1')then
73 76 load_reg <= Load;
@@ -92,13 +95,25 begin
92 95 ect <= e2;
93 96 else
94 97 Countf1 <= Countf1 + 1;
98 if(i=4)then
99 i <= 0;
95 100 ect <= e0;
101 else
102 i <= i+1;
103 ect <= e1;
104 end if;
96 105 end if;
97 106 end if;
98 107
99 108 when e2 =>
100 109 if(load_reg = '1' and Load = '0')then
110 if(i=4)then
111 i <= 0;
101 112 ect <= e0;
113 else
114 i <= i+1;
115 ect <= e2;
116 end if;
102 117 end if;
103 118
104 119 when others =>
@@ -126,6 +141,12 with ect select
126 141 Read & Dummy_Read & Dummy_Read when e2,
127 142 (others => '1') when others;
128 143
144 with ect select
145 WorkFreq <= "01" when e0,
146 "10" when e1,
147 "11" when e2,
148 "00" when others;
149
129 150 end architecture;
130 151
131 152
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@@ -49,6 +49,7 port(
49 49 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
50 50 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
51 51
52 WorkFreq : out std_logic_vector(1 downto 0);
52 53 Read_DEMUX : out std_logic_vector(14 downto 0);
53 54 Empty : out std_logic_vector(4 downto 0);
54 55 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
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