@@ -0,0 +1,110 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------ | |
|
19 | -- Author : Martin Morlot | |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------ | |
|
22 | library IEEE; | |
|
23 | use IEEE.std_logic_1164.all; | |
|
24 | use IEEE.numeric_std.all; | |
|
25 | ||
|
26 | entity HeaderBuilder is | |
|
27 | generic( | |
|
28 | Data_sz : integer := 32); | |
|
29 | port( | |
|
30 | clkm : in std_logic; | |
|
31 | rstn : in std_logic; | |
|
32 | ||
|
33 | pong : in std_logic; | |
|
34 | Statu : in std_logic_vector(3 downto 0); | |
|
35 | Matrix_Type : in std_logic_vector(1 downto 0); | |
|
36 | Matrix_Write : in std_logic; | |
|
37 | Valid : out std_logic; | |
|
38 | ||
|
39 | dataIN : in std_logic_vector((2*Data_sz)-1 downto 0); | |
|
40 | emptyIN : in std_logic_vector(1 downto 0); | |
|
41 | RenOUT : out std_logic_vector(1 downto 0); | |
|
42 | ||
|
43 | dataOUT : out std_logic_vector(Data_sz-1 downto 0); | |
|
44 | emptyOUT : out std_logic; | |
|
45 | RenIN : in std_logic; | |
|
46 | ||
|
47 | header : out std_logic_vector(Data_sz-1 DOWNTO 0); | |
|
48 | header_val : out std_logic; | |
|
49 | header_ack : in std_logic | |
|
50 | ); | |
|
51 | end entity; | |
|
52 | ||
|
53 | ||
|
54 | architecture ar_HeaderBuilder of HeaderBuilder is | |
|
55 | ||
|
56 | signal Matrix_Param : std_logic_vector(3 downto 0); | |
|
57 | signal Write_reg : std_logic; | |
|
58 | signal Data_cpt : integer; | |
|
59 | signal MAX : integer; | |
|
60 | ||
|
61 | ||
|
62 | begin | |
|
63 | ||
|
64 | process (clkm,rstn) | |
|
65 | begin | |
|
66 | if(rstn='0')then | |
|
67 | Valid <= '0'; | |
|
68 | Write_reg <= '0'; | |
|
69 | Data_cpt <= 0; | |
|
70 | MAX <= 0; | |
|
71 | ||
|
72 | ||
|
73 | elsif(clkm' event and clkm='1')then | |
|
74 | Write_reg <= Matrix_Write; | |
|
75 | ||
|
76 | if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then | |
|
77 | MAX <= 128; | |
|
78 | else | |
|
79 | MAX <= 256; | |
|
80 | end if; | |
|
81 | ||
|
82 | if(Write_reg = '0' and Matrix_Write = '1')then | |
|
83 | if(Data_cpt = MAX)then | |
|
84 | Data_cpt <= 0; | |
|
85 | Valid <= '1'; | |
|
86 | header_val <= '1'; | |
|
87 | else | |
|
88 | Data_cpt <= Data_cpt + 1; | |
|
89 | Valid <= '0'; | |
|
90 | end if; | |
|
91 | end if; | |
|
92 | ||
|
93 | if(header_ack = '1')then | |
|
94 | header_val <= '0'; | |
|
95 | end if; | |
|
96 | ||
|
97 | end if; | |
|
98 | end process; | |
|
99 | ||
|
100 | Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4)); | |
|
101 | ||
|
102 | header(1 downto 0) <= Matrix_Type; | |
|
103 | header(5 downto 2) <= Matrix_Param; | |
|
104 | ||
|
105 | dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz); | |
|
106 | emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1); | |
|
107 | ||
|
108 | RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1'; | |
|
109 | ||
|
110 | end architecture; No newline at end of file |
@@ -0,0 +1,61 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------ | |
|
19 | -- Author : Martin Morlot | |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------ | |
|
22 | library ieee; | |
|
23 | use ieee.std_logic_1164.all; | |
|
24 | library grlib; | |
|
25 | use grlib.amba.all; | |
|
26 | use std.textio.all; | |
|
27 | library lpp; | |
|
28 | use lpp.lpp_amba.all; | |
|
29 | ||
|
30 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on | |
|
31 | ||
|
32 | package lpp_Header is | |
|
33 | ||
|
34 | component HeaderBuilder is | |
|
35 | generic( | |
|
36 | Data_sz : integer := 32); | |
|
37 | port( | |
|
38 | clkm : in std_logic; | |
|
39 | rstn : in std_logic; | |
|
40 | ||
|
41 | pong : in std_logic; | |
|
42 | Statu : in std_logic_vector(3 downto 0); | |
|
43 | Matrix_Type : in std_logic_vector(1 downto 0); | |
|
44 | Matrix_Write : in std_logic; | |
|
45 | Valid : out std_logic; | |
|
46 | ||
|
47 | dataIN : in std_logic_vector((2*Data_sz)-1 downto 0); | |
|
48 | emptyIN : in std_logic_vector(1 downto 0); | |
|
49 | RenOUT : out std_logic_vector(1 downto 0); | |
|
50 | ||
|
51 | dataOUT : out std_logic_vector(Data_sz-1 downto 0); | |
|
52 | emptyOUT : out std_logic; | |
|
53 | RenIN : in std_logic; | |
|
54 | ||
|
55 | header : out std_logic_vector(Data_sz-1 DOWNTO 0); | |
|
56 | header_val : out std_logic; | |
|
57 | header_ack : in std_logic | |
|
58 | ); | |
|
59 | end component; | |
|
60 | ||
|
61 | end; No newline at end of file |
@@ -1,651 +1,651 | |||
|
1 | 1 | ----------------------------------------------------------------------------- |
|
2 | 2 | -- LEON3 Demonstration design |
|
3 | 3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 2 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | |
|
20 | 20 | |
|
21 | 21 | library ieee; |
|
22 | 22 | use ieee.std_logic_1164.all; |
|
23 | 23 | library grlib; |
|
24 | 24 | use grlib.amba.all; |
|
25 | 25 | use grlib.stdlib.all; |
|
26 | 26 | library techmap; |
|
27 | 27 | use techmap.gencomp.all; |
|
28 | 28 | library gaisler; |
|
29 | 29 | use gaisler.memctrl.all; |
|
30 | 30 | use gaisler.leon3.all; |
|
31 | 31 | use gaisler.uart.all; |
|
32 | 32 | use gaisler.misc.all; |
|
33 | 33 | library esa; |
|
34 | 34 | use esa.memoryctrl.all; |
|
35 | 35 | use work.config.all; |
|
36 | 36 | library lpp; |
|
37 | 37 | use lpp.lpp_amba.all; |
|
38 | 38 | use lpp.lpp_memory.all; |
|
39 | 39 | use lpp.lpp_uart.all; |
|
40 | 40 | use lpp.lpp_matrix.all; |
|
41 | 41 | use lpp.lpp_delay.all; |
|
42 | 42 | use lpp.lpp_fft.all; |
|
43 | 43 | use lpp.fft_components.all; |
|
44 | 44 | use lpp.lpp_ad_conv.all; |
|
45 | 45 | use lpp.iir_filter.all; |
|
46 | 46 | use lpp.general_purpose.all; |
|
47 | 47 | use lpp.Filtercfg.all; |
|
48 | 48 | use lpp.lpp_demux.all; |
|
49 | 49 | use lpp.lpp_top_lfr_pkg.all; |
|
50 | 50 | |
|
51 | 51 | entity leon3mp is |
|
52 | 52 | generic ( |
|
53 | 53 | fabtech : integer := CFG_FABTECH; |
|
54 | 54 | memtech : integer := CFG_MEMTECH; |
|
55 | 55 | padtech : integer := CFG_PADTECH; |
|
56 | 56 | clktech : integer := CFG_CLKTECH; |
|
57 | 57 | disas : integer := CFG_DISAS; -- Enable disassembly to console |
|
58 | 58 | dbguart : integer := CFG_DUART; -- Print UART on console |
|
59 | 59 | pclow : integer := CFG_PCLOW |
|
60 | 60 | ); |
|
61 | 61 | port ( |
|
62 | 62 | clk50MHz : in std_ulogic; |
|
63 | 63 | reset : in std_ulogic; |
|
64 | 64 | ramclk : out std_logic; |
|
65 | 65 | |
|
66 | 66 | ahbrxd : in std_ulogic; -- DSU rx data |
|
67 | 67 | ahbtxd : out std_ulogic; -- DSU tx data |
|
68 | 68 | dsubre : in std_ulogic; |
|
69 | 69 | dsuact : out std_ulogic; |
|
70 | 70 | urxd1 : in std_ulogic; -- UART1 rx data |
|
71 | 71 | utxd1 : out std_ulogic; -- UART1 tx data |
|
72 | 72 | errorn : out std_ulogic; |
|
73 | 73 | |
|
74 | 74 | address : out std_logic_vector(18 downto 0); |
|
75 | 75 | data : inout std_logic_vector(31 downto 0); |
|
76 | 76 | gpio : inout std_logic_vector(6 downto 0); -- I/O port |
|
77 | 77 | |
|
78 | 78 | nBWa : out std_logic; |
|
79 | 79 | nBWb : out std_logic; |
|
80 | 80 | nBWc : out std_logic; |
|
81 | 81 | nBWd : out std_logic; |
|
82 | 82 | nBWE : out std_logic; |
|
83 | 83 | nADSC : out std_logic; |
|
84 | 84 | nADSP : out std_logic; |
|
85 | 85 | nADV : out std_logic; |
|
86 | 86 | nGW : out std_logic; |
|
87 | 87 | nCE1 : out std_logic; |
|
88 | 88 | CE2 : out std_logic; |
|
89 | 89 | nCE3 : out std_logic; |
|
90 | 90 | nOE : out std_logic; |
|
91 | 91 | MODE : out std_logic; |
|
92 | 92 | SSRAM_CLK : out std_logic; |
|
93 | 93 | ZZ : out std_logic; |
|
94 | 94 | --------------------------------------------------------------------- |
|
95 | 95 | --- AJOUT TEST ------------------------In/Out----------------------- |
|
96 | 96 | --------------------------------------------------------------------- |
|
97 | 97 | -- UART |
|
98 | 98 | UART_RXD : in std_logic; |
|
99 | 99 | UART_TXD : out std_logic; |
|
100 | 100 | -- ACQ |
|
101 | 101 | CNV_CH1 : OUT STD_LOGIC; |
|
102 | 102 | SCK_CH1 : OUT STD_LOGIC; |
|
103 | 103 | SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
104 | 104 | Bias_Fails : out std_logic; |
|
105 | 105 | -- ADC |
|
106 | 106 | -- ADC_in : in AD7688_in(4 downto 0); |
|
107 | 107 | -- ADC_out : out AD7688_out; |
|
108 | 108 | |
|
109 | 109 | -- CNA |
|
110 | 110 | -- DAC_SYNC : out std_logic; |
|
111 | 111 | -- DAC_SCLK : out std_logic; |
|
112 | 112 | -- DAC_DATA : out std_logic; |
|
113 | 113 | -- Diver |
|
114 | 114 | SPW1_EN : out std_logic; |
|
115 | 115 | SPW2_EN : out std_logic; |
|
116 | 116 | TEST : out std_logic_vector(3 downto 0); |
|
117 | 117 | |
|
118 | 118 | BP : in std_logic; |
|
119 | 119 | --------------------------------------------------------------------- |
|
120 | 120 | led : out std_logic_vector(1 downto 0) |
|
121 | 121 | ); |
|
122 | 122 | end; |
|
123 | 123 | |
|
124 | 124 | architecture Behavioral of leon3mp is |
|
125 | 125 | |
|
126 | 126 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
|
127 | 127 | CFG_GRETH+CFG_AHB_JTAG; |
|
128 | 128 | constant maxahbm : integer := maxahbmsp; |
|
129 | 129 | |
|
130 | 130 | --Clk & Rst g�n� |
|
131 | 131 | signal vcc : std_logic_vector(4 downto 0); |
|
132 | 132 | signal gnd : std_logic_vector(4 downto 0); |
|
133 | 133 | signal resetnl : std_ulogic; |
|
134 | 134 | signal clk2x : std_ulogic; |
|
135 | 135 | signal lclk : std_ulogic; |
|
136 | 136 | signal lclk2x : std_ulogic; |
|
137 | 137 | signal clkm : std_ulogic; |
|
138 | 138 | signal rstn : std_ulogic; |
|
139 | 139 | signal rstraw : std_ulogic; |
|
140 | 140 | signal pciclk : std_ulogic; |
|
141 | 141 | signal sdclkl : std_ulogic; |
|
142 | 142 | signal cgi : clkgen_in_type; |
|
143 | 143 | signal cgo : clkgen_out_type; |
|
144 | 144 | --- AHB / APB |
|
145 | 145 | signal apbi : apb_slv_in_type; |
|
146 | 146 | signal apbo : apb_slv_out_vector := (others => apb_none); |
|
147 | 147 | signal ahbsi : ahb_slv_in_type; |
|
148 | 148 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); |
|
149 | 149 | signal ahbmi : ahb_mst_in_type; |
|
150 | 150 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); |
|
151 | 151 | --UART |
|
152 | 152 | signal ahbuarti : uart_in_type; |
|
153 | 153 | signal ahbuarto : uart_out_type; |
|
154 | 154 | signal apbuarti : uart_in_type; |
|
155 | 155 | signal apbuarto : uart_out_type; |
|
156 | 156 | --MEM CTRLR |
|
157 | 157 | signal memi : memory_in_type; |
|
158 | 158 | signal memo : memory_out_type; |
|
159 | 159 | signal wpo : wprot_out_type; |
|
160 | 160 | signal sdo : sdram_out_type; |
|
161 | 161 | --IRQ |
|
162 | 162 | signal irqi : irq_in_vector(0 to CFG_NCPU-1); |
|
163 | 163 | signal irqo : irq_out_vector(0 to CFG_NCPU-1); |
|
164 | 164 | --Timer |
|
165 | 165 | signal gpti : gptimer_in_type; |
|
166 | 166 | signal gpto : gptimer_out_type; |
|
167 | 167 | --GPIO |
|
168 | 168 | signal gpioi : gpio_in_type; |
|
169 | 169 | signal gpioo : gpio_out_type; |
|
170 | 170 | --DSU |
|
171 | 171 | signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); |
|
172 | 172 | signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); |
|
173 | 173 | signal dsui : dsu_in_type; |
|
174 | 174 | signal dsuo : dsu_out_type; |
|
175 | 175 | |
|
176 | 176 | --------------------------------------------------------------------- |
|
177 | 177 | --- AJOUT TEST ------------------------Signaux---------------------- |
|
178 | 178 | --------------------------------------------------------------------- |
|
179 | 179 | -- FIFOs |
|
180 | 180 | signal FifoF0_Empty : std_logic_vector(4 downto 0); |
|
181 | 181 | signal FifoF0_Data : std_logic_vector(79 downto 0); |
|
182 | 182 | signal FifoF1_Empty : std_logic_vector(4 downto 0); |
|
183 | 183 | signal FifoF1_Data : std_logic_vector(79 downto 0); |
|
184 | 184 | signal FifoF3_Empty : std_logic_vector(4 downto 0); |
|
185 | 185 | signal FifoF3_Data : std_logic_vector(79 downto 0); |
|
186 | 186 | |
|
187 | 187 | signal FifoINT_Full : std_logic_vector(4 downto 0); |
|
188 | 188 | signal FifoINT_Data : std_logic_vector(79 downto 0); |
|
189 | 189 | |
|
190 | 190 | signal FifoOUT_Full : std_logic_vector(1 downto 0); |
|
191 | 191 | |
|
192 | 192 | -- MATRICE SPECTRALE |
|
193 | 193 | signal SM_FlagError : std_logic; |
|
194 | 194 | signal SM_Pong : std_logic; |
|
195 | 195 | signal SM_Read : std_logic_vector(4 downto 0); |
|
196 | 196 | signal SM_Write : std_logic_vector(1 downto 0); |
|
197 | signal SM_ReUse : std_logic_vector(4 downto 0); | |
|
198 | signal SM_Param : std_logic_vector(3 downto 0); | |
|
197 | 199 | signal SM_Data : std_logic_vector(63 downto 0); |
|
198 | 200 | |
|
199 | 201 | signal Dma_acq : std_logic; |
|
200 | 202 | |
|
201 | 203 | -- FFT |
|
202 | 204 | signal FFT_Load : std_logic; |
|
203 | 205 | signal FFT_Read : std_logic_vector(4 downto 0); |
|
204 | 206 | signal FFT_Write : std_logic_vector(4 downto 0); |
|
205 | 207 | signal FFT_ReUse : std_logic_vector(4 downto 0); |
|
206 | 208 | signal FFT_Data : std_logic_vector(79 downto 0); |
|
207 | 209 | |
|
208 | 210 | -- DEMUX |
|
209 | 211 | signal DEMU_Read : std_logic_vector(14 downto 0); |
|
210 | 212 | signal DEMU_Empty : std_logic_vector(4 downto 0); |
|
211 | 213 | signal DEMU_Data : std_logic_vector(79 downto 0); |
|
212 | 214 | |
|
213 | 215 | -- ACQ |
|
214 | ||
|
215 | 216 | signal sample_val : STD_LOGIC; |
|
216 | 217 | signal sample : Samples(8-1 DOWNTO 0); |
|
217 | 218 | |
|
218 | 219 | signal TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
219 | 220 | signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
220 | 221 | signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
221 | 222 | signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
222 | 223 | signal TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
223 | 224 | signal TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
224 | 225 | |
|
225 | 226 | -- ADC |
|
226 | 227 | --signal SmplClk : std_logic; |
|
227 | 228 | --signal ADC_DataReady : std_logic; |
|
228 | 229 | --signal ADC_SmplOut : Samples_out(4 downto 0); |
|
229 | 230 | --signal enableADC : std_logic; |
|
230 | 231 | -- |
|
231 | 232 | --signal WG_Write : std_logic_vector(4 downto 0); |
|
232 | 233 | --signal WG_ReUse : std_logic_vector(4 downto 0); |
|
233 | 234 | --signal WG_DATA : std_logic_vector(79 downto 0); |
|
234 | 235 | --signal s_out : std_logic_vector(79 downto 0); |
|
235 | 236 | -- |
|
236 | 237 | --signal fuller : std_logic_vector(4 downto 0); |
|
237 | 238 | --signal reader : std_logic_vector(4 downto 0); |
|
238 | 239 | --signal try : std_logic_vector(1 downto 0); |
|
239 | 240 | --signal TXDint : std_logic; |
|
240 | 241 | -- |
|
241 | 242 | ---- IIR Filter |
|
242 | 243 | --signal sample_clk_out : std_logic; |
|
243 | 244 | -- |
|
244 | 245 | --signal Rd : std_logic_vector(0 downto 0); |
|
245 | 246 | --signal Ept : std_logic_vector(4 downto 0); |
|
246 | 247 | -- |
|
247 | 248 | --signal Bwr : std_logic_vector(0 downto 0); |
|
248 | 249 | --signal Bre : std_logic_vector(0 downto 0); |
|
249 | 250 | --signal DataTMP : std_logic_vector(15 downto 0); |
|
250 | 251 | --signal FullUp : std_logic_vector(0 downto 0); |
|
251 | 252 | --signal EmptyUp : std_logic_vector(0 downto 0); |
|
252 | 253 | --signal FullDown : std_logic_vector(0 downto 0); |
|
253 | 254 | --signal EmptyDown : std_logic_vector(0 downto 0); |
|
254 | 255 | --------------------------------------------------------------------- |
|
255 | 256 | constant IOAEN : integer := CFG_CAN; |
|
256 | 257 | constant boardfreq : integer := 50000; |
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257 | 258 | |
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258 | 259 | begin |
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259 | 260 | |
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260 | 261 | --------------------------------------------------------------------- |
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261 | 262 | --- AJOUT TEST -------------------------------------IPs------------- |
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262 | 263 | --------------------------------------------------------------------- |
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263 | 264 | led(1 downto 0) <= gpio(1 downto 0); |
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264 | 265 | |
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265 | 266 | --- COM USB --------------------------------------------------------- |
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266 | 267 | -- MemIn0 : APB_FifoWrite |
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267 | 268 | -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) |
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268 | 269 | -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); |
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269 | 270 | -- |
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270 | 271 | -- BUF0 : APB_USB |
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271 | 272 | -- generic map (6,6,DataMax => 1024) |
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272 | 273 | -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); |
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273 | 274 | -- |
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274 | 275 | -- MemOut0 : APB_FifoRead |
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275 | 276 | -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) |
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276 | 277 | -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); |
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277 | 278 | -- |
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278 | 279 | --slrd <= usb_Read; |
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279 | 280 | --slwr <= usb_Write; |
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280 | 281 | |
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281 | 282 | --- CNA ------------------------------------------------------------- |
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282 | 283 | |
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283 | 284 | -- CONV : APB_CNA |
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284 | 285 | -- generic map (5,5) |
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285 | 286 | -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); |
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286 | 287 | |
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287 | 288 | --TEST(0) <= SmplClk; |
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288 | 289 | --TEST(1) <= WG_Write(0); |
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289 | 290 | --TEST(2) <= Fuller(0); |
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290 | 291 | --TEST(3) <= s_out(s_out'length-1); |
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291 | 292 | |
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292 | 293 | |
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293 | 294 | --SPW1_EN <= '1'; |
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294 | 295 | --SPW2_EN <= '0'; |
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295 | 296 | |
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296 | 297 | --- CAN ------------------------------------------------------------- |
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297 | 298 | |
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298 | 299 | -- Divider : Clk_divider |
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299 | 300 | -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) |
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300 | 301 | -- Port map(clkm,rstn,SmplClk); |
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301 | 302 | -- |
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302 | 303 | -- ADC : AD7688_drvr |
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303 | 304 | -- generic map (ChanelCount => 5, clkkHz => 24_576) |
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304 | 305 | -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); |
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305 | 306 | -- |
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306 | 307 | -- WG : WriteGen_ADC |
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307 | 308 | -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); |
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308 | 309 | -- |
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309 | 310 | --enableADC <= gpio(0); |
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310 | 311 | |
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311 | 312 | --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); |
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312 | 313 | -- |
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313 | 314 | -- |
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314 | 315 | -- MemIn1 : APB_FIFO |
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315 | 316 | -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
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316 | 317 | -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); |
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317 | 318 | |
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318 |
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319 | GENERIC MAP ( | |
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320 | ChanelCount => 8, | |
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321 | ncycle_cnv_high => 79, | |
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322 | ncycle_cnv => 500) | |
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323 | PORT MAP ( | |
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324 | cnv_clk => clk50MHz, -- | |
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325 | cnv_rstn => rstn, -- | |
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326 | cnv_run => '1', -- | |
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327 | cnv => CNV_CH1, -- | |
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328 | clk => clkm, -- | |
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329 | rstn => rstn, -- | |
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330 | sck => SCK_CH1, -- | |
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331 | sdo => SDO_CH1, -- | |
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332 | sample => sample, | |
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333 | sample_val => sample_val); | |
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319 | -- DIGITAL_acquisition : ADS7886_drvr | |
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320 | -- GENERIC MAP ( | |
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321 | -- ChanelCount => 8, | |
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322 | -- ncycle_cnv_high => 79, | |
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323 | -- ncycle_cnv => 500) | |
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324 | -- PORT MAP ( | |
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325 | -- cnv_clk => clk50MHz, -- | |
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326 | -- cnv_rstn => rstn, -- | |
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327 | -- cnv_run => '1', -- | |
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328 | -- cnv => CNV_CH1, -- | |
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329 | -- clk => clkm, -- | |
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330 | -- rstn => rstn, -- | |
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331 | -- sck => SCK_CH1, -- | |
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332 | -- sdo => SDO_CH1, -- | |
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333 | -- sample => sample, | |
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334 | -- sample_val => sample_val); | |
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334 | 335 | -- |
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335 | TopACQ_WenF0 <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val; | |
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336 | TopACQ_DataF0 <= sample(4) & sample(3) & sample(2) & sample(1) & sample(0); | |
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336 | --TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val; | |
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337 | --TopACQ_DataF0 <= E & D & C & B & A; | |
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338 | ||
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337 | 339 | -- |
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338 | TEST(0) <= TopACQ_WenF0(1); | |
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339 | TEST(1) <= SDO_CH1(1); | |
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340 | -- | |
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341 | -- | |
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340 | --TEST(0) <= TopACQ_WenF0(1); | |
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341 | --TEST(1) <= SDO_CH1(1); | |
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342 | 342 | -- |
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343 | 343 | --process(clkm,rstn) |
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344 | 344 | --begin |
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345 | 345 | -- if(rstn='0')then |
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346 | 346 | -- TopACQ_WenF0a <= (others => '1'); |
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347 | 347 | -- |
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348 | 348 | -- elsif(clkm'event and clkm='1')then |
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349 | 349 | -- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val; |
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350 | 350 | -- |
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351 | 351 | -- end if; |
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352 | 352 | --end process; |
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353 | 353 | |
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354 |
|
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355 |
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354 | TopACQ : lpp_top_acq | |
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355 | port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3); | |
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356 | 356 | |
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357 | 357 | Bias_Fails <= '0'; |
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358 | 358 | --- FIFO IN ------------------------------------------------------------- |
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359 | 359 | |
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360 | MemOut : APB_FIFO | |
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361 | generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) | |
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362 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9)); | |
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363 |
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364 |
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365 |
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360 | -- MemOut : APB_FIFO | |
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361 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) | |
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362 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9)); | |
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363 | Memf0 : lppFIFOxN | |
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364 | generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') | |
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365 | port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); | |
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366 | 366 | |
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367 | 367 | Memf1 : lppFIFOxN |
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368 | 368 | generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
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369 | 369 | port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(9 downto 5),TopACQ_DataF1,FifoF1_Data,open,FifoF1_Empty); |
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370 | 370 | |
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371 | 371 | Memf3 : lppFIFOxN |
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372 | 372 | generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
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373 | 373 | port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(14 downto 10),TopACQ_DataF3,FifoF3_Data,open,FifoF3_Empty); |
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374 | 374 | |
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375 | 375 | --- DEMUX ------------------------------------------------------------- |
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376 | 376 | |
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377 | 377 | DEMU0 : DEMUX |
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378 | 378 | generic map(Data_sz => 16) |
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379 | 379 | port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data); |
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380 | 380 | |
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381 | 381 | --- FFT ------------------------------------------------------------- |
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382 | 382 | |
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383 | 383 | -- MemIn : APB_FIFO |
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384 | 384 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) |
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385 | 385 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); |
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386 | 386 | |
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387 | 387 | FFT0 : FFT |
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388 | 388 | generic map(Data_sz => 16,NbData => 256) |
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389 | 389 | port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); |
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390 | 390 | |
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391 | 391 | ----- LINK MEMORY ------------------------------------------------------- |
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392 | 392 | |
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393 | 393 | -- MemOut : APB_FIFO |
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394 | 394 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) |
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395 | 395 | -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9)); |
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396 | 396 | |
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397 | 397 | MemInt : lppFIFOxN |
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398 | 398 | generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') |
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399 |
port map(rstn,clkm,clkm, |
|
|
399 | port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); | |
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400 | 400 | -- |
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401 | 401 | -- MemIn : APB_FIFO |
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402 | 402 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) |
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403 | 403 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); |
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404 | 404 | |
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405 | 405 | ----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- |
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406 | 406 | |
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407 | 407 | SM0 : MatriceSpectrale |
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408 | 408 | generic map(Input_SZ => 16,Result_SZ => 32) |
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409 | port map(clkm,rstn,FifoINT_Full,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Write,SM_Read,SM_Data); | |
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409 | port map(clkm,rstn,FifoINT_Full,FFT_ReUse,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data); | |
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410 | 410 | |
|
411 | 411 | Dma_acq <= '1'; |
|
412 | 412 | |
|
413 |
|
|
|
414 |
|
|
|
415 |
|
|
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413 | MemOut : APB_FIFO | |
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414 | generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) | |
|
415 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); | |
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416 | 416 | |
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417 | 417 | ----- FIFO ------------------------------------------------------------- |
|
418 | 418 | |
|
419 | 419 | Memtest : APB_FIFO |
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420 | 420 | generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) |
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421 | 421 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); |
|
422 | 422 | |
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423 | 423 | --***************************************TEST DEMI-FIFO******************************************************************************** |
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424 | 424 | -- MemIn : APB_FIFO |
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425 | 425 | -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) |
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426 | 426 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8)); |
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427 | 427 | -- |
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428 | 428 | -- Pont : Bridge |
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429 | 429 | -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0)); |
|
430 | 430 | -- |
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431 | 431 | -- MemOut : APB_FIFO |
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432 | 432 | -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) |
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433 | 433 | -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9)); |
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434 | 434 | --************************************************************************************************************************************* |
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435 | 435 | |
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436 | 436 | --- UART ------------------------------------------------------------- |
|
437 | 437 | |
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438 | 438 | COM0 : APB_UART |
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439 | 439 | generic map (pindex => 4, paddr => 4) |
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440 | 440 | port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD); |
|
441 | 441 | |
|
442 | 442 | --- DELAY ------------------------------------------------------------ |
|
443 | 443 | |
|
444 | 444 | -- Delay0 : APB_Delay |
|
445 | 445 | -- generic map (pindex => 4, paddr => 4) |
|
446 | 446 | -- port map (clkm,rstn,apbi,apbo(4)); |
|
447 | 447 | |
|
448 | 448 | --- IIR Filter ------------------------------------------------------- |
|
449 | 449 | --Test(0) <= sample_clk_out; |
|
450 | 450 | -- |
|
451 | 451 | -- |
|
452 | 452 | -- IIR1: APB_IIR_Filter |
|
453 | 453 | -- generic map( |
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454 | 454 | -- tech => CFG_MEMTECH, |
|
455 | 455 | -- pindex => 8, |
|
456 | 456 | -- paddr => 8, |
|
457 | 457 | -- Sample_SZ => Sample_SZ, |
|
458 | 458 | -- ChanelsCount => ChanelsCount, |
|
459 | 459 | -- Coef_SZ => Coef_SZ, |
|
460 | 460 | -- CoefCntPerCel => CoefCntPerCel, |
|
461 | 461 | -- Cels_count => Cels_count, |
|
462 | 462 | -- virgPos => virgPos |
|
463 | 463 | -- ) |
|
464 | 464 | -- port map( |
|
465 | 465 | -- rst => rstn, |
|
466 | 466 | -- clk => clkm, |
|
467 | 467 | -- apbi => apbi, |
|
468 | 468 | -- apbo => apbo(8), |
|
469 | 469 | -- sample_clk_out => sample_clk_out, |
|
470 | 470 | -- GOtest => Test(1), |
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471 | 471 | -- CoefsInitVal => (others => '1') |
|
472 | 472 | -- ); |
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473 | 473 | ---------------------------------------------------------------------- |
|
474 | 474 | |
|
475 | 475 | ---------------------------------------------------------------------- |
|
476 | 476 | --- Reset and Clock generation ------------------------------------- |
|
477 | 477 | ---------------------------------------------------------------------- |
|
478 | 478 | |
|
479 | 479 | vcc <= (others => '1'); gnd <= (others => '0'); |
|
480 | 480 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
|
481 | 481 | |
|
482 | 482 | rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); |
|
483 | 483 | |
|
484 | 484 | |
|
485 | 485 | clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); |
|
486 | 486 | |
|
487 | 487 | clkgen0 : clkgen -- clock generator |
|
488 | 488 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
|
489 | 489 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) |
|
490 | 490 | port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); |
|
491 | 491 | |
|
492 | 492 | ramclk <= clkm; |
|
493 | 493 | process(lclk2x) |
|
494 | 494 | begin |
|
495 | 495 | if lclk2x'event and lclk2x = '1' then |
|
496 | 496 | lclk <= not lclk; |
|
497 | 497 | end if; |
|
498 | 498 | end process; |
|
499 | 499 | |
|
500 | 500 | ---------------------------------------------------------------------- |
|
501 | 501 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
|
502 | 502 | ---------------------------------------------------------------------- |
|
503 | 503 | |
|
504 | 504 | l3 : if CFG_LEON3 = 1 generate |
|
505 | 505 | cpu : for i in 0 to CFG_NCPU-1 generate |
|
506 | 506 | u0 : leon3s -- LEON3 processor |
|
507 | 507 | generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
|
508 | 508 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
|
509 | 509 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
|
510 | 510 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
|
511 | 511 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
|
512 | 512 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
|
513 | 513 | port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
|
514 | 514 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
|
515 | 515 | end generate; |
|
516 | 516 | errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); |
|
517 | 517 | |
|
518 | 518 | dsugen : if CFG_DSU = 1 generate |
|
519 | 519 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
520 | 520 | generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
521 | 521 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
522 | 522 | port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
523 | 523 | -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); |
|
524 | 524 | dsui.enable <= '1'; |
|
525 | 525 | dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); |
|
526 | 526 | dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); |
|
527 | 527 | end generate; |
|
528 | 528 | end generate; |
|
529 | 529 | |
|
530 | 530 | nodsu : if CFG_DSU = 0 generate |
|
531 | 531 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; |
|
532 | 532 | end generate; |
|
533 | 533 | |
|
534 | 534 | irqctrl : if CFG_IRQ3_ENABLE /= 0 generate |
|
535 | 535 | irqctrl0 : irqmp -- interrupt controller |
|
536 | 536 | generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
|
537 | 537 | port map (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
538 | 538 | end generate; |
|
539 | 539 | irq3 : if CFG_IRQ3_ENABLE = 0 generate |
|
540 | 540 | x : for i in 0 to CFG_NCPU-1 generate |
|
541 | 541 | irqi(i).irl <= "0000"; |
|
542 | 542 | end generate; |
|
543 | 543 | apbo(2) <= apb_none; |
|
544 | 544 | end generate; |
|
545 | 545 | |
|
546 | 546 | ---------------------------------------------------------------------- |
|
547 | 547 | --- Memory controllers --------------------------------------------- |
|
548 | 548 | ---------------------------------------------------------------------- |
|
549 | 549 | |
|
550 | 550 | memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) |
|
551 | 551 | port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); |
|
552 | 552 | |
|
553 | 553 | memi.brdyn <= '1'; memi.bexcn <= '1'; |
|
554 | 554 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; |
|
555 | 555 | |
|
556 | 556 | bdr : for i in 0 to 3 generate |
|
557 | 557 | data_pad : iopadv generic map (tech => padtech, width => 8) |
|
558 | 558 | port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), |
|
559 | 559 | memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); |
|
560 | 560 | end generate; |
|
561 | 561 | |
|
562 | 562 | |
|
563 | 563 | addr_pad : outpadv generic map (width => 19, tech => padtech) |
|
564 | 564 | port map (address, memo.address(20 downto 2)); |
|
565 | 565 | |
|
566 | 566 | |
|
567 | 567 | SSRAM_0:entity ssram_plugin |
|
568 | 568 | generic map (tech => padtech) |
|
569 | 569 | port map |
|
570 | 570 | (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); |
|
571 | 571 | |
|
572 | 572 | ---------------------------------------------------------------------- |
|
573 | 573 | --- AHB CONTROLLER ------------------------------------------------- |
|
574 | 574 | ---------------------------------------------------------------------- |
|
575 | 575 | |
|
576 | 576 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
577 | 577 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
578 | 578 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
579 | 579 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) |
|
580 | 580 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
581 | 581 | |
|
582 | 582 | ---------------------------------------------------------------------- |
|
583 | 583 | --- AHB UART ------------------------------------------------------- |
|
584 | 584 | ---------------------------------------------------------------------- |
|
585 | 585 | |
|
586 | 586 | dcomgen : if CFG_AHB_UART = 1 generate |
|
587 | 587 | dcom0: ahbuart -- Debug UART |
|
588 | 588 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) |
|
589 | 589 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); |
|
590 | 590 | dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); |
|
591 | 591 | dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); |
|
592 | 592 | -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; |
|
593 | 593 | end generate; |
|
594 | 594 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; |
|
595 | 595 | |
|
596 | 596 | ---------------------------------------------------------------------- |
|
597 | 597 | --- APB Bridge ----------------------------------------------------- |
|
598 | 598 | ---------------------------------------------------------------------- |
|
599 | 599 | |
|
600 | 600 | apb0 : apbctrl -- AHB/APB bridge |
|
601 | 601 | generic map (hindex => 1, haddr => CFG_APBADDR) |
|
602 | 602 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); |
|
603 | 603 | |
|
604 | 604 | ---------------------------------------------------------------------- |
|
605 | 605 | --- GPT Timer ------------------------------------------------------ |
|
606 | 606 | ---------------------------------------------------------------------- |
|
607 | 607 | |
|
608 | 608 | gpt : if CFG_GPT_ENABLE /= 0 generate |
|
609 | 609 | timer0 : gptimer -- timer unit |
|
610 | 610 | generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
611 | 611 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
612 | 612 | nbits => CFG_GPT_TW) |
|
613 | 613 | port map (rstn, clkm, apbi, apbo(3), gpti, gpto); |
|
614 | 614 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; |
|
615 | 615 | -- led(4) <= gpto.wdog; |
|
616 | 616 | end generate; |
|
617 | 617 | notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; |
|
618 | 618 | |
|
619 | 619 | |
|
620 | 620 | ---------------------------------------------------------------------- |
|
621 | 621 | --- APB UART ------------------------------------------------------- |
|
622 | 622 | ---------------------------------------------------------------------- |
|
623 | 623 | |
|
624 | 624 | ua1 : if CFG_UART1_ENABLE /= 0 generate |
|
625 | 625 | uart1 : apbuart -- UART 1 |
|
626 | 626 | generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
627 | 627 | fifosize => CFG_UART1_FIFO) |
|
628 | 628 | port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); |
|
629 | 629 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; |
|
630 | 630 | apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; |
|
631 | 631 | -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; |
|
632 | 632 | end generate; |
|
633 | 633 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; |
|
634 | 634 | |
|
635 | 635 | ---------------------------------------------------------------------- |
|
636 | 636 | --- GPIO ----------------------------------------------------------- |
|
637 | 637 | ---------------------------------------------------------------------- |
|
638 | 638 | |
|
639 | 639 | gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit |
|
640 | 640 | grgpio0: grgpio |
|
641 | 641 | generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) |
|
642 | 642 | port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); |
|
643 | 643 | |
|
644 | 644 | pio_pads : for i in 0 to 6 generate |
|
645 | 645 | pio_pad : iopad generic map (tech => padtech) |
|
646 | 646 | port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); |
|
647 | 647 | end generate; |
|
648 | 648 | end generate; |
|
649 | 649 | |
|
650 | 650 | |
|
651 | 651 | end Behavioral; No newline at end of file |
@@ -1,149 +1,170 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | 22 | library IEEE; |
|
23 | 23 | use IEEE.std_logic_1164.all; |
|
24 | 24 | use IEEE.numeric_std.all; |
|
25 | 25 | |
|
26 | 26 | entity DEMUX is |
|
27 | 27 | generic( |
|
28 | 28 | Data_sz : integer range 1 to 32 := 16); |
|
29 | 29 | port( |
|
30 | 30 | clk : in std_logic; |
|
31 | 31 | rstn : in std_logic; |
|
32 | 32 | |
|
33 | 33 | Read : in std_logic_vector(4 downto 0); |
|
34 | 34 | Load : in std_logic; |
|
35 | 35 | |
|
36 | 36 | EmptyF0 : in std_logic_vector(4 downto 0); |
|
37 | 37 | EmptyF1 : in std_logic_vector(4 downto 0); |
|
38 | 38 | EmptyF2 : in std_logic_vector(4 downto 0); |
|
39 | 39 | |
|
40 | 40 | DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
41 | 41 | DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
42 | 42 | DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
43 | 43 | |
|
44 | WorkFreq : out std_logic_vector(1 downto 0); | |
|
44 | 45 | Read_DEMUX : out std_logic_vector(14 downto 0); |
|
45 | 46 | Empty : out std_logic_vector(4 downto 0); |
|
46 | 47 | Data : out std_logic_vector((5*Data_sz)-1 downto 0) |
|
47 | 48 | ); |
|
48 | 49 | end entity; |
|
49 | 50 | |
|
50 | 51 | |
|
51 | 52 | architecture ar_DEMUX of DEMUX is |
|
52 | 53 | |
|
53 | 54 | type etat is (eX,e0,e1,e2,e3); |
|
54 | 55 | signal ect : etat; |
|
55 | 56 | |
|
56 | 57 | |
|
57 | 58 | signal load_reg : std_logic; |
|
58 | 59 | constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1'); |
|
59 | 60 | |
|
60 | 61 | signal Countf0 : integer; |
|
61 | 62 | signal Countf1 : integer; |
|
63 | signal i : integer; | |
|
62 | 64 | |
|
63 | 65 | begin |
|
64 | 66 | process(clk,rstn) |
|
65 | 67 | begin |
|
66 | 68 | if(rstn='0')then |
|
67 | 69 | ect <= e0; |
|
68 | 70 | load_reg <= '0'; |
|
69 |
Countf0 <= |
|
|
71 | Countf0 <= 0; | |
|
70 | 72 | Countf1 <= 0; |
|
73 | i <= 0; | |
|
71 | 74 | |
|
72 | 75 | elsif(clk'event and clk='1')then |
|
73 | 76 | load_reg <= Load; |
|
74 | 77 | |
|
75 | 78 | case ect is |
|
76 | 79 | |
|
77 | 80 | when e0 => |
|
78 | 81 | if(load_reg = '1' and Load = '0')then |
|
79 | 82 | if(Countf0 = 24)then |
|
80 | 83 | Countf0 <= 0; |
|
81 | 84 | ect <= e1; |
|
82 | 85 | else |
|
83 | 86 | Countf0 <= Countf0 + 1; |
|
84 | 87 | ect <= e0; |
|
85 | 88 | end if; |
|
86 | 89 | end if; |
|
87 | 90 | |
|
88 | 91 | when e1 => |
|
89 | 92 | if(load_reg = '1' and Load = '0')then |
|
90 | 93 | if(Countf1 = 74)then |
|
91 | 94 | Countf1 <= 0; |
|
92 | 95 | ect <= e2; |
|
93 | 96 | else |
|
94 | 97 | Countf1 <= Countf1 + 1; |
|
95 |
|
|
|
98 | if(i=4)then | |
|
99 | i <= 0; | |
|
100 | ect <= e0; | |
|
101 | else | |
|
102 | i <= i+1; | |
|
103 | ect <= e1; | |
|
104 | end if; | |
|
96 | 105 | end if; |
|
97 | 106 | end if; |
|
98 | 107 | |
|
99 | 108 | when e2 => |
|
100 | 109 | if(load_reg = '1' and Load = '0')then |
|
101 |
|
|
|
110 | if(i=4)then | |
|
111 | i <= 0; | |
|
112 | ect <= e0; | |
|
113 | else | |
|
114 | i <= i+1; | |
|
115 | ect <= e2; | |
|
116 | end if; | |
|
102 | 117 | end if; |
|
103 | 118 | |
|
104 | 119 | when others => |
|
105 | 120 | null; |
|
106 | 121 | |
|
107 | 122 | end case; |
|
108 | 123 | end if; |
|
109 | 124 | end process; |
|
110 | 125 | |
|
111 | 126 | with ect select |
|
112 | 127 | Empty <= EmptyF0 when e0, |
|
113 | 128 | EmptyF1 when e1, |
|
114 | 129 | EmptyF2 when e2, |
|
115 | 130 | (others => '1') when others; |
|
116 | 131 | |
|
117 | 132 | with ect select |
|
118 | 133 | Data <= DataF0 when e0, |
|
119 | 134 | DataF1 when e1, |
|
120 | 135 | DataF2 when e2, |
|
121 | 136 | (others => '0') when others; |
|
122 | 137 | |
|
123 | 138 | with ect select |
|
124 | 139 | Read_DEMUX <= Dummy_Read & Dummy_Read & Read when e0, |
|
125 | 140 | Dummy_Read & Read & Dummy_Read when e1, |
|
126 | 141 | Read & Dummy_Read & Dummy_Read when e2, |
|
127 | 142 | (others => '1') when others; |
|
128 | 143 | |
|
144 | with ect select | |
|
145 | WorkFreq <= "01" when e0, | |
|
146 | "10" when e1, | |
|
147 | "11" when e2, | |
|
148 | "00" when others; | |
|
149 | ||
|
129 | 150 | end architecture; |
|
130 | 151 | |
|
131 | 152 | |
|
132 | 153 | |
|
133 | 154 | |
|
134 | 155 | |
|
135 | 156 | |
|
136 | 157 | |
|
137 | 158 | |
|
138 | 159 | |
|
139 | 160 | |
|
140 | 161 | |
|
141 | 162 | |
|
142 | 163 | |
|
143 | 164 | |
|
144 | 165 | |
|
145 | 166 | |
|
146 | 167 | |
|
147 | 168 | |
|
148 | 169 | |
|
149 | 170 |
@@ -1,58 +1,59 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | 22 | library ieee; |
|
23 | 23 | use ieee.std_logic_1164.all; |
|
24 | 24 | library grlib; |
|
25 | 25 | use grlib.amba.all; |
|
26 | 26 | use std.textio.all; |
|
27 | 27 | library lpp; |
|
28 | 28 | use lpp.lpp_amba.all; |
|
29 | 29 | |
|
30 | 30 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on |
|
31 | 31 | |
|
32 |
package lpp_demux is |
|
|
32 | package lpp_demux is | |
|
33 | 33 | |
|
34 | 34 | component DEMUX is |
|
35 | 35 | generic( |
|
36 | 36 | Data_sz : integer range 1 to 32 := 16); |
|
37 | 37 | port( |
|
38 | 38 | clk : in std_logic; |
|
39 | 39 | rstn : in std_logic; |
|
40 | 40 | |
|
41 | 41 | Read : in std_logic_vector(4 downto 0); |
|
42 | 42 | Load : in std_logic; |
|
43 | 43 | |
|
44 | 44 | EmptyF0 : in std_logic_vector(4 downto 0); |
|
45 | 45 | EmptyF1 : in std_logic_vector(4 downto 0); |
|
46 | 46 | EmptyF2 : in std_logic_vector(4 downto 0); |
|
47 | 47 | |
|
48 | 48 | DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
49 | 49 | DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
50 | 50 | DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
51 | 51 | |
|
52 | WorkFreq : out std_logic_vector(1 downto 0); | |
|
52 | 53 | Read_DEMUX : out std_logic_vector(14 downto 0); |
|
53 | 54 | Empty : out std_logic_vector(4 downto 0); |
|
54 | 55 | Data : out std_logic_vector((5*Data_sz)-1 downto 0) |
|
55 | 56 | ); |
|
56 | 57 | end component; |
|
57 | 58 | |
|
58 | 59 | end; No newline at end of file |
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