HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r590:f6390d699855

merge simu_with_leon3...

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r590:f6390d699855 JC

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r590:f6390d699855

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designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +35 -2

                component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
+               SIGNAL rstn_50 : STD_LOGIC;
+               SIGNAL clk_lock : STD_LOGIC;
+               SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
+               SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
+               SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
+               SIGNAL     ahbrxd: STD_LOGIC;
+               SIGNAL     ahbtxd: STD_LOGIC;
+               SIGNAL     urxd1 : STD_LOGIC;
+               SIGNAL     utxd1 : STD_LOGIC;
              BEGIN  -- beh
                -----------------------------------------------------------------------------
+               -- CLK_LOCK
+               -----------------------------------------------------------------------------
+               rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
+               PROCESS (clk50MHz_int, rstn_50)
+               BEGIN  -- PROCESS
+                 IF rstn_50 = '0' THEN         -- asynchronous reset (active low)
+                   clk_lock <= '0';
+                   clk_busy_counter <= (OTHERS => '0');
+                   nSRAM_BUSY_reg <= '0';
+                 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN  -- rising clock edge
+                   nSRAM_BUSY_reg <= nSRAM_BUSY;
+                   IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
+                     IF clk_busy_counter = "1111"  THEN
+                       clk_lock <= '1';
+                     ELSE
+                       clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
+                     END IF;
+                   END IF;
+                 END IF;
+               END PROCESS;
+               -----------------------------------------------------------------------------
                -- CLK
                -----------------------------------------------------------------------------
-               rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
-               rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
+               rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
+               rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
                --clk_pad : clkint  port map (A => clk50MHz, Y => clk50MHz_int );
                clk50MHz_int <= clk50MHz;

lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd +49 -7

 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
                  OTHERS => (OTHERS => '0'));
-               TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
+               TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
                SIGNAL state : AHB_DMA_FSM_STATE;
                SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
                SIGNAL bus_request : STD_LOGIC;
                SIGNAL bus_lock : STD_LOGIC;
+               SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
+               SIGNAL HREADY_pre : STD_LOGIC;
+               SIGNAL HREADY_falling : STD_LOGIC;
+               SIGNAL inhib_ren : STD_LOGIC;
              BEGIN
                -----------------------------------------------------------------------------
                -----------------------------------------------------------------------------
                AHB_Master_Out.HADDR  <= address(31 DOWNTO 6) & address_counter_reg & "00";
-               AHB_Master_Out.HWDATA <= ahbdrivedata(data);
+               AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
-               -----------------------------------------------------------------------------
                --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
                --ren <= NOT beat;
                -----------------------------------------------------------------------------
+               HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1';
-               PROCESS (clk, rstn)
                BEGIN  -- PROCESS
                  IF rstn = '0' THEN                  -- asynchronous reset (active low)
                    state <= IDLE;
                    done <= '0';
+                   ren <= '1';
-                   address_counter_reg <= (OTHERS => '0');
                    AHB_Master_Out.HTRANS  <= HTRANS_IDLE;
                    AHB_Master_Out.HBUSREQ <= '0';
                    AHB_Master_Out.HLOCK   <= '0';
+                   data_reg <= (OTHERS => '0');
+                   HREADY_pre <= '0';
+                   inhib_ren <= '0';
                  ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+                   HREADY_pre <= AHB_Master_In.HREADY;
+                   IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1'  THEN
+                     data_reg <= data;
+                   END IF;
-                   done <= '0';
+                   ren <= '1';
+                   inhib_ren <= '0';
                    CASE state IS
                      WHEN IDLE =>
                        AHB_Master_Out.HBUSREQ <= '0';
                        AHB_Master_Out.HTRANS  <= HTRANS_IDLE;
                        address_counter_reg <= (OTHERS => '0');
                        IF send = '1' THEN
+                         state <= s_INIT_TRANS;
+                       END IF;
+                     WHEN s_INIT_TRANS =>
-                         AHB_Master_Out.HBUSREQ <= '1';
-                         AHB_Master_Out.HLOCK   <= '1';
-                         AHB_Master_Out.HTRANS  <= HTRANS_IDLE;
-                         state <= s_ARBITER;
-                       END IF;
                      WHEN s_ARBITER =>
                        AHB_Master_Out.HBUSREQ <= '1';
                        AHB_Master_Out.HTRANS  <= HTRANS_IDLE;
                        address_counter_reg <= (OTHERS => '0');
-                       IF AHB_Master_In.HGRANT(hindex) = '1' THEN
+                       IF  AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
                          AHB_Master_Out.HTRANS  <= HTRANS_IDLE;
                          state <= s_CTRL;
                        END IF;
                      WHEN s_CTRL =>
+                       inhib_ren              <= '1';
                        AHB_Master_Out.HBUSREQ <= '1';
                        AHB_Master_Out.HLOCK   <= '1';
                        AHB_Master_Out.HTRANS  <= HTRANS_NONSEQ;
                        IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
-                         AHB_Master_Out.HTRANS  <= HTRANS_SEQ;
+                         --AHB_Master_Out.HTRANS  <= HTRANS_SEQ;
                          state <= s_CTRL_DATA;
+                         --ren <= '0';
                        END IF;
                      WHEN s_CTRL_DATA =>
                          state <= s_DATA;
                        END IF;
+                       ren <= HREADY_falling;
+                       --IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
+                       --  ren <= '0';
+                       --END IF;
                      WHEN s_DATA =>
+                       ren <= HREADY_falling;
-                       AHB_Master_Out.HBUSREQ <= '0';
-                       AHB_Master_Out.HLOCK   <= '0';
+                       --AHB_Master_Out.HLOCK   <= '0';
                        AHB_Master_Out.HTRANS  <= HTRANS_IDLE;
                        IF AHB_Master_In.HREADY = '1' THEN
+                         AHB_Master_Out.HLOCK   <= '0';
                          state <= IDLE;
                          done <= '1';
                        END IF;
                ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
                data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
                -----------------------------------------------------------------------------
-               ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
+               --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
                -----------------------------------------------------------------------------
                --PROCESS (clk, rstn)

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