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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 --library proasic3l;
49 49 --use proasic3l.all;
50 50
51 51 ENTITY LFR_EQM IS
52 52 --GENERIC (
53 53 -- Mem_use : INTEGER := use_RAM);
54 54
55 55 PORT (
56 56 clk50MHz : IN STD_ULOGIC;
57 57 clk49_152MHz : IN STD_ULOGIC;
58 58 reset : IN STD_ULOGIC;
59 59
60 60 -- TAG --------------------------------------------------------------------
61 61 TAG1 : IN STD_ULOGIC; -- DSU rx data
62 62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
63 63 -- UART APB ---------------------------------------------------------------
64 64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
65 65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
66 66 -- RAM --------------------------------------------------------------------
67 67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
68 68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69 69
70 70 nSRAM_MBE : INOUT STD_LOGIC; -- new
71 71 nSRAM_E1 : OUT STD_LOGIC; -- new
72 72 nSRAM_E2 : OUT STD_LOGIC; -- new
73 73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
74 74 nSRAM_W : OUT STD_LOGIC; -- new
75 75 nSRAM_G : OUT STD_LOGIC; -- new
76 76 nSRAM_BUSY : IN STD_LOGIC; -- new
77 77 -- SPW --------------------------------------------------------------------
78 78 spw1_en : OUT STD_LOGIC; -- new
79 79 spw1_din : IN STD_LOGIC;
80 80 spw1_sin : IN STD_LOGIC;
81 81 spw1_dout : OUT STD_LOGIC;
82 82 spw1_sout : OUT STD_LOGIC;
83 83 spw2_en : OUT STD_LOGIC; -- new
84 84 spw2_din : IN STD_LOGIC;
85 85 spw2_sin : IN STD_LOGIC;
86 86 spw2_dout : OUT STD_LOGIC;
87 87 spw2_sout : OUT STD_LOGIC;
88 88 -- ADC --------------------------------------------------------------------
89 89 bias_fail_sw : OUT STD_LOGIC;
90 90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
91 91 ADC_smpclk : OUT STD_LOGIC;
92 92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
93 93 -- DAC --------------------------------------------------------------------
94 94 DAC_SDO : OUT STD_LOGIC;
95 95 DAC_SCK : OUT STD_LOGIC;
96 96 DAC_SYNC : OUT STD_LOGIC;
97 97 DAC_CAL_EN : OUT STD_LOGIC;
98 98 -- HK ---------------------------------------------------------------------
99 99 HK_smpclk : OUT STD_LOGIC;
100 100 ADC_OEB_bar_HK : OUT STD_LOGIC;
101 101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 102 ---------------------------------------------------------------------------
103 103 TAG8 : OUT STD_LOGIC
104 104 );
105 105
106 106 END LFR_EQM;
107 107
108 108
109 109 ARCHITECTURE beh OF LFR_EQM IS
110 110
111 111 SIGNAL clk_25 : STD_LOGIC := '0';
112 112 SIGNAL clk_24 : STD_LOGIC := '0';
113 113 -----------------------------------------------------------------------------
114 114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
116 116
117 117 -- CONSTANTS
118 118 CONSTANT CFG_PADTECH : INTEGER := inferred;
119 119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
120 120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
121 121 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
122 122
123 123 SIGNAL apbi_ext : apb_slv_in_type;
124 124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
125 125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
126 126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
127 127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
128 128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
129 129
130 130 -- Spacewire signals
131 131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 134 SIGNAL spw_rxtxclk : STD_ULOGIC;
135 135 SIGNAL spw_rxclkn : STD_ULOGIC;
136 136 SIGNAL spw_clk : STD_LOGIC;
137 137 SIGNAL swni : grspw_in_type;
138 138 SIGNAL swno : grspw_out_type;
139 139
140 140 --GPIO
141 141 SIGNAL gpioi : gpio_in_type;
142 142 SIGNAL gpioo : gpio_out_type;
143 143
144 144 -- AD Converter ADS7886
145 145 SIGNAL sample : Samples14v(8 DOWNTO 0);
146 146 SIGNAL sample_s : Samples(8 DOWNTO 0);
147 147 SIGNAL sample_val : STD_LOGIC;
148 148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
149 149
150 150 -----------------------------------------------------------------------------
151 151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 152
153 153 -----------------------------------------------------------------------------
154 154 SIGNAL rstn_25 : STD_LOGIC;
155 155 SIGNAL rstn_24 : STD_LOGIC;
156 156
157 157 SIGNAL LFR_soft_rstn : STD_LOGIC;
158 158 SIGNAL LFR_rstn : STD_LOGIC;
159 159
160 160 SIGNAL ADC_smpclk_s : STD_LOGIC;
161 161
162 162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
163 163
164 164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
165 165 SIGNAL clk_25_int : STD_LOGIC := '0';
166 166
167 167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
168
168
169 SIGNAL rstn_50 : STD_LOGIC;
170 SIGNAL clk_lock : STD_LOGIC;
171 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
173
174 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL ahbrxd: STD_LOGIC;
176 SIGNAL ahbtxd: STD_LOGIC;
177 SIGNAL urxd1 : STD_LOGIC;
178 SIGNAL utxd1 : STD_LOGIC;
169 179 BEGIN -- beh
170 180
171 181 -----------------------------------------------------------------------------
182 -- CLK_LOCK
183 -----------------------------------------------------------------------------
184 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
185
186 PROCESS (clk50MHz_int, rstn_50)
187 BEGIN -- PROCESS
188 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
189 clk_lock <= '0';
190 clk_busy_counter <= (OTHERS => '0');
191 nSRAM_BUSY_reg <= '0';
192 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
193 nSRAM_BUSY_reg <= nSRAM_BUSY;
194 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
195 IF clk_busy_counter = "1111" THEN
196 clk_lock <= '1';
197 ELSE
198 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
199 END IF;
200 END IF;
201 END IF;
202 END PROCESS;
203
204 -----------------------------------------------------------------------------
172 205 -- CLK
173 206 -----------------------------------------------------------------------------
174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
207 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
208 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
176 209
177 210 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
178 211 clk50MHz_int <= clk50MHz;
179 212
180 213 PROCESS(clk50MHz_int)
181 214 BEGIN
182 215 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
183 216 --clk_25_int <= NOT clk_25_int;
184 217 clk_25 <= NOT clk_25;
185 218 END IF;
186 219 END PROCESS;
187 220 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
188 221
189 222 PROCESS(clk49_152MHz)
190 223 BEGIN
191 224 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
192 225 clk_24 <= NOT clk_24;
193 226 END IF;
194 227 END PROCESS;
195 228
196 229 -----------------------------------------------------------------------------
197 230 --
198 231 leon3_soc_1 : leon3_soc
199 232 GENERIC MAP (
200 233 fabtech => apa3l,
201 234 memtech => apa3l,
202 235 padtech => inferred,
203 236 clktech => inferred,
204 237 disas => 0,
205 238 dbguart => 0,
206 239 pclow => 2,
207 240 clk_freq => 25000,
208 241 IS_RADHARD => 0,
209 242 NB_CPU => 1,
210 243 ENABLE_FPU => 1,
211 244 FPU_NETLIST => 0,
212 245 ENABLE_DSU => 1,
213 246 ENABLE_AHB_UART => 1,
214 247 ENABLE_APB_UART => 1,
215 248 ENABLE_IRQMP => 1,
216 249 ENABLE_GPT => 1,
217 250 NB_AHB_MASTER => NB_AHB_MASTER,
218 251 NB_AHB_SLAVE => NB_AHB_SLAVE,
219 252 NB_APB_SLAVE => NB_APB_SLAVE,
220 253 ADDRESS_SIZE => 19,
221 254 USES_IAP_MEMCTRLR => 1,
222 255 BYPASS_EDAC_MEMCTRLR => '0',
223 256 SRBANKSZ => 8)
224 257 PORT MAP (
225 258 clk => clk_25,
226 259 reset => rstn_25,
227 260 errorn => OPEN,
228 261
229 262 ahbrxd => TAG1,
230 263 ahbtxd => TAG3,
231 264 urxd1 => TAG2,
232 265 utxd1 => TAG4,
233 266
234 267 address => address,
235 268 data => data,
236 269 nSRAM_BE0 => OPEN,
237 270 nSRAM_BE1 => OPEN,
238 271 nSRAM_BE2 => OPEN,
239 272 nSRAM_BE3 => OPEN,
240 273 nSRAM_WE => nSRAM_W,
241 274 nSRAM_CE => nSRAM_CE,
242 275 nSRAM_OE => nSRAM_G,
243 276 nSRAM_READY => nSRAM_BUSY,
244 277 SRAM_MBE => nSRAM_MBE,
245 278
246 279 apbi_ext => apbi_ext,
247 280 apbo_ext => apbo_ext,
248 281 ahbi_s_ext => ahbi_s_ext,
249 282 ahbo_s_ext => ahbo_s_ext,
250 283 ahbi_m_ext => ahbi_m_ext,
251 284 ahbo_m_ext => ahbo_m_ext);
252 285
253 286
254 287 nSRAM_E1 <= nSRAM_CE(0);
255 288 nSRAM_E2 <= nSRAM_CE(1);
256 289
257 290 -------------------------------------------------------------------------------
258 291 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
259 292 -------------------------------------------------------------------------------
260 293 apb_lfr_management_1 : apb_lfr_management
261 294 GENERIC MAP (
262 295 tech => apa3l,
263 296 pindex => 6,
264 297 paddr => 6,
265 298 pmask => 16#fff#,
266 299 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
267 300 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
268 301 PORT MAP (
269 302 clk25MHz => clk_25,
270 303 resetn_25MHz => rstn_25, -- TODO
271 304 --clk24_576MHz => clk_24, -- 49.152MHz/2
272 305 --resetn_24_576MHz => rstn_24, -- TODO
273 306
274 307 grspw_tick => swno.tickout,
275 308 apbi => apbi_ext,
276 309 apbo => apbo_ext(6),
277 310
278 311 HK_sample => sample_s(8),
279 312 HK_val => sample_val,
280 313 HK_sel => HK_SEL,
281 314
282 315 DAC_SDO => DAC_SDO,
283 316 DAC_SCK => DAC_SCK,
284 317 DAC_SYNC => DAC_SYNC,
285 318 DAC_CAL_EN => DAC_CAL_EN,
286 319
287 320 coarse_time => coarse_time,
288 321 fine_time => fine_time,
289 322 LFR_soft_rstn => LFR_soft_rstn
290 323 );
291 324
292 325 -----------------------------------------------------------------------
293 326 --- SpaceWire --------------------------------------------------------
294 327 -----------------------------------------------------------------------
295 328
296 329 ------------------------------------------------------------------------------
297 330 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
298 331 ------------------------------------------------------------------------------
299 332 spw1_en <= '1';
300 333 spw2_en <= '1';
301 334 ------------------------------------------------------------------------------
302 335 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
303 336 ------------------------------------------------------------------------------
304 337
305 338 --spw_clk <= clk50MHz;
306 339 --spw_rxtxclk <= spw_clk;
307 340 --spw_rxclkn <= NOT spw_rxtxclk;
308 341
309 342 -- PADS for SPW1
310 343 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
311 344 PORT MAP (spw1_din, dtmp(0));
312 345 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
313 346 PORT MAP (spw1_sin, stmp(0));
314 347 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
315 348 PORT MAP (spw1_dout, swno.d(0));
316 349 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
317 350 PORT MAP (spw1_sout, swno.s(0));
318 351 -- PADS FOR SPW2
319 352 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
320 353 PORT MAP (spw2_din, dtmp(1));
321 354 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
322 355 PORT MAP (spw2_sin, stmp(1));
323 356 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
324 357 PORT MAP (spw2_dout, swno.d(1));
325 358 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
326 359 PORT MAP (spw2_sout, swno.s(1));
327 360
328 361 -- GRSPW PHY
329 362 --spw1_input: if CFG_SPW_GRSPW = 1 generate
330 363 spw_inputloop : FOR j IN 0 TO 1 GENERATE
331 364 spw_phy0 : grspw_phy
332 365 GENERIC MAP(
333 366 tech => apa3l,
334 367 rxclkbuftype => 1,
335 368 scantest => 0)
336 369 PORT MAP(
337 370 rxrst => swno.rxrst,
338 371 di => dtmp(j),
339 372 si => stmp(j),
340 373 rxclko => spw_rxclk(j),
341 374 do => swni.d(j),
342 375 ndo => swni.nd(j*5+4 DOWNTO j*5),
343 376 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
344 377 END GENERATE spw_inputloop;
345 378
346 379 -- SPW core
347 380 sw0 : grspwm GENERIC MAP(
348 381 tech => apa3l,
349 382 hindex => 1,
350 383 pindex => 5,
351 384 paddr => 5,
352 385 pirq => 11,
353 386 sysfreq => 25000, -- CPU_FREQ
354 387 rmap => 1,
355 388 rmapcrc => 1,
356 389 fifosize1 => 16,
357 390 fifosize2 => 16,
358 391 rxclkbuftype => 1,
359 392 rxunaligned => 0,
360 393 rmapbufs => 4,
361 394 ft => 0,
362 395 netlist => 0,
363 396 ports => 2,
364 397 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
365 398 memtech => apa3l,
366 399 destkey => 2,
367 400 spwcore => 1
368 401 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
369 402 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
370 403 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
371 404 )
372 405 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
373 406 spw_rxclk(1),
374 407 clk50MHz_int,
375 408 clk50MHz_int,
376 409 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
377 410 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
378 411 swni, swno);
379 412
380 413 swni.tickin <= '0';
381 414 swni.rmapen <= '1';
382 415 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
383 416 swni.tickinraw <= '0';
384 417 swni.timein <= (OTHERS => '0');
385 418 swni.dcrstval <= (OTHERS => '0');
386 419 swni.timerrstval <= (OTHERS => '0');
387 420
388 421 -------------------------------------------------------------------------------
389 422 -- LFR ------------------------------------------------------------------------
390 423 -------------------------------------------------------------------------------
391 424 LFR_rstn <= LFR_soft_rstn AND rstn_25;
392 425
393 426 lpp_lfr_1 : lpp_lfr
394 427 GENERIC MAP (
395 428 Mem_use => use_RAM,
396 429 nb_data_by_buffer_size => 32,
397 430 --nb_word_by_buffer_size => 30,
398 431 nb_snapshot_param_size => 32,
399 432 delta_vector_size => 32,
400 433 delta_vector_size_f0_2 => 7, -- log2(96)
401 434 pindex => 15,
402 435 paddr => 15,
403 436 pmask => 16#fff#,
404 437 pirq_ms => 6,
405 438 pirq_wfp => 14,
406 439 hindex => 2,
407 440 top_lfr_version => X"020146") -- aa.bb.cc version
408 441 -- AA : BOARD NUMBER
409 442 -- 0 => MINI_LFR
410 443 -- 1 => EM
411 444 -- 2 => EQM (with A3PE3000)
412 445 PORT MAP (
413 446 clk => clk_25,
414 447 rstn => LFR_rstn,
415 448 sample_B => sample_s(2 DOWNTO 0),
416 449 sample_E => sample_s(7 DOWNTO 3),
417 450 sample_val => sample_val,
418 451 apbi => apbi_ext,
419 452 apbo => apbo_ext(15),
420 453 ahbi => ahbi_m_ext,
421 454 ahbo => ahbo_m_ext(2),
422 455 coarse_time => coarse_time,
423 456 fine_time => fine_time,
424 457 data_shaping_BW => bias_fail_sw,
425 458 debug_vector => OPEN,
426 459 debug_vector_ms => OPEN); --,
427 460 --observation_vector_0 => OPEN,
428 461 --observation_vector_1 => OPEN,
429 462 --observation_reg => observation_reg);
430 463
431 464
432 465 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
433 466 sample_s(I) <= sample(I) & '0' & '0';
434 467 END GENERATE all_sample;
435 468 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
436 469
437 470 -----------------------------------------------------------------------------
438 471 --
439 472 -----------------------------------------------------------------------------
440 473 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
441 474 GENERIC MAP (
442 475 ChanelCount => 9,
443 476 ncycle_cnv_high => 13,
444 477 ncycle_cnv => 25,
445 478 FILTER_ENABLED => 16#FF#)
446 479 PORT MAP (
447 480 cnv_clk => clk_24,
448 481 cnv_rstn => rstn_24,
449 482 cnv => ADC_smpclk_s,
450 483 clk => clk_25,
451 484 rstn => rstn_25,
452 485 ADC_data => ADC_data,
453 486 ADC_nOE => ADC_OEB_bar_CH_s,
454 487 sample => sample,
455 488 sample_val => sample_val);
456 489
457 490 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
458 491
459 492 ADC_smpclk <= ADC_smpclk_s;
460 493 HK_smpclk <= ADC_smpclk_s;
461 494
462 495 TAG8 <= nSRAM_BUSY;
463 496
464 497 -----------------------------------------------------------------------------
465 498 -- HK
466 499 -----------------------------------------------------------------------------
467 500 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
468 501
469 502 END beh;
Show file before | Show file after | Hide comments
@@ -1,213 +1,255
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 -- 1.0 - initial version
24 24 -------------------------------------------------------------------------------
25 25 LIBRARY ieee;
26 26 USE ieee.std_logic_1164.ALL;
27 27 USE ieee.numeric_std.ALL;
28 28 LIBRARY grlib;
29 29 USE grlib.amba.ALL;
30 30 USE grlib.stdlib.ALL;
31 31 USE grlib.devices.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_amba.ALL;
35 35 USE lpp.apb_devices_list.ALL;
36 36 USE lpp.lpp_memory.ALL;
37 37 USE lpp.lpp_dma_pkg.ALL;
38 38 USE lpp.general_purpose.ALL;
39 39 --USE lpp.lpp_waveform_pkg.ALL;
40 40 LIBRARY techmap;
41 41 USE techmap.gencomp.ALL;
42 42
43 43
44 44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
45 45 GENERIC (
46 46 hindex : INTEGER := 2;
47 47 vendorid : IN INTEGER := 0;
48 48 deviceid : IN INTEGER := 0;
49 49 version : IN INTEGER := 0
50 50 );
51 51 PORT (
52 52 clk : IN STD_LOGIC;
53 53 rstn : IN STD_LOGIC;
54 54
55 55 -- AMBA AHB Master Interface
56 56 AHB_Master_In : IN AHB_Mst_In_Type;
57 57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 58
59 59 -- FIFO Interface
60 60 ren : OUT STD_LOGIC;
61 61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62
63 63 -- Controls
64 64 send : IN STD_LOGIC;
65 65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
66 66 done : OUT STD_LOGIC;
67 67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
68 68 );
69 69 END;
70 70
71 71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
72 72
73 73 CONSTANT HConfig : AHB_Config_Type := (
74 74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
75 75 OTHERS => (OTHERS => '0'));
76 76
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 78 SIGNAL state : AHB_DMA_FSM_STATE;
79 79
80 80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
82 82
83 83 SIGNAL data_window : STD_LOGIC;
84 84 SIGNAL ctrl_window : STD_LOGIC;
85 85
86 86 SIGNAL bus_request : STD_LOGIC;
87 87 SIGNAL bus_lock : STD_LOGIC;
88
89 SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
90
91 SIGNAL HREADY_pre : STD_LOGIC;
92 SIGNAL HREADY_falling : STD_LOGIC;
93
94 SIGNAL inhib_ren : STD_LOGIC;
88 95
89 96 BEGIN
90 97
91 98 -----------------------------------------------------------------------------
92 99 AHB_Master_Out.HCONFIG <= HConfig;
93 100 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
94 101 AHB_Master_Out.HINDEX <= hindex;
95 102 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
96 103 AHB_Master_Out.HIRQ <= (OTHERS => '0');
97 104 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
98 105 AHB_Master_Out.HWRITE <= '1';
99 106
100 107 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
101 108
102 109 --AHB_Master_Out.HBUSREQ <= bus_request;
103 110 --AHB_Master_Out.HLOCK <= data_window;
104 111
105 112 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
106 113 -- '1' WHEN ctrl_window = '1' ELSE
107 114 -- '0';
108 115
109 116 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
110 117 -- '1' WHEN ctrl_window = '1' ELSE '0';
111 118
112 119 -----------------------------------------------------------------------------
113 120 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
115
121 AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
122
116 123 -----------------------------------------------------------------------------
117 124 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
118 125 --ren <= NOT beat;
119 126 -----------------------------------------------------------------------------
127
128 HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1';
129
130
120 131 PROCESS (clk, rstn)
121 132 BEGIN -- PROCESS
122 133 IF rstn = '0' THEN -- asynchronous reset (active low)
123 134 state <= IDLE;
124 135 done <= '0';
136 ren <= '1';
125 137 address_counter_reg <= (OTHERS => '0');
126 138 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
127 139 AHB_Master_Out.HBUSREQ <= '0';
128 140 AHB_Master_Out.HLOCK <= '0';
141
142 data_reg <= (OTHERS => '0');
143
144 HREADY_pre <= '0';
145 inhib_ren <= '0';
129 146 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
147 HREADY_pre <= AHB_Master_In.HREADY;
148
149 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
150 data_reg <= data;
151 END IF;
152
130 153 done <= '0';
154 ren <= '1';
155 inhib_ren <= '0';
131 156 CASE state IS
132 157 WHEN IDLE =>
133 158 AHB_Master_Out.HBUSREQ <= '0';
134 159 AHB_Master_Out.HLOCK <= '0';
135 160 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
136 161 address_counter_reg <= (OTHERS => '0');
137 162 IF send = '1' THEN
138 AHB_Master_Out.HBUSREQ <= '1';
139 AHB_Master_Out.HLOCK <= '1';
140 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
141 state <= s_ARBITER;
163 state <= s_INIT_TRANS;
142 164 END IF;
143
165
166 WHEN s_INIT_TRANS =>
167 AHB_Master_Out.HBUSREQ <= '1';
168 AHB_Master_Out.HLOCK <= '1';
169 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
170 state <= s_ARBITER;
171
144 172 WHEN s_ARBITER =>
145 173 AHB_Master_Out.HBUSREQ <= '1';
146 174 AHB_Master_Out.HLOCK <= '1';
147 175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
148 176 address_counter_reg <= (OTHERS => '0');
149 177
150 IF AHB_Master_In.HGRANT(hindex) = '1' THEN
178 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
151 179 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
152 180 state <= s_CTRL;
153 181 END IF;
154 182
155 183 WHEN s_CTRL =>
184 inhib_ren <= '1';
156 185 AHB_Master_Out.HBUSREQ <= '1';
157 186 AHB_Master_Out.HLOCK <= '1';
158 187 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
159 188 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
160 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
189 --AHB_Master_Out.HTRANS <= HTRANS_SEQ;
161 190 state <= s_CTRL_DATA;
191 --ren <= '0';
162 192 END IF;
163 193
164 194 WHEN s_CTRL_DATA =>
165 195 AHB_Master_Out.HBUSREQ <= '1';
166 196 AHB_Master_Out.HLOCK <= '1';
167 197 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
168 198 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
169 199 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
170 200 END IF;
171 201
172 202 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
173 203 AHB_Master_Out.HBUSREQ <= '0';
174 204 AHB_Master_Out.HLOCK <= '1';--'0';
175 205 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
176 206 state <= s_DATA;
177 207 END IF;
178 208
209 ren <= HREADY_falling;
210
211 --IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
212 -- ren <= '0';
213 --END IF;
214
215
179 216 WHEN s_DATA =>
217 ren <= HREADY_falling;
218
180 219 AHB_Master_Out.HBUSREQ <= '0';
181 AHB_Master_Out.HLOCK <= '0';
220 --AHB_Master_Out.HLOCK <= '0';
182 221 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
183 222 IF AHB_Master_In.HREADY = '1' THEN
223 AHB_Master_Out.HLOCK <= '0';
184 224 state <= IDLE;
185 225 done <= '1';
186 226 END IF;
187 227
188 228 WHEN OTHERS => NULL;
189 229 END CASE;
190 230 END IF;
191 231 END PROCESS;
192 232
193 233 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
194 234 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
195 235 -----------------------------------------------------------------------------
196 ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
236
237
238 --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
197 239
198 240 -----------------------------------------------------------------------------
199 241 --PROCESS (clk, rstn)
200 242 --BEGIN -- PROCESS
201 243 -- IF rstn = '0' THEN -- asynchronous reset (active low)
202 244 -- address_counter_reg <= (OTHERS => '0');
203 245 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
204 246 -- address_counter_reg <= address_counter;
205 247 -- END IF;
206 248 --END PROCESS;
207 249
208 250 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
209 251 -- address_counter_reg;
210 252 -----------------------------------------------------------------------------
211 253
212 254
213 255 END Behavioral;
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