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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
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29 | 29 | USE techmap.gencomp.ALL; |
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30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.sim.ALL; |
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32 | 32 | USE gaisler.memctrl.ALL; |
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33 | 33 | USE gaisler.leon3.ALL; |
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34 | 34 | USE gaisler.uart.ALL; |
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35 | 35 | USE gaisler.misc.ALL; |
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36 | 36 | USE gaisler.spacewire.ALL; |
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37 | 37 | LIBRARY esa; |
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38 | 38 | USE esa.memoryctrl.ALL; |
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39 | 39 | LIBRARY lpp; |
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40 | 40 | USE lpp.lpp_memory.ALL; |
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41 | 41 | USE lpp.lpp_ad_conv.ALL; |
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42 | 42 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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43 | 43 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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44 | 44 | USE lpp.iir_filter.ALL; |
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45 | 45 | USE lpp.general_purpose.ALL; |
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46 | 46 | USE lpp.lpp_lfr_management.ALL; |
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47 | 47 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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48 | 48 | USE lpp.lpp_bootloader_pkg.ALL; |
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49 | 49 | |
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50 | 50 | --library proasic3l; |
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51 | 51 | --use proasic3l.all; |
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52 | 52 | |
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53 | 53 | ENTITY LFR_EQM IS |
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54 | 54 | GENERIC ( |
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55 | 55 | Mem_use : INTEGER := use_RAM; |
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56 | 56 | USE_BOOTLOADER : INTEGER := 0 |
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57 | 57 | ); |
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58 | 58 | |
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59 | 59 | PORT ( |
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60 | 60 | clk50MHz : IN STD_ULOGIC; |
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61 | 61 | clk49_152MHz : IN STD_ULOGIC; |
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62 | 62 | reset : IN STD_ULOGIC; |
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63 | 63 | |
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64 | 64 | -- TAG -------------------------------------------------------------------- |
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65 | 65 | TAG1 : IN STD_ULOGIC; -- DSU rx data |
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66 | 66 | TAG3 : OUT STD_ULOGIC; -- DSU tx data |
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67 | 67 | -- UART APB --------------------------------------------------------------- |
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68 | 68 | TAG2 : IN STD_ULOGIC; -- UART1 rx data |
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69 | 69 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
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70 | 70 | -- RAM -------------------------------------------------------------------- |
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71 | 71 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); |
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72 | 72 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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73 | 73 | |
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74 | 74 | nSRAM_MBE : INOUT STD_LOGIC; -- new |
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75 | 75 | nSRAM_E1 : OUT STD_LOGIC; -- new |
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76 | 76 | nSRAM_E2 : OUT STD_LOGIC; -- new |
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77 | 77 | -- nSRAM_SCRUB : OUT STD_LOGIC; -- new |
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78 | 78 | nSRAM_W : OUT STD_LOGIC; -- new |
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79 | 79 | nSRAM_G : OUT STD_LOGIC; -- new |
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80 | 80 | nSRAM_BUSY : IN STD_LOGIC; -- new |
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81 | 81 | -- SPW -------------------------------------------------------------------- |
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82 | 82 | spw1_en : OUT STD_LOGIC; -- new |
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83 | 83 | spw1_din : IN STD_LOGIC; |
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84 | 84 | spw1_sin : IN STD_LOGIC; |
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85 | 85 | spw1_dout : OUT STD_LOGIC; |
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86 | 86 | spw1_sout : OUT STD_LOGIC; |
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87 | 87 | spw2_en : OUT STD_LOGIC; -- new |
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88 | 88 | spw2_din : IN STD_LOGIC; |
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89 | 89 | spw2_sin : IN STD_LOGIC; |
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90 | 90 | spw2_dout : OUT STD_LOGIC; |
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91 | 91 | spw2_sout : OUT STD_LOGIC; |
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92 | 92 | -- ADC -------------------------------------------------------------------- |
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93 | 93 | bias_fail_sw : OUT STD_LOGIC; |
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94 | 94 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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95 | 95 | ADC_smpclk : OUT STD_LOGIC; |
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96 | 96 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
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97 | 97 | -- DAC -------------------------------------------------------------------- |
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98 | 98 | DAC_SDO : OUT STD_LOGIC; |
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99 | 99 | DAC_SCK : OUT STD_LOGIC; |
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100 | 100 | DAC_SYNC : OUT STD_LOGIC; |
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101 | 101 | DAC_CAL_EN : OUT STD_LOGIC; |
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102 | 102 | -- HK --------------------------------------------------------------------- |
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103 | 103 | HK_smpclk : OUT STD_LOGIC; |
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104 | 104 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
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105 | 105 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
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106 | 106 | --------------------------------------------------------------------------- |
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107 | 107 | TAG8 : OUT STD_LOGIC |
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108 | 108 | ); |
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109 | 109 | |
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110 | 110 | END LFR_EQM; |
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111 | 111 | |
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112 | 112 | |
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113 | 113 | ARCHITECTURE beh OF LFR_EQM IS |
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114 | 114 | |
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115 | 115 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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116 | 116 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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117 | 117 | ----------------------------------------------------------------------------- |
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118 | 118 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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119 | 119 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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120 | 120 | |
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121 | 121 | -- CONSTANTS |
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122 | 122 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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123 | 123 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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124 | 124 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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125 | 125 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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126 | 126 | |
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127 | 127 | SIGNAL apbi_ext : apb_slv_in_type; |
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128 | 128 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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129 | 129 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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130 | 130 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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131 | 131 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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132 | 132 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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133 | 133 | |
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134 | 134 | -- Spacewire signals |
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135 | 135 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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136 | 136 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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137 | 137 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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138 | 138 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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139 | 139 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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140 | 140 | SIGNAL spw_clk : STD_LOGIC; |
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141 | 141 | SIGNAL swni : grspw_in_type; |
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142 | 142 | SIGNAL swno : grspw_out_type; |
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143 | 143 | |
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144 | 144 | --GPIO |
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145 | 145 | SIGNAL gpioi : gpio_in_type; |
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146 | 146 | SIGNAL gpioo : gpio_out_type; |
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147 | 147 | |
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148 | 148 | -- AD Converter ADS7886 |
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149 | 149 | SIGNAL sample : Samples14v(8 DOWNTO 0); |
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150 | 150 | SIGNAL sample_s : Samples(8 DOWNTO 0); |
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151 | 151 | SIGNAL sample_val : STD_LOGIC; |
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152 | 152 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); |
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153 | 153 | |
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154 | 154 | ----------------------------------------------------------------------------- |
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155 | 155 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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156 | 156 | |
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157 | 157 | ----------------------------------------------------------------------------- |
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158 | 158 | SIGNAL rstn_25 : STD_LOGIC; |
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159 | 159 | SIGNAL rstn_24 : STD_LOGIC; |
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160 | 160 | |
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161 | 161 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
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162 | 162 | SIGNAL LFR_rstn : STD_LOGIC; |
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163 | 163 | |
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164 | 164 | SIGNAL ADC_smpclk_s : STD_LOGIC; |
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165 | 165 | |
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166 | 166 | SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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167 | 167 | |
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168 | 168 | SIGNAL clk50MHz_int : STD_LOGIC := '0'; |
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169 | 169 | SIGNAL clk_25_int : STD_LOGIC := '0'; |
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170 | 170 | |
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171 | 171 | component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; |
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172 | ||
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172 | ||
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173 | SIGNAL rstn_50 : STD_LOGIC; | |
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174 | SIGNAL clk_lock : STD_LOGIC; | |
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175 | SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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176 | SIGNAL nSRAM_BUSY_reg : STD_LOGIC; | |
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173 | 177 | BEGIN -- beh |
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174 | 178 | |
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175 | 179 | ----------------------------------------------------------------------------- |
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180 | -- CLK_LOCK | |
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181 | ----------------------------------------------------------------------------- | |
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182 | rst_gen_global : rstgen PORT MAP (reset, clk_50, '1', rstn_50, OPEN); | |
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183 | ||
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184 | PROCESS (clk50MHz_int, rstn_50) | |
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185 | BEGIN -- PROCESS | |
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186 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) | |
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187 | clk_lock <= '0'; | |
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188 | clk_busy_counter <= (OTHERS => '0'); | |
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189 | nSRAM_BUSY_reg <= '0'; | |
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190 | ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge | |
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191 | nSRAM_BUSY_reg <= nSRAM_BUSY; | |
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192 | IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN | |
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193 | IF clk_busy_counter = "1111" THEN | |
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194 | clk_lock = '1'; | |
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195 | ELSE | |
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196 | clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); | |
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197 | END IF; | |
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198 | END IF; | |
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199 | END IF; | |
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200 | END PROCESS; | |
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201 | ||
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202 | ----------------------------------------------------------------------------- | |
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176 | 203 | -- CLK |
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177 | 204 | ----------------------------------------------------------------------------- |
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178 |
rst_domain25 : rstgen PORT MAP (reset, clk_25, |
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179 |
rst_domain24 : rstgen PORT MAP (reset, clk_24, |
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205 | rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); | |
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206 | rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); | |
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180 | 207 | |
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181 | 208 | --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); |
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182 | 209 | clk50MHz_int <= clk50MHz; |
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183 | 210 | |
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184 | 211 | PROCESS(clk50MHz_int) |
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185 | 212 | BEGIN |
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186 | 213 | IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN |
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187 | 214 | --clk_25_int <= NOT clk_25_int; |
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188 | 215 | clk_25 <= NOT clk_25; |
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189 | 216 | END IF; |
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190 | 217 | END PROCESS; |
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191 | 218 | --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); |
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192 | 219 | |
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193 | 220 | PROCESS(clk49_152MHz) |
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194 | 221 | BEGIN |
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195 | 222 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
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196 | 223 | clk_24 <= NOT clk_24; |
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197 | 224 | END IF; |
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198 | 225 | END PROCESS; |
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199 | 226 | |
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200 | 227 | ----------------------------------------------------------------------------- |
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201 | 228 | -- |
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202 | 229 | leon3_soc_1 : leon3_soc |
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203 | 230 | GENERIC MAP ( |
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204 | 231 | fabtech => apa3e, |
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205 | 232 | memtech => apa3e, |
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206 | 233 | padtech => inferred, |
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207 | 234 | clktech => inferred, |
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208 | 235 | disas => 0, |
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209 | 236 | dbguart => 0, |
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210 | 237 | pclow => 2, |
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211 | 238 | clk_freq => 25000, |
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212 | 239 | IS_RADHARD => 0, |
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213 | 240 | NB_CPU => 1, |
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214 | 241 | ENABLE_FPU => 1, |
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215 | 242 | FPU_NETLIST => 0, |
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216 | 243 | ENABLE_DSU => 1, |
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217 | 244 | ENABLE_AHB_UART => 1, |
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218 | 245 | ENABLE_APB_UART => 1, |
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219 | 246 | ENABLE_IRQMP => 1, |
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220 | 247 | ENABLE_GPT => 1, |
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221 | 248 | NB_AHB_MASTER => NB_AHB_MASTER, |
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222 | 249 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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223 | 250 | NB_APB_SLAVE => NB_APB_SLAVE, |
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224 | 251 | ADDRESS_SIZE => 19, |
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225 | 252 | USES_IAP_MEMCTRLR => 1, |
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226 | 253 | BYPASS_EDAC_MEMCTRLR => '0', |
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227 | 254 | SRBANKSZ => 8) |
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228 | 255 | PORT MAP ( |
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229 | 256 | clk => clk_25, |
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230 | 257 | reset => rstn_25, |
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231 | 258 | errorn => OPEN, |
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232 | 259 | |
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233 | 260 | ahbrxd => TAG1, |
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234 | 261 | ahbtxd => TAG3, |
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235 | 262 | urxd1 => TAG2, |
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236 | 263 | utxd1 => TAG4, |
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237 | 264 | |
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238 | 265 | address => address, |
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239 | 266 | data => data, |
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240 | 267 | nSRAM_BE0 => OPEN, |
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241 | 268 | nSRAM_BE1 => OPEN, |
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242 | 269 | nSRAM_BE2 => OPEN, |
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243 | 270 | nSRAM_BE3 => OPEN, |
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244 | 271 | nSRAM_WE => nSRAM_W, |
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245 | 272 | nSRAM_CE => nSRAM_CE, |
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246 | 273 | nSRAM_OE => nSRAM_G, |
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247 | 274 | nSRAM_READY => nSRAM_BUSY, |
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248 | 275 | SRAM_MBE => nSRAM_MBE, |
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249 | 276 | |
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250 | 277 | apbi_ext => apbi_ext, |
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251 | 278 | apbo_ext => apbo_ext, |
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252 | 279 | ahbi_s_ext => ahbi_s_ext, |
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253 | 280 | ahbo_s_ext => ahbo_s_ext, |
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254 | 281 | ahbi_m_ext => ahbi_m_ext, |
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255 | 282 | ahbo_m_ext => ahbo_m_ext); |
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256 | 283 | |
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257 | 284 | |
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258 | 285 | nSRAM_E1 <= nSRAM_CE(0); |
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259 | 286 | nSRAM_E2 <= nSRAM_CE(1); |
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260 | 287 | |
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261 | 288 | ------------------------------------------------------------------------------- |
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262 | 289 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
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263 | 290 | ------------------------------------------------------------------------------- |
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264 | 291 | apb_lfr_management_1 : apb_lfr_management |
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265 | 292 | GENERIC MAP ( |
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266 | 293 | tech => apa3l, |
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267 | 294 | pindex => 6, |
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268 | 295 | paddr => 6, |
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269 | 296 | pmask => 16#fff#, |
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270 | 297 | --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
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271 | 298 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
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272 | 299 | PORT MAP ( |
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273 | 300 | clk25MHz => clk_25, |
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274 | 301 | resetn_25MHz => rstn_25, -- TODO |
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275 | 302 | --clk24_576MHz => clk_24, -- 49.152MHz/2 |
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276 | 303 | --resetn_24_576MHz => rstn_24, -- TODO |
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277 | 304 | |
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278 | 305 | grspw_tick => swno.tickout, |
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279 | 306 | apbi => apbi_ext, |
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280 | 307 | apbo => apbo_ext(6), |
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281 | 308 | |
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282 | 309 | HK_sample => sample_s(8), |
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283 | 310 | HK_val => sample_val, |
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284 | 311 | HK_sel => HK_SEL, |
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285 | 312 | |
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286 | 313 | DAC_SDO => DAC_SDO, |
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287 | 314 | DAC_SCK => DAC_SCK, |
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288 | 315 | DAC_SYNC => DAC_SYNC, |
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289 | 316 | DAC_CAL_EN => DAC_CAL_EN, |
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290 | 317 | |
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291 | 318 | coarse_time => coarse_time, |
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292 | 319 | fine_time => fine_time, |
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293 | 320 | LFR_soft_rstn => LFR_soft_rstn |
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294 | 321 | ); |
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295 | 322 | |
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296 | 323 | ----------------------------------------------------------------------- |
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297 | 324 | --- SpaceWire -------------------------------------------------------- |
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298 | 325 | ----------------------------------------------------------------------- |
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299 | 326 | |
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300 | 327 | ------------------------------------------------------------------------------ |
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301 | 328 | -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ |
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302 | 329 | ------------------------------------------------------------------------------ |
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303 | 330 | spw1_en <= '1'; |
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304 | 331 | spw2_en <= '1'; |
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305 | 332 | ------------------------------------------------------------------------------ |
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306 | 333 | -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ |
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307 | 334 | ------------------------------------------------------------------------------ |
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308 | 335 | |
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309 | 336 | --spw_clk <= clk50MHz; |
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310 | 337 | --spw_rxtxclk <= spw_clk; |
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311 | 338 | --spw_rxclkn <= NOT spw_rxtxclk; |
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312 | 339 | |
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313 | 340 | -- PADS for SPW1 |
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314 | 341 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
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315 | 342 | PORT MAP (spw1_din, dtmp(0)); |
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316 | 343 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
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317 | 344 | PORT MAP (spw1_sin, stmp(0)); |
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318 | 345 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
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319 | 346 | PORT MAP (spw1_dout, swno.d(0)); |
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320 | 347 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
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321 | 348 | PORT MAP (spw1_sout, swno.s(0)); |
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322 | 349 | -- PADS FOR SPW2 |
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323 | 350 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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324 | 351 | PORT MAP (spw2_din, dtmp(1)); |
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325 | 352 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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326 | 353 | PORT MAP (spw2_sin, stmp(1)); |
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327 | 354 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
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328 | 355 | PORT MAP (spw2_dout, swno.d(1)); |
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329 | 356 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
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330 | 357 | PORT MAP (spw2_sout, swno.s(1)); |
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331 | 358 | |
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332 | 359 | -- GRSPW PHY |
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333 | 360 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
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334 | 361 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
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335 | 362 | spw_phy0 : grspw_phy |
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336 | 363 | GENERIC MAP( |
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337 | 364 | tech => apa3l, |
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338 | 365 | rxclkbuftype => 1, |
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339 | 366 | scantest => 0) |
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340 | 367 | PORT MAP( |
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341 | 368 | rxrst => swno.rxrst, |
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342 | 369 | di => dtmp(j), |
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343 | 370 | si => stmp(j), |
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344 | 371 | rxclko => spw_rxclk(j), |
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345 | 372 | do => swni.d(j), |
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346 | 373 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
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347 | 374 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
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348 | 375 | END GENERATE spw_inputloop; |
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349 | 376 | |
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350 | 377 | -- SPW core |
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351 | 378 | sw0 : grspwm GENERIC MAP( |
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352 | 379 | tech => apa3l, |
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353 | 380 | hindex => 1, |
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354 | 381 | pindex => 5, |
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355 | 382 | paddr => 5, |
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356 | 383 | pirq => 11, |
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357 | 384 | sysfreq => 25000, -- CPU_FREQ |
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358 | 385 | rmap => 1, |
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359 | 386 | rmapcrc => 1, |
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360 | 387 | fifosize1 => 16, |
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361 | 388 | fifosize2 => 16, |
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362 | 389 | rxclkbuftype => 1, |
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363 | 390 | rxunaligned => 0, |
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364 | 391 | rmapbufs => 4, |
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365 | 392 | ft => 0, |
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366 | 393 | netlist => 0, |
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367 | 394 | ports => 2, |
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368 | 395 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
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369 | 396 | memtech => apa3l, |
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370 | 397 | destkey => 2, |
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371 | 398 | spwcore => 1 |
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372 | 399 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
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373 | 400 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
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374 | 401 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
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375 | 402 | ) |
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376 | 403 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
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377 | 404 | spw_rxclk(1), |
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378 | 405 | clk50MHz_int, |
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379 | 406 | clk50MHz_int, |
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380 | 407 | -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, |
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381 | 408 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
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382 | 409 | swni, swno); |
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383 | 410 | |
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384 | 411 | swni.tickin <= '0'; |
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385 | 412 | swni.rmapen <= '1'; |
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386 | 413 | swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz |
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387 | 414 | swni.tickinraw <= '0'; |
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388 | 415 | swni.timein <= (OTHERS => '0'); |
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389 | 416 | swni.dcrstval <= (OTHERS => '0'); |
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390 | 417 | swni.timerrstval <= (OTHERS => '0'); |
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391 | 418 | |
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392 | 419 | ------------------------------------------------------------------------------- |
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393 | 420 | -- LFR ------------------------------------------------------------------------ |
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394 | 421 | ------------------------------------------------------------------------------- |
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395 | 422 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
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396 | 423 | |
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397 | 424 | lpp_lfr_1 : lpp_lfr |
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398 | 425 | GENERIC MAP ( |
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399 | 426 | Mem_use => Mem_use, |
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400 | 427 | nb_data_by_buffer_size => 32, |
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401 | 428 | --nb_word_by_buffer_size => 30, |
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402 | 429 | nb_snapshot_param_size => 32, |
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403 | 430 | delta_vector_size => 32, |
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404 | 431 | delta_vector_size_f0_2 => 7, -- log2(96) |
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405 | 432 | pindex => 15, |
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406 | 433 | paddr => 15, |
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407 | 434 | pmask => 16#fff#, |
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408 | 435 | pirq_ms => 6, |
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409 | 436 | pirq_wfp => 14, |
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410 | 437 | hindex => 2, |
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411 | 438 | top_lfr_version => X"020147") -- aa.bb.cc version |
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412 | 439 | -- AA : BOARD NUMBER |
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413 | 440 | -- 0 => MINI_LFR |
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414 | 441 | -- 1 => EM |
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415 | 442 | -- 2 => EQM (with A3PE3000) |
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416 | 443 | PORT MAP ( |
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417 | 444 | clk => clk_25, |
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418 | 445 | rstn => LFR_rstn, |
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419 | 446 | sample_B => sample_s(2 DOWNTO 0), |
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420 | 447 | sample_E => sample_s(7 DOWNTO 3), |
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421 | 448 | sample_val => sample_val, |
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422 | 449 | apbi => apbi_ext, |
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423 | 450 | apbo => apbo_ext(15), |
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424 | 451 | ahbi => ahbi_m_ext, |
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425 | 452 | ahbo => ahbo_m_ext(2), |
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426 | 453 | coarse_time => coarse_time, |
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427 | 454 | fine_time => fine_time, |
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428 | 455 | data_shaping_BW => bias_fail_sw, |
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429 | 456 | debug_vector => OPEN, |
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430 | 457 | debug_vector_ms => OPEN); --, |
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431 | 458 | --observation_vector_0 => OPEN, |
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432 | 459 | --observation_vector_1 => OPEN, |
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433 | 460 | --observation_reg => observation_reg); |
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434 | 461 | |
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435 | 462 | |
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436 | 463 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
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437 | 464 | sample_s(I) <= sample(I) & '0' & '0'; |
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438 | 465 | END GENERATE all_sample; |
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439 | 466 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); |
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440 | 467 | |
|
441 | 468 | ----------------------------------------------------------------------------- |
|
442 | 469 | -- |
|
443 | 470 | ----------------------------------------------------------------------------- |
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444 | 471 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter |
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445 | 472 | GENERIC MAP ( |
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446 | 473 | ChanelCount => 9, |
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447 | 474 | ncycle_cnv_high => 13, |
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448 | 475 | ncycle_cnv => 25, |
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449 | 476 | FILTER_ENABLED => 16#FF#) |
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450 | 477 | PORT MAP ( |
|
451 | 478 | cnv_clk => clk_24, |
|
452 | 479 | cnv_rstn => rstn_24, |
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453 | 480 | cnv => ADC_smpclk_s, |
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454 | 481 | clk => clk_25, |
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455 | 482 | rstn => rstn_25, |
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456 | 483 | ADC_data => ADC_data, |
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457 | 484 | ADC_nOE => ADC_OEB_bar_CH_s, |
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458 | 485 | sample => sample, |
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459 | 486 | sample_val => sample_val); |
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460 | 487 | |
|
461 | 488 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); |
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462 | 489 | |
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463 | 490 | ADC_smpclk <= ADC_smpclk_s; |
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464 | 491 | HK_smpclk <= ADC_smpclk_s; |
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465 | 492 | |
|
466 | 493 | TAG8 <= nSRAM_BUSY; |
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467 | 494 | |
|
468 | 495 | ----------------------------------------------------------------------------- |
|
469 | 496 | -- HK |
|
470 | 497 | ----------------------------------------------------------------------------- |
|
471 | 498 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); |
|
472 | 499 | |
|
473 | 500 | ----------------------------------------------------------------------------- |
|
474 | 501 | -- |
|
475 | 502 | ----------------------------------------------------------------------------- |
|
476 | 503 | inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE |
|
477 | 504 | lpp_bootloader_1: lpp_bootloader |
|
478 | 505 | GENERIC MAP ( |
|
479 | 506 | pindex => 13, |
|
480 | 507 | paddr => 13, |
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481 | 508 | pmask => 16#fff#, |
|
482 | 509 | hindex => 3, |
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483 | 510 | haddr => 0, |
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484 | 511 | hmask => 16#fff#) |
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485 | 512 | PORT MAP ( |
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486 | 513 | HCLK => clk_25, |
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487 | 514 | HRESETn => rstn_25, |
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488 | 515 | apbi => apbi_ext, |
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489 | 516 | apbo => apbo_ext(13), |
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490 | 517 | ahbsi => ahbi_s_ext, |
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491 | 518 | ahbso => ahbo_s_ext(3)); |
|
492 | 519 | END GENERATE inst_bootloader; |
|
493 | 520 | END beh; |
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