@@ -0,0 +1,8 | |||
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1 | iir_filter.vhd | |
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2 | FILTERcfg.vhd | |
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3 | RAM.vhd | |
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4 | RAM_CEL.vhd | |
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5 | RAM_CTRLR_v2.vhd | |
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6 | IIR_CEL_CTRLR_v2_CONTROL.vhd | |
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7 | IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |
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8 | IIR_CEL_CTRLR_v2.vhd |
@@ -0,0 +1,9 | |||
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1 | APB_FFT.vhd | |
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2 | APB_FFT_half.vhd | |
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3 | Driver_FFT.vhd | |
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4 | FFT.vhd | |
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5 | FFTamont.vhd | |
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6 | FFTaval.vhd | |
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7 | Flag_Extremum.vhd | |
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8 | Linker_FFT.vhd | |
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9 | lpp_fft.vhd |
@@ -0,0 +1,13 | |||
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1 | ALU_Driver.vhd | |
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2 | APB_Matrix.vhd | |
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3 | Dispatch.vhd | |
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4 | DriveInputs.vhd | |
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5 | GetResult.vhd | |
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6 | MatriceSpectrale.vhd | |
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7 | Matrix.vhd | |
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8 | SpectralMatrix.vhd | |
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9 | Starter.vhd | |
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10 | TopMatrix_PDR.vhd | |
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11 | TopSpecMatrix.vhd | |
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12 | Top_MatrixSpec.vhd | |
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13 | lpp_matrix.vhd |
@@ -0,0 +1,7 | |||
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1 | lpp_memory.vhd | |
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2 | lpp_FIFO.vhd | |
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3 | APB_FIFO.vhd | |
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4 | Bridge.vhd | |
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5 | SSRAM_plugin.vhd | |
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6 | lppFIFOx5.vhd | |
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7 | lppFIFOxN.vhd |
@@ -607,17 +607,6 BEGIN | |||
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607 | 607 | header_val => header_val, |
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608 | 608 | header_ack => header_ack); |
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609 | 609 | |
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610 | --fifo_latency_correction_1 : fifo_latency_correction | |
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611 | -- PORT MAP ( | |
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612 | -- HCLK => clkm, | |
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613 | -- HRESETn => resetn, | |
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614 | -- fifo_data => fifo_data, | |
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615 | -- fifo_empty => fifo_empty, | |
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616 | -- fifo_ren => fifo_ren, | |
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617 | -- dma_data => dma_data, | |
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618 | -- dma_empty => dma_empty, | |
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619 | -- dma_ren => dma_ren); | |
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620 | ||
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621 | 610 | fifo_test_dma_1 : fifo_test_dma |
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622 | 611 | GENERIC MAP ( |
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623 | 612 | tech => fabtech, |
@@ -1,21 +1,21 | |||
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1 | 1 | ./amba_lcd_16x2_ctrlr |
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2 | ./dsp/iir_filter | |
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3 | ./dsp/lpp_downsampling | |
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4 | ./dsp/lpp_fft | |
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5 | 2 | ./general_purpose |
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6 | 3 | ./general_purpose/lpp_AMR |
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7 | 4 | ./general_purpose/lpp_balise |
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8 | 5 | ./general_purpose/lpp_delay |
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6 | ./lpp_amba | |
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7 | ./dsp/iir_filter | |
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8 | ./dsp/lpp_downsampling | |
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9 | ./dsp/lpp_fft | |
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9 | 10 | ./lfr_time_management |
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10 | 11 | ./lpp_ad_Conv |
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11 | ./lpp_amba | |
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12 | 12 | ./lpp_bootloader |
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13 | 13 | ./lpp_cna |
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14 | 14 | ./lpp_demux |
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15 | ./lpp_dma | |
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16 | 15 | ./lpp_matrix |
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17 | 16 | ./lpp_memory |
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18 | ./lpp_top_lfr | |
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17 | ./lpp_dma | |
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19 | 18 | ./lpp_uart |
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20 | 19 | ./lpp_usb |
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21 | 20 | ./lpp_waveform |
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21 | ./lpp_top_lfr |
@@ -1,3 +1,4 | |||
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1 | general_purpose.vhd | |
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1 | 2 | ADDRcntr.vhd |
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2 | 3 | ALU.vhd |
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3 | 4 | Adder.vhd |
@@ -14,5 +15,4 Multiplier.vhd | |||
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14 | 15 | REG.vhd |
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15 | 16 | SYNC_FF.vhd |
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16 | 17 | Shifter.vhd |
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17 | general_purpose.vhd | |
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18 | 18 | TwoComplementer.vhd |
@@ -36,7 +36,7 ENTITY apb_lfr_time_management IS | |||
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36 | 36 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR |
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37 | 37 | pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used |
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38 | 38 | masterclk : INTEGER := 25000000; --! master clock in Hz |
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39 |
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39 | timeclk : INTEGER := 49152000; --! other clock in Hz | |
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40 | 40 | finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter |
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41 | 41 | ); |
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42 | 42 | |
@@ -62,7 +62,7 ARCHITECTURE Behavioral OF apb_lfr_time_ | |||
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62 | 62 | --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; |
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63 | 63 | CONSTANT pconfig : apb_config_type := ( |
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64 | 64 | --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), |
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65 |
0 => ahb_device_reg ( |
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65 | 0 => ahb_device_reg (VENDOR_LPP, 0, 0, REVISION, pirq), | |
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66 | 66 | 1 => apb_iobar(paddr, pmask)); |
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67 | 67 | |
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68 | 68 | TYPE apb_lfr_time_management_Reg IS RECORD |
@@ -80,20 +80,53 ARCHITECTURE Behavioral OF apb_lfr_time_ | |||
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80 | 80 | SIGNAL soft_tick : STD_LOGIC; |
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81 | 81 | SIGNAL reset_next_commutation : STD_LOGIC; |
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82 | 82 | |
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83 | SIGNAL irq1 : STD_LOGIC; | |
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84 | SIGNAL irq2 : STD_LOGIC; | |
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85 | ||
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83 | 86 | BEGIN |
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84 | 87 | |
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85 | 88 | lfrtimemanagement0 : lfr_time_management |
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86 | GENERIC MAP(masterclk => masterclk, timeclk => otherclk, finetimeclk => finetimeclk) | |
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87 | PORT MAP(master_clock => clk25MHz, time_clock => clk49_152MHz, resetn => resetn, | |
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88 | grspw_tick => grspw_tick, soft_tick => soft_tick, | |
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89 | coarse_time_load => r.coarse_time_load, coarse_time => r.coarse_time, fine_time => r.fine_time, | |
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90 | next_commutation => r.next_commutation, reset_next_commutation => reset_next_commutation, | |
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91 | irq1 => apbo.pirq(pirq), irq2 => apbo.pirq(pirq+1)); | |
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89 | GENERIC MAP( | |
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90 | masterclk => masterclk, | |
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91 | timeclk => timeclk, | |
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92 | finetimeclk => finetimeclk, | |
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93 | nb_clk_div_ticks => 1) | |
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94 | PORT MAP( | |
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95 | master_clock => clk25MHz, | |
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96 | time_clock => clk49_152MHz, | |
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97 | resetn => resetn, | |
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98 | grspw_tick => grspw_tick, | |
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99 | soft_tick => soft_tick, | |
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100 | coarse_time_load => r.coarse_time_load, | |
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101 | coarse_time => r.coarse_time, | |
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102 | fine_time => r.fine_time, | |
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103 | next_commutation => r.next_commutation, | |
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104 | reset_next_commutation => reset_next_commutation, | |
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105 | irq1 => irq1,--apbo.pirq(pirq), | |
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106 | irq2 => irq2);--apbo.pirq(pirq+1)); | |
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107 | ||
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108 | --apbo.pirq <= (OTHERS => '0'); | |
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109 | ||
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110 | all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE | |
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111 | irq1_gen: IF I = pirq GENERATE | |
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112 | apbo.pirq(I) <= irq1; | |
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113 | END GENERATE irq1_gen; | |
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114 | irq2_gen: IF I = pirq+1 GENERATE | |
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115 | apbo.pirq(I) <= irq2; | |
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116 | END GENERATE irq2_gen; | |
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117 | others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE | |
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118 | apbo.pirq(I) <= '0'; | |
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119 | END GENERATE others_irq; | |
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120 | END GENERATE all_irq_gen; | |
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121 | ||
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122 | --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE | |
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123 | --END GENERATE all_irq_sig; | |
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92 | 124 | |
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93 | 125 | PROCESS(resetn, clk25MHz, reset_next_commutation) |
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94 | 126 | BEGIN |
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95 | 127 | |
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96 | 128 | IF resetn = '0' THEN |
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129 | Rdata <= (OTHERS => '0'); | |
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97 | 130 | r.coarse_time_load <= x"80000000"; |
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98 | 131 | r.ctrl <= x"00000000"; |
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99 | 132 | r.next_commutation <= x"ffffffff"; |
@@ -164,11 +197,12 BEGIN | |||
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164 | 197 | END IF; |
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165 | 198 | |
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166 | 199 | END IF; |
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167 | apbo.pconfig <= pconfig; | |
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168 | 200 | END PROCESS; |
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169 | 201 | |
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170 |
apbo.prdata <= Rdata |
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202 | apbo.prdata <= Rdata ;--WHEN apbi.penable = '1'; | |
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171 | 203 | coarse_time <= r.coarse_time; |
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172 | 204 | fine_time <= r.fine_time; |
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205 | apbo.pconfig <= pconfig; | |
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206 | apbo.pindex <= pindex; | |
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173 | 207 | |
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174 | 208 | END Behavioral; |
@@ -1,3 +1,3 | |||
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1 |
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1 | lpp_lfr_time_management.vhd | |
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2 | 2 | lfr_time_management.vhd |
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3 |
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3 | apb_lfr_time_management.vhd |
@@ -80,6 +80,8 signal nCE3int : std_logic:='1'; | |||
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80 | 80 | Type stateT is (idle,st1,st2,st3,st4); |
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81 | 81 | signal state : stateT; |
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82 | 82 | |
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83 | SIGNAL nclk : STD_LOGIC; | |
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84 | ||
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83 | 85 | begin |
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84 | 86 | |
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85 | 87 | process(clk , mem_ctrlr_o.RAMSN(0)) |
@@ -102,8 +104,9 begin | |||
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102 | 104 | end if; |
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103 | 105 | end process; |
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104 | 106 | |
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107 | nclk <= NOT clk; | |
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105 | 108 | ssram_clk_pad : outpad generic map (tech => tech) |
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106 |
port map (SSRAM_CLK,n |
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109 | port map (SSRAM_CLK,nclk); | |
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107 | 110 | |
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108 | 111 | |
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109 | 112 | nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0); |
@@ -181,4 +184,4 MODE_pad : outpad generic map (tech => t | |||
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181 | 184 | ZZ_pad : outpad generic map (tech => tech) |
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182 | 185 | port map (ZZ, '0'); |
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183 | 186 | |
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184 | end architecture; No newline at end of file | |
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187 | end architecture; |
@@ -485,6 +485,10 BEGIN | |||
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485 | 485 | data_f2_in_valid => sample_f2_val, |
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486 | 486 | data_f3_in_valid => sample_f3_val); |
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487 | 487 | |
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488 | data_f0_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
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489 | data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
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490 | data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
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491 | data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
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488 | 492 | data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; |
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489 | 493 | data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; |
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490 | 494 | data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; |
@@ -495,4 +499,4 BEGIN | |||
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495 | 499 | sample_f2_wdata <= sample_f2_wdata_s; |
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496 | 500 | sample_f3_wdata <= sample_f3_wdata_s; |
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497 | 501 | |
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498 |
END tb; |
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502 | END tb; No newline at end of file |
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