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1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
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18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
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19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
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21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
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22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
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23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
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24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
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25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
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26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
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27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
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28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
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29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
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30 | LIBRARY gaisler; | |
31 | USE gaisler.memctrl.ALL; |
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31 | USE gaisler.memctrl.ALL; | |
32 | USE gaisler.leon3.ALL; |
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32 | USE gaisler.leon3.ALL; | |
33 | USE gaisler.uart.ALL; |
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33 | USE gaisler.uart.ALL; | |
34 | USE gaisler.misc.ALL; |
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34 | USE gaisler.misc.ALL; | |
35 | USE gaisler.spacewire.ALL; |
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35 | USE gaisler.spacewire.ALL; | |
36 | LIBRARY esa; |
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36 | LIBRARY esa; | |
37 | USE esa.memoryctrl.ALL; |
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37 | USE esa.memoryctrl.ALL; | |
38 | LIBRARY lpp; |
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38 | LIBRARY lpp; | |
39 | USE lpp.lpp_memory.ALL; |
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39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
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40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
43 | USE lpp.iir_filter.ALL; |
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43 | USE lpp.iir_filter.ALL; | |
44 | USE lpp.general_purpose.ALL; |
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44 | USE lpp.general_purpose.ALL; | |
45 | USE lpp.lpp_lfr_time_management.ALL; |
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45 | USE lpp.lpp_lfr_time_management.ALL; | |
46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
47 |
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47 | |||
48 | ENTITY MINI_LFR_top IS |
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48 | ENTITY MINI_LFR_top IS | |
49 |
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49 | |||
50 | PORT ( |
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50 | PORT ( | |
51 | clk_50 : IN STD_LOGIC; |
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51 | clk_50 : IN STD_LOGIC; | |
52 | clk_49 : IN STD_LOGIC; |
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52 | clk_49 : IN STD_LOGIC; | |
53 | reset : IN STD_LOGIC; |
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53 | reset : IN STD_LOGIC; | |
54 | --BPs |
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54 | --BPs | |
55 | BP0 : IN STD_LOGIC; |
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55 | BP0 : IN STD_LOGIC; | |
56 | BP1 : IN STD_LOGIC; |
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56 | BP1 : IN STD_LOGIC; | |
57 | --LEDs |
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57 | --LEDs | |
58 | LED0 : OUT STD_LOGIC; |
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58 | LED0 : OUT STD_LOGIC; | |
59 | LED1 : OUT STD_LOGIC; |
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59 | LED1 : OUT STD_LOGIC; | |
60 | LED2 : OUT STD_LOGIC; |
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60 | LED2 : OUT STD_LOGIC; | |
61 | --UARTs |
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61 | --UARTs | |
62 | TXD1 : IN STD_LOGIC; |
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62 | TXD1 : IN STD_LOGIC; | |
63 | RXD1 : OUT STD_LOGIC; |
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63 | RXD1 : OUT STD_LOGIC; | |
64 | nCTS1 : OUT STD_LOGIC; |
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64 | nCTS1 : OUT STD_LOGIC; | |
65 | nRTS1 : IN STD_LOGIC; |
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65 | nRTS1 : IN STD_LOGIC; | |
66 |
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66 | |||
67 | TXD2 : IN STD_LOGIC; |
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67 | TXD2 : IN STD_LOGIC; | |
68 | RXD2 : OUT STD_LOGIC; |
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68 | RXD2 : OUT STD_LOGIC; | |
69 | nCTS2 : OUT STD_LOGIC; |
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69 | nCTS2 : OUT STD_LOGIC; | |
70 | nDTR2 : IN STD_LOGIC; |
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70 | nDTR2 : IN STD_LOGIC; | |
71 | nRTS2 : IN STD_LOGIC; |
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71 | nRTS2 : IN STD_LOGIC; | |
72 | nDCD2 : OUT STD_LOGIC; |
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72 | nDCD2 : OUT STD_LOGIC; | |
73 |
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73 | |||
74 | --EXT CONNECTOR |
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74 | --EXT CONNECTOR | |
75 | IO0 : INOUT STD_LOGIC; |
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75 | IO0 : INOUT STD_LOGIC; | |
76 | IO1 : INOUT STD_LOGIC; |
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76 | IO1 : INOUT STD_LOGIC; | |
77 | IO2 : INOUT STD_LOGIC; |
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77 | IO2 : INOUT STD_LOGIC; | |
78 | IO3 : INOUT STD_LOGIC; |
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78 | IO3 : INOUT STD_LOGIC; | |
79 | IO4 : INOUT STD_LOGIC; |
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79 | IO4 : INOUT STD_LOGIC; | |
80 | IO5 : INOUT STD_LOGIC; |
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80 | IO5 : INOUT STD_LOGIC; | |
81 | IO6 : INOUT STD_LOGIC; |
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81 | IO6 : INOUT STD_LOGIC; | |
82 | IO7 : INOUT STD_LOGIC; |
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82 | IO7 : INOUT STD_LOGIC; | |
83 | IO8 : INOUT STD_LOGIC; |
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83 | IO8 : INOUT STD_LOGIC; | |
84 | IO9 : INOUT STD_LOGIC; |
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84 | IO9 : INOUT STD_LOGIC; | |
85 | IO10 : INOUT STD_LOGIC; |
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85 | IO10 : INOUT STD_LOGIC; | |
86 | IO11 : INOUT STD_LOGIC; |
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86 | IO11 : INOUT STD_LOGIC; | |
87 |
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87 | |||
88 | --SPACE WIRE |
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88 | --SPACE WIRE | |
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
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89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
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90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
91 | SPW_NOM_SIN : IN STD_LOGIC; |
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91 | SPW_NOM_SIN : IN STD_LOGIC; | |
92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
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94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
95 | SPW_RED_SIN : IN STD_LOGIC; |
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95 | SPW_RED_SIN : IN STD_LOGIC; | |
96 | SPW_RED_DOUT : OUT STD_LOGIC; |
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96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
97 | SPW_RED_SOUT : OUT STD_LOGIC; |
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97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
98 | -- MINI LFR ADC INPUTS |
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98 | -- MINI LFR ADC INPUTS | |
99 | ADC_nCS : OUT STD_LOGIC; |
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99 | ADC_nCS : OUT STD_LOGIC; | |
100 | ADC_CLK : OUT STD_LOGIC; |
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100 | ADC_CLK : OUT STD_LOGIC; | |
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
102 |
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102 | |||
103 | -- SRAM |
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103 | -- SRAM | |
104 | SRAM_nWE : OUT STD_LOGIC; |
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104 | SRAM_nWE : OUT STD_LOGIC; | |
105 | SRAM_CE : OUT STD_LOGIC; |
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105 | SRAM_CE : OUT STD_LOGIC; | |
106 | SRAM_nOE : OUT STD_LOGIC; |
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106 | SRAM_nOE : OUT STD_LOGIC; | |
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
110 | ); |
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110 | ); | |
111 |
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111 | |||
112 | END MINI_LFR_top; |
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112 | END MINI_LFR_top; | |
113 |
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113 | |||
114 |
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114 | |||
115 | ARCHITECTURE beh OF MINI_LFR_top IS |
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115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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118 | SIGNAL clk_24 : STD_LOGIC := '0'; | |
119 | ----------------------------------------------------------------------------- |
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119 | ----------------------------------------------------------------------------- | |
120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
122 | -- |
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122 | -- | |
123 | SIGNAL errorn : STD_LOGIC; |
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123 | SIGNAL errorn : STD_LOGIC; | |
124 | -- UART AHB --------------------------------------------------------------- |
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124 | -- UART AHB --------------------------------------------------------------- | |
125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
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125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
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126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
127 |
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127 | |||
128 | -- UART APB --------------------------------------------------------------- |
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128 | -- UART APB --------------------------------------------------------------- | |
129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
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129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
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130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
131 | -- |
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131 | -- | |
132 | SIGNAL I00_s : STD_LOGIC; |
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132 | SIGNAL I00_s : STD_LOGIC; | |
133 |
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133 | |||
134 | -- CONSTANTS |
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134 | -- CONSTANTS | |
135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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135 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
136 | -- |
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136 | -- | |
137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
140 |
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140 | |||
141 | SIGNAL apbi_ext : apb_slv_in_type; |
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141 | SIGNAL apbi_ext : apb_slv_in_type; | |
142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |
143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |
145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |
147 |
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147 | |||
148 | -- Spacewire signals |
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148 | -- Spacewire signals | |
149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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152 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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153 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
154 | SIGNAL spw_clk : STD_LOGIC; |
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154 | SIGNAL spw_clk : STD_LOGIC; | |
155 | SIGNAL swni : grspw_in_type; |
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155 | SIGNAL swni : grspw_in_type; | |
156 | SIGNAL swno : grspw_out_type; |
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156 | SIGNAL swno : grspw_out_type; | |
157 | -- SIGNAL clkmn : STD_ULOGIC; |
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157 | -- SIGNAL clkmn : STD_ULOGIC; | |
158 | -- SIGNAL txclk : STD_ULOGIC; |
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158 | -- SIGNAL txclk : STD_ULOGIC; | |
159 |
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159 | |||
160 | --GPIO |
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160 | --GPIO | |
161 | SIGNAL gpioi : gpio_in_type; |
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161 | SIGNAL gpioi : gpio_in_type; | |
162 | SIGNAL gpioo : gpio_out_type; |
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162 | SIGNAL gpioo : gpio_out_type; | |
163 |
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163 | |||
164 | -- AD Converter ADS7886 |
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164 | -- AD Converter ADS7886 | |
165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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165 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
166 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
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166 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
167 | SIGNAL sample_val : STD_LOGIC; |
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167 | SIGNAL sample_val : STD_LOGIC; | |
168 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
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168 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
169 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
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169 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
171 |
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171 | |||
172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
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172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
173 |
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173 | |||
174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 | ----------------------------------------------------------------------------- |
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175 | ----------------------------------------------------------------------------- | |
176 |
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176 | |||
177 | BEGIN -- beh |
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177 | BEGIN -- beh | |
178 |
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178 | |||
179 | ----------------------------------------------------------------------------- |
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179 | ----------------------------------------------------------------------------- | |
180 | -- CLK |
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180 | -- CLK | |
181 | ----------------------------------------------------------------------------- |
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181 | ----------------------------------------------------------------------------- | |
182 |
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182 | |||
183 | PROCESS(clk_50) |
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183 | PROCESS(clk_50) | |
184 | BEGIN |
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184 | BEGIN | |
185 | IF clk_50'EVENT AND clk_50 = '1' THEN |
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185 | IF clk_50'EVENT AND clk_50 = '1' THEN | |
186 | clk_50_s <= NOT clk_50_s; |
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186 | clk_50_s <= NOT clk_50_s; | |
187 | END IF; |
|
187 | END IF; | |
188 | END PROCESS; |
|
188 | END PROCESS; | |
189 |
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189 | |||
190 | PROCESS(clk_50_s) |
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190 | PROCESS(clk_50_s) | |
191 | BEGIN |
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191 | BEGIN | |
192 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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192 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
193 | clk_25 <= NOT clk_25; |
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193 | clk_25 <= NOT clk_25; | |
194 | END IF; |
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194 | END IF; | |
195 | END PROCESS; |
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195 | END PROCESS; | |
196 |
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196 | |||
197 | PROCESS(clk_49) |
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197 | PROCESS(clk_49) | |
198 | BEGIN |
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198 | BEGIN | |
199 | IF clk_49'EVENT AND clk_49 = '1' THEN |
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199 | IF clk_49'EVENT AND clk_49 = '1' THEN | |
200 | clk_24 <= NOT clk_24; |
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200 | clk_24 <= NOT clk_24; | |
201 | END IF; |
|
201 | END IF; | |
202 | END PROCESS; |
|
202 | END PROCESS; | |
203 |
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203 | |||
204 | ----------------------------------------------------------------------------- |
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204 | ----------------------------------------------------------------------------- | |
205 |
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205 | |||
206 | PROCESS (clk_25, reset) |
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206 | PROCESS (clk_25, reset) | |
207 | BEGIN -- PROCESS |
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207 | BEGIN -- PROCESS | |
208 | IF reset = '0' THEN -- asynchronous reset (active low) |
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208 | IF reset = '0' THEN -- asynchronous reset (active low) | |
209 | LED0 <= '0'; |
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209 | LED0 <= '0'; | |
210 | LED1 <= '0'; |
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210 | LED1 <= '0'; | |
211 | LED2 <= '0'; |
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211 | LED2 <= '0'; | |
212 | --IO1 <= '0'; |
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212 | --IO1 <= '0'; | |
213 | --IO2 <= '1'; |
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213 | --IO2 <= '1'; | |
214 | --IO3 <= '0'; |
|
214 | --IO3 <= '0'; | |
215 | --IO4 <= '0'; |
|
215 | --IO4 <= '0'; | |
216 | --IO5 <= '0'; |
|
216 | --IO5 <= '0'; | |
217 | --IO6 <= '0'; |
|
217 | --IO6 <= '0'; | |
218 | --IO7 <= '0'; |
|
218 | --IO7 <= '0'; | |
219 | --IO8 <= '0'; |
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219 | --IO8 <= '0'; | |
220 | --IO9 <= '0'; |
|
220 | --IO9 <= '0'; | |
221 | --IO10 <= '0'; |
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221 | --IO10 <= '0'; | |
222 | --IO11 <= '0'; |
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222 | --IO11 <= '0'; | |
223 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
223 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
224 | LED0 <= '0'; |
|
224 | LED0 <= '0'; | |
225 | LED1 <= '1'; |
|
225 | LED1 <= '1'; | |
226 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
226 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
227 | --IO1 <= '1'; |
|
227 | --IO1 <= '1'; | |
228 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
228 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |
229 | --IO3 <= ADC_SDO(0); |
|
229 | --IO3 <= ADC_SDO(0); | |
230 | --IO4 <= ADC_SDO(1); |
|
230 | --IO4 <= ADC_SDO(1); | |
231 | --IO5 <= ADC_SDO(2); |
|
231 | --IO5 <= ADC_SDO(2); | |
232 | --IO6 <= ADC_SDO(3); |
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232 | --IO6 <= ADC_SDO(3); | |
233 | --IO7 <= ADC_SDO(4); |
|
233 | --IO7 <= ADC_SDO(4); | |
234 | --IO8 <= ADC_SDO(5); |
|
234 | --IO8 <= ADC_SDO(5); | |
235 | --IO9 <= ADC_SDO(6); |
|
235 | --IO9 <= ADC_SDO(6); | |
236 | --IO10 <= ADC_SDO(7); |
|
236 | --IO10 <= ADC_SDO(7); | |
237 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
237 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
238 | END IF; |
|
238 | END IF; | |
239 | END PROCESS; |
|
239 | END PROCESS; | |
240 |
|
240 | |||
241 | PROCESS (clk_24, reset) |
|
241 | PROCESS (clk_24, reset) | |
242 | BEGIN -- PROCESS |
|
242 | BEGIN -- PROCESS | |
243 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
243 | IF reset = '0' THEN -- asynchronous reset (active low) | |
244 | I00_s <= '0'; |
|
244 | I00_s <= '0'; | |
245 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
|
245 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge | |
246 | I00_s <= NOT I00_s ; |
|
246 | I00_s <= NOT I00_s ; | |
247 | END IF; |
|
247 | END IF; | |
248 | END PROCESS; |
|
248 | END PROCESS; | |
249 | -- IO0 <= I00_s; |
|
249 | -- IO0 <= I00_s; | |
250 |
|
250 | |||
251 | --UARTs |
|
251 | --UARTs | |
252 | nCTS1 <= '1'; |
|
252 | nCTS1 <= '1'; | |
253 | nCTS2 <= '1'; |
|
253 | nCTS2 <= '1'; | |
254 | nDCD2 <= '1'; |
|
254 | nDCD2 <= '1'; | |
255 |
|
255 | |||
256 | --EXT CONNECTOR |
|
256 | --EXT CONNECTOR | |
257 |
|
257 | |||
258 | --SPACE WIRE |
|
258 | --SPACE WIRE | |
259 |
|
259 | |||
260 | leon3_soc_1 : leon3_soc |
|
260 | leon3_soc_1 : leon3_soc | |
261 | GENERIC MAP ( |
|
261 | GENERIC MAP ( | |
262 | fabtech => apa3e, |
|
262 | fabtech => apa3e, | |
263 | memtech => apa3e, |
|
263 | memtech => apa3e, | |
264 | padtech => inferred, |
|
264 | padtech => inferred, | |
265 | clktech => inferred, |
|
265 | clktech => inferred, | |
266 | disas => 0, |
|
266 | disas => 0, | |
267 | dbguart => 0, |
|
267 | dbguart => 0, | |
268 | pclow => 2, |
|
268 | pclow => 2, | |
269 | clk_freq => 25000, |
|
269 | clk_freq => 25000, | |
270 | NB_CPU => 1, |
|
270 | NB_CPU => 1, | |
271 | ENABLE_FPU => 1, |
|
271 | ENABLE_FPU => 1, | |
272 | FPU_NETLIST => 0, |
|
272 | FPU_NETLIST => 0, | |
273 | ENABLE_DSU => 1, |
|
273 | ENABLE_DSU => 1, | |
274 | ENABLE_AHB_UART => 1, |
|
274 | ENABLE_AHB_UART => 1, | |
275 | ENABLE_APB_UART => 1, |
|
275 | ENABLE_APB_UART => 1, | |
276 | ENABLE_IRQMP => 1, |
|
276 | ENABLE_IRQMP => 1, | |
277 | ENABLE_GPT => 1, |
|
277 | ENABLE_GPT => 1, | |
278 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
278 | NB_AHB_MASTER => NB_AHB_MASTER, | |
279 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
279 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
280 | NB_APB_SLAVE => NB_APB_SLAVE) |
|
280 | NB_APB_SLAVE => NB_APB_SLAVE) | |
281 | PORT MAP ( |
|
281 | PORT MAP ( | |
282 | clk => clk_25, |
|
282 | clk => clk_25, | |
283 | reset => reset, |
|
283 | reset => reset, | |
284 | errorn => errorn, |
|
284 | errorn => errorn, | |
285 | ahbrxd => TXD1, |
|
285 | ahbrxd => TXD1, | |
286 | ahbtxd => RXD1, |
|
286 | ahbtxd => RXD1, | |
287 | urxd1 => TXD2, |
|
287 | urxd1 => TXD2, | |
288 | utxd1 => RXD2, |
|
288 | utxd1 => RXD2, | |
289 | address => SRAM_A, |
|
289 | address => SRAM_A, | |
290 | data => SRAM_DQ, |
|
290 | data => SRAM_DQ, | |
291 | nSRAM_BE0 => SRAM_nBE(0), |
|
291 | nSRAM_BE0 => SRAM_nBE(0), | |
292 | nSRAM_BE1 => SRAM_nBE(1), |
|
292 | nSRAM_BE1 => SRAM_nBE(1), | |
293 | nSRAM_BE2 => SRAM_nBE(2), |
|
293 | nSRAM_BE2 => SRAM_nBE(2), | |
294 | nSRAM_BE3 => SRAM_nBE(3), |
|
294 | nSRAM_BE3 => SRAM_nBE(3), | |
295 | nSRAM_WE => SRAM_nWE, |
|
295 | nSRAM_WE => SRAM_nWE, | |
296 | nSRAM_CE => SRAM_CE, |
|
296 | nSRAM_CE => SRAM_CE, | |
297 | nSRAM_OE => SRAM_nOE, |
|
297 | nSRAM_OE => SRAM_nOE, | |
298 |
|
298 | |||
299 | apbi_ext => apbi_ext, |
|
299 | apbi_ext => apbi_ext, | |
300 | apbo_ext => apbo_ext, |
|
300 | apbo_ext => apbo_ext, | |
301 | ahbi_s_ext => ahbi_s_ext, |
|
301 | ahbi_s_ext => ahbi_s_ext, | |
302 | ahbo_s_ext => ahbo_s_ext, |
|
302 | ahbo_s_ext => ahbo_s_ext, | |
303 | ahbi_m_ext => ahbi_m_ext, |
|
303 | ahbi_m_ext => ahbi_m_ext, | |
304 | ahbo_m_ext => ahbo_m_ext); |
|
304 | ahbo_m_ext => ahbo_m_ext); | |
305 |
|
305 | |||
306 | ------------------------------------------------------------------------------- |
|
306 | ------------------------------------------------------------------------------- | |
307 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
307 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
308 | ------------------------------------------------------------------------------- |
|
308 | ------------------------------------------------------------------------------- | |
309 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
309 | apb_lfr_time_management_1 : apb_lfr_time_management | |
310 | GENERIC MAP ( |
|
310 | GENERIC MAP ( | |
311 | pindex => 6, |
|
311 | pindex => 6, | |
312 | paddr => 6, |
|
312 | paddr => 6, | |
313 | pmask => 16#fff#, |
|
313 | pmask => 16#fff#, | |
314 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
314 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
315 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
315 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
316 | PORT MAP ( |
|
316 | PORT MAP ( | |
317 | clk25MHz => clk_25, |
|
317 | clk25MHz => clk_25, | |
318 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
318 | clk24_576MHz => clk_24, -- 49.152MHz/2 | |
319 | resetn => reset, |
|
319 | resetn => reset, | |
320 | grspw_tick => swno.tickout, |
|
320 | grspw_tick => swno.tickout, | |
321 | apbi => apbi_ext, |
|
321 | apbi => apbi_ext, | |
322 | apbo => apbo_ext(6), |
|
322 | apbo => apbo_ext(6), | |
323 | coarse_time => coarse_time, |
|
323 | coarse_time => coarse_time, | |
324 | fine_time => fine_time); |
|
324 | fine_time => fine_time); | |
325 |
|
325 | |||
326 | ----------------------------------------------------------------------- |
|
326 | ----------------------------------------------------------------------- | |
327 | --- SpaceWire -------------------------------------------------------- |
|
327 | --- SpaceWire -------------------------------------------------------- | |
328 | ----------------------------------------------------------------------- |
|
328 | ----------------------------------------------------------------------- | |
329 |
|
329 | |||
330 | SPW_EN <= '1'; |
|
330 | SPW_EN <= '1'; | |
331 |
|
331 | |||
332 | spw_clk <= clk_50_s; |
|
332 | spw_clk <= clk_50_s; | |
333 | spw_rxtxclk <= spw_clk; |
|
333 | spw_rxtxclk <= spw_clk; | |
334 | spw_rxclkn <= NOT spw_rxtxclk; |
|
334 | spw_rxclkn <= NOT spw_rxtxclk; | |
335 |
|
335 | |||
336 | -- PADS for SPW1 |
|
336 | -- PADS for SPW1 | |
337 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
337 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
338 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
338 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
339 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
339 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
340 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
340 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
341 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
341 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
342 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
342 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
343 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
343 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
344 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
344 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
345 | -- PADS FOR SPW2 |
|
345 | -- PADS FOR SPW2 | |
346 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
346 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
347 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
347 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
348 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
348 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
349 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
349 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
350 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
350 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
351 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
351 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
352 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
352 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
353 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
353 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
354 |
|
354 | |||
355 | -- GRSPW PHY |
|
355 | -- GRSPW PHY | |
356 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
356 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
357 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
357 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
358 | spw_phy0 : grspw_phy |
|
358 | spw_phy0 : grspw_phy | |
359 | GENERIC MAP( |
|
359 | GENERIC MAP( | |
360 | tech => apa3e, |
|
360 | tech => apa3e, | |
361 | rxclkbuftype => 1, |
|
361 | rxclkbuftype => 1, | |
362 | scantest => 0) |
|
362 | scantest => 0) | |
363 | PORT MAP( |
|
363 | PORT MAP( | |
364 | rxrst => swno.rxrst, |
|
364 | rxrst => swno.rxrst, | |
365 | di => dtmp(j), |
|
365 | di => dtmp(j), | |
366 | si => stmp(j), |
|
366 | si => stmp(j), | |
367 | rxclko => spw_rxclk(j), |
|
367 | rxclko => spw_rxclk(j), | |
368 | do => swni.d(j), |
|
368 | do => swni.d(j), | |
369 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
369 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
370 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
370 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
371 | END GENERATE spw_inputloop; |
|
371 | END GENERATE spw_inputloop; | |
372 |
|
372 | |||
373 | -- SPW core |
|
373 | -- SPW core | |
374 | sw0 : grspwm GENERIC MAP( |
|
374 | sw0 : grspwm GENERIC MAP( | |
375 | tech => apa3e, |
|
375 | tech => apa3e, | |
376 | hindex => 1, |
|
376 | hindex => 1, | |
377 | pindex => 5, |
|
377 | pindex => 5, | |
378 | paddr => 5, |
|
378 | paddr => 5, | |
379 | pirq => 11, |
|
379 | pirq => 11, | |
380 | sysfreq => 25000, -- CPU_FREQ |
|
380 | sysfreq => 25000, -- CPU_FREQ | |
381 | rmap => 1, |
|
381 | rmap => 1, | |
382 | rmapcrc => 1, |
|
382 | rmapcrc => 1, | |
383 | fifosize1 => 16, |
|
383 | fifosize1 => 16, | |
384 | fifosize2 => 16, |
|
384 | fifosize2 => 16, | |
385 | rxclkbuftype => 1, |
|
385 | rxclkbuftype => 1, | |
386 | rxunaligned => 0, |
|
386 | rxunaligned => 0, | |
387 | rmapbufs => 4, |
|
387 | rmapbufs => 4, | |
388 | ft => 0, |
|
388 | ft => 0, | |
389 | netlist => 0, |
|
389 | netlist => 0, | |
390 | ports => 2, |
|
390 | ports => 2, | |
391 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
391 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
392 | memtech => apa3e, |
|
392 | memtech => apa3e, | |
393 | destkey => 2, |
|
393 | destkey => 2, | |
394 | spwcore => 1 |
|
394 | spwcore => 1 | |
395 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
395 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
396 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
396 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
397 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
397 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
398 | ) |
|
398 | ) | |
399 | PORT MAP(reset, clk_25, spw_rxclk(0), |
|
399 | PORT MAP(reset, clk_25, spw_rxclk(0), | |
400 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
400 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
401 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
401 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
402 | swni, swno); |
|
402 | swni, swno); | |
403 |
|
403 | |||
404 | swni.tickin <= '0'; |
|
404 | swni.tickin <= '0'; | |
405 | swni.rmapen <= '1'; |
|
405 | swni.rmapen <= '1'; | |
406 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
406 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
407 | swni.tickinraw <= '0'; |
|
407 | swni.tickinraw <= '0'; | |
408 | swni.timein <= (OTHERS => '0'); |
|
408 | swni.timein <= (OTHERS => '0'); | |
409 | swni.dcrstval <= (OTHERS => '0'); |
|
409 | swni.dcrstval <= (OTHERS => '0'); | |
410 | swni.timerrstval <= (OTHERS => '0'); |
|
410 | swni.timerrstval <= (OTHERS => '0'); | |
411 |
|
411 | |||
412 | ------------------------------------------------------------------------------- |
|
412 | ------------------------------------------------------------------------------- | |
413 | -- LFR ------------------------------------------------------------------------ |
|
413 | -- LFR ------------------------------------------------------------------------ | |
414 | ------------------------------------------------------------------------------- |
|
414 | ------------------------------------------------------------------------------- | |
415 | lpp_lfr_1 : lpp_lfr |
|
415 | lpp_lfr_1 : lpp_lfr | |
416 | GENERIC MAP ( |
|
416 | GENERIC MAP ( | |
417 | Mem_use => use_RAM, |
|
417 | Mem_use => use_RAM, | |
418 | nb_data_by_buffer_size => 32, |
|
418 | nb_data_by_buffer_size => 32, | |
419 | nb_word_by_buffer_size => 30, |
|
419 | nb_word_by_buffer_size => 30, | |
420 | nb_snapshot_param_size => 32, |
|
420 | nb_snapshot_param_size => 32, | |
421 | delta_vector_size => 32, |
|
421 | delta_vector_size => 32, | |
422 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
422 | delta_vector_size_f0_2 => 7, -- log2(96) | |
423 | pindex => 15, |
|
423 | pindex => 15, | |
424 | paddr => 15, |
|
424 | paddr => 15, | |
425 | pmask => 16#fff#, |
|
425 | pmask => 16#fff#, | |
426 | pirq_ms => 6, |
|
426 | pirq_ms => 6, | |
427 | pirq_wfp => 14, |
|
427 | pirq_wfp => 14, | |
428 | hindex => 2, |
|
428 | hindex => 2, | |
429 |
top_lfr_version => X"00010 |
|
429 | top_lfr_version => X"00010E") -- aa.bb.cc version | |
430 | PORT MAP ( |
|
430 | PORT MAP ( | |
431 | clk => clk_25, |
|
431 | clk => clk_25, | |
432 | rstn => reset, |
|
432 | rstn => reset, | |
433 | sample_B => sample_s(2 DOWNTO 0), |
|
433 | sample_B => sample_s(2 DOWNTO 0), | |
434 | sample_E => sample_s(7 DOWNTO 3), |
|
434 | sample_E => sample_s(7 DOWNTO 3), | |
435 | sample_val => sample_val, |
|
435 | sample_val => sample_val, | |
436 | apbi => apbi_ext, |
|
436 | apbi => apbi_ext, | |
437 | apbo => apbo_ext(15), |
|
437 | apbo => apbo_ext(15), | |
438 | ahbi => ahbi_m_ext, |
|
438 | ahbi => ahbi_m_ext, | |
439 | ahbo => ahbo_m_ext(2), |
|
439 | ahbo => ahbo_m_ext(2), | |
440 | coarse_time => coarse_time, |
|
440 | coarse_time => coarse_time, | |
441 | fine_time => fine_time, |
|
441 | fine_time => fine_time, | |
442 | data_shaping_BW => bias_fail_sw_sig, |
|
442 | data_shaping_BW => bias_fail_sw_sig, | |
443 | observation_reg => observation_reg); |
|
443 | observation_reg => observation_reg); | |
444 |
|
444 | |||
445 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE |
|
445 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE | |
446 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
|
446 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; | |
447 | END GENERATE all_sample; |
|
447 | END GENERATE all_sample; | |
448 |
|
448 | |||
449 |
|
449 | |||
450 |
|
450 | |||
451 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
451 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
452 | GENERIC MAP( |
|
452 | GENERIC MAP( | |
453 | ChannelCount => 8, |
|
453 | ChannelCount => 8, | |
454 | SampleNbBits => 14, |
|
454 | SampleNbBits => 14, | |
455 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
455 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 | |
456 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
456 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 | |
457 | PORT MAP ( |
|
457 | PORT MAP ( | |
458 | -- CONV |
|
458 | -- CONV | |
459 | cnv_clk => clk_24, |
|
459 | cnv_clk => clk_24, | |
460 | cnv_rstn => reset, |
|
460 | cnv_rstn => reset, | |
461 | cnv => ADC_nCS_sig, |
|
461 | cnv => ADC_nCS_sig, | |
462 | -- DATA |
|
462 | -- DATA | |
463 | clk => clk_25, |
|
463 | clk => clk_25, | |
464 | rstn => reset, |
|
464 | rstn => reset, | |
465 | sck => ADC_CLK_sig, |
|
465 | sck => ADC_CLK_sig, | |
466 | sdo => ADC_SDO_sig, |
|
466 | sdo => ADC_SDO_sig, | |
467 | -- SAMPLE |
|
467 | -- SAMPLE | |
468 | sample => sample, |
|
468 | sample => sample, | |
469 | sample_val => sample_val); |
|
469 | sample_val => sample_val); | |
470 |
|
470 | |||
471 | --IO10 <= ADC_SDO_sig(5); |
|
471 | --IO10 <= ADC_SDO_sig(5); | |
472 | --IO9 <= ADC_SDO_sig(4); |
|
472 | --IO9 <= ADC_SDO_sig(4); | |
473 | --IO8 <= ADC_SDO_sig(3); |
|
473 | --IO8 <= ADC_SDO_sig(3); | |
474 |
|
474 | |||
475 | ADC_nCS <= ADC_nCS_sig; |
|
475 | ADC_nCS <= ADC_nCS_sig; | |
476 | ADC_CLK <= ADC_CLK_sig; |
|
476 | ADC_CLK <= ADC_CLK_sig; | |
477 | ADC_SDO_sig <= ADC_SDO; |
|
477 | ADC_SDO_sig <= ADC_SDO; | |
478 |
|
478 | |||
479 | ---------------------------------------------------------------------- |
|
479 | ---------------------------------------------------------------------- | |
480 | --- GPIO ----------------------------------------------------------- |
|
480 | --- GPIO ----------------------------------------------------------- | |
481 | ---------------------------------------------------------------------- |
|
481 | ---------------------------------------------------------------------- | |
482 |
|
482 | |||
483 | grgpio0 : grgpio |
|
483 | grgpio0 : grgpio | |
484 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
484 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
485 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
485 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
486 |
|
486 | |||
487 | --pio_pad_0 : iopad |
|
487 | --pio_pad_0 : iopad | |
488 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
488 | -- GENERIC MAP (tech => CFG_PADTECH) | |
489 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
489 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
490 | --pio_pad_1 : iopad |
|
490 | --pio_pad_1 : iopad | |
491 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
491 | -- GENERIC MAP (tech => CFG_PADTECH) | |
492 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
492 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
493 | --pio_pad_2 : iopad |
|
493 | --pio_pad_2 : iopad | |
494 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
494 | -- GENERIC MAP (tech => CFG_PADTECH) | |
495 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
495 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
496 | --pio_pad_3 : iopad |
|
496 | --pio_pad_3 : iopad | |
497 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
497 | -- GENERIC MAP (tech => CFG_PADTECH) | |
498 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
498 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
499 | --pio_pad_4 : iopad |
|
499 | --pio_pad_4 : iopad | |
500 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
500 | -- GENERIC MAP (tech => CFG_PADTECH) | |
501 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
501 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
502 | --pio_pad_5 : iopad |
|
502 | --pio_pad_5 : iopad | |
503 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
503 | -- GENERIC MAP (tech => CFG_PADTECH) | |
504 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
504 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
505 | --pio_pad_6 : iopad |
|
505 | --pio_pad_6 : iopad | |
506 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
506 | -- GENERIC MAP (tech => CFG_PADTECH) | |
507 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
507 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
508 | --pio_pad_7 : iopad |
|
508 | --pio_pad_7 : iopad | |
509 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
509 | -- GENERIC MAP (tech => CFG_PADTECH) | |
510 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
510 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
511 |
|
511 | |||
512 | PROCESS (clk_25, reset) |
|
512 | PROCESS (clk_25, reset) | |
513 | BEGIN -- PROCESS |
|
513 | BEGIN -- PROCESS | |
514 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
514 | IF reset = '0' THEN -- asynchronous reset (active low) | |
515 | IO0 <= '0'; |
|
515 | IO0 <= '0'; | |
516 | IO1 <= '0'; |
|
516 | IO1 <= '0'; | |
517 | IO2 <= '0'; |
|
517 | IO2 <= '0'; | |
518 | IO3 <= '0'; |
|
518 | IO3 <= '0'; | |
519 | IO4 <= '0'; |
|
519 | IO4 <= '0'; | |
520 | IO5 <= '0'; |
|
520 | IO5 <= '0'; | |
521 | IO6 <= '0'; |
|
521 | IO6 <= '0'; | |
522 | IO7 <= '0'; |
|
522 | IO7 <= '0'; | |
523 | IO8 <= '0'; |
|
523 | IO8 <= '0'; | |
524 | IO9 <= '0'; |
|
524 | IO9 <= '0'; | |
525 | IO10 <= '0'; |
|
525 | IO10 <= '0'; | |
526 | IO11 <= '0'; |
|
526 | IO11 <= '0'; | |
527 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
527 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |
528 | CASE gpioo.dout(1 DOWNTO 0) IS |
|
528 | CASE gpioo.dout(1 DOWNTO 0) IS | |
529 | WHEN "00" => |
|
529 | WHEN "00" => | |
530 | IO0 <= observation_reg(0 ); |
|
530 | IO0 <= observation_reg(0 ); | |
531 | IO1 <= observation_reg(1 ); |
|
531 | IO1 <= observation_reg(1 ); | |
532 | IO2 <= observation_reg(2 ); |
|
532 | IO2 <= observation_reg(2 ); | |
533 | IO3 <= observation_reg(3 ); |
|
533 | IO3 <= observation_reg(3 ); | |
534 | IO4 <= observation_reg(4 ); |
|
534 | IO4 <= observation_reg(4 ); | |
535 | IO5 <= observation_reg(5 ); |
|
535 | IO5 <= observation_reg(5 ); | |
536 | IO6 <= observation_reg(6 ); |
|
536 | IO6 <= observation_reg(6 ); | |
537 | IO7 <= observation_reg(7 ); |
|
537 | IO7 <= observation_reg(7 ); | |
538 | IO8 <= observation_reg(8 ); |
|
538 | IO8 <= observation_reg(8 ); | |
539 | IO9 <= observation_reg(9 ); |
|
539 | IO9 <= observation_reg(9 ); | |
540 | IO10 <= observation_reg(10); |
|
540 | IO10 <= observation_reg(10); | |
541 | IO11 <= observation_reg(11); |
|
541 | IO11 <= observation_reg(11); | |
542 | WHEN "01" => |
|
542 | WHEN "01" => | |
543 | IO0 <= observation_reg(0 + 12); |
|
543 | IO0 <= observation_reg(0 + 12); | |
544 | IO1 <= observation_reg(1 + 12); |
|
544 | IO1 <= observation_reg(1 + 12); | |
545 | IO2 <= observation_reg(2 + 12); |
|
545 | IO2 <= observation_reg(2 + 12); | |
546 | IO3 <= observation_reg(3 + 12); |
|
546 | IO3 <= observation_reg(3 + 12); | |
547 | IO4 <= observation_reg(4 + 12); |
|
547 | IO4 <= observation_reg(4 + 12); | |
548 | IO5 <= observation_reg(5 + 12); |
|
548 | IO5 <= observation_reg(5 + 12); | |
549 | IO6 <= observation_reg(6 + 12); |
|
549 | IO6 <= observation_reg(6 + 12); | |
550 | IO7 <= observation_reg(7 + 12); |
|
550 | IO7 <= observation_reg(7 + 12); | |
551 | IO8 <= observation_reg(8 + 12); |
|
551 | IO8 <= observation_reg(8 + 12); | |
552 | IO9 <= observation_reg(9 + 12); |
|
552 | IO9 <= observation_reg(9 + 12); | |
553 | IO10 <= observation_reg(10 + 12); |
|
553 | IO10 <= observation_reg(10 + 12); | |
554 | IO11 <= observation_reg(11 + 12); |
|
554 | IO11 <= observation_reg(11 + 12); | |
555 | WHEN "10" => |
|
555 | WHEN "10" => | |
556 | IO0 <= observation_reg(0 + 12 + 12); |
|
556 | IO0 <= observation_reg(0 + 12 + 12); | |
557 | IO1 <= observation_reg(1 + 12 + 12); |
|
557 | IO1 <= observation_reg(1 + 12 + 12); | |
558 | IO2 <= observation_reg(2 + 12 + 12); |
|
558 | IO2 <= observation_reg(2 + 12 + 12); | |
559 | IO3 <= observation_reg(3 + 12 + 12); |
|
559 | IO3 <= observation_reg(3 + 12 + 12); | |
560 | IO4 <= observation_reg(4 + 12 + 12); |
|
560 | IO4 <= observation_reg(4 + 12 + 12); | |
561 | IO5 <= observation_reg(5 + 12 + 12); |
|
561 | IO5 <= observation_reg(5 + 12 + 12); | |
562 | IO6 <= observation_reg(6 + 12 + 12); |
|
562 | IO6 <= observation_reg(6 + 12 + 12); | |
563 | IO7 <= observation_reg(7 + 12 + 12); |
|
563 | IO7 <= observation_reg(7 + 12 + 12); | |
564 | IO8 <= '0'; |
|
564 | IO8 <= '0'; | |
565 | IO9 <= '0'; |
|
565 | IO9 <= '0'; | |
566 | IO10 <= '0'; |
|
566 | IO10 <= '0'; | |
567 | IO11 <= '0'; |
|
567 | IO11 <= '0'; | |
568 | WHEN "11" => |
|
568 | WHEN "11" => | |
569 | IO0 <= '0'; |
|
569 | IO0 <= '0'; | |
570 | IO1 <= '0'; |
|
570 | IO1 <= '0'; | |
571 | IO2 <= '0'; |
|
571 | IO2 <= '0'; | |
572 | IO3 <= '0'; |
|
572 | IO3 <= '0'; | |
573 | IO4 <= '0'; |
|
573 | IO4 <= '0'; | |
574 | IO5 <= '0'; |
|
574 | IO5 <= '0'; | |
575 | IO6 <= '0'; |
|
575 | IO6 <= '0'; | |
576 | IO7 <= '0'; |
|
576 | IO7 <= '0'; | |
577 | IO8 <= '0'; |
|
577 | IO8 <= '0'; | |
578 | IO9 <= '0'; |
|
578 | IO9 <= '0'; | |
579 | IO10 <= '0'; |
|
579 | IO10 <= '0'; | |
580 | IO11 <= '0'; |
|
580 | IO11 <= '0'; | |
581 | WHEN OTHERS => NULL; |
|
581 | WHEN OTHERS => NULL; | |
582 | END CASE; |
|
582 | END CASE; | |
583 |
|
583 | |||
584 | END IF; |
|
584 | END IF; | |
585 | END PROCESS; |
|
585 | END PROCESS; | |
586 |
|
586 | |||
587 | END beh; |
|
587 | END beh; |
@@ -1,770 +1,716 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
8 | USE lpp.FILTERcfg.ALL; |
|
8 | USE lpp.FILTERcfg.ALL; | |
9 | USE lpp.lpp_memory.ALL; |
|
9 | USE lpp.lpp_memory.ALL; | |
10 | USE lpp.lpp_waveform_pkg.ALL; |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
11 | USE lpp.lpp_dma_pkg.ALL; |
|
11 | USE lpp.lpp_dma_pkg.ALL; | |
12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
12 | USE lpp.lpp_top_lfr_pkg.ALL; | |
13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
14 | USE lpp.general_purpose.ALL; |
|
14 | USE lpp.general_purpose.ALL; | |
15 |
|
15 | |||
16 | LIBRARY techmap; |
|
16 | LIBRARY techmap; | |
17 | USE techmap.gencomp.ALL; |
|
17 | USE techmap.gencomp.ALL; | |
18 |
|
18 | |||
19 | LIBRARY grlib; |
|
19 | LIBRARY grlib; | |
20 | USE grlib.amba.ALL; |
|
20 | USE grlib.amba.ALL; | |
21 | USE grlib.stdlib.ALL; |
|
21 | USE grlib.stdlib.ALL; | |
22 | USE grlib.devices.ALL; |
|
22 | USE grlib.devices.ALL; | |
23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
23 | USE GRLIB.DMA2AHB_Package.ALL; | |
24 |
|
24 | |||
25 | ENTITY lpp_lfr IS |
|
25 | ENTITY lpp_lfr IS | |
26 | GENERIC ( |
|
26 | GENERIC ( | |
27 | Mem_use : INTEGER := use_RAM; |
|
27 | Mem_use : INTEGER := use_RAM; | |
28 | nb_data_by_buffer_size : INTEGER := 11; |
|
28 | nb_data_by_buffer_size : INTEGER := 11; | |
29 | nb_word_by_buffer_size : INTEGER := 11; |
|
29 | nb_word_by_buffer_size : INTEGER := 11; | |
30 | nb_snapshot_param_size : INTEGER := 11; |
|
30 | nb_snapshot_param_size : INTEGER := 11; | |
31 | delta_vector_size : INTEGER := 20; |
|
31 | delta_vector_size : INTEGER := 20; | |
32 | delta_vector_size_f0_2 : INTEGER := 7; |
|
32 | delta_vector_size_f0_2 : INTEGER := 7; | |
33 |
|
33 | |||
34 | pindex : INTEGER := 4; |
|
34 | pindex : INTEGER := 4; | |
35 | paddr : INTEGER := 4; |
|
35 | paddr : INTEGER := 4; | |
36 | pmask : INTEGER := 16#fff#; |
|
36 | pmask : INTEGER := 16#fff#; | |
37 | pirq_ms : INTEGER := 0; |
|
37 | pirq_ms : INTEGER := 0; | |
38 | pirq_wfp : INTEGER := 1; |
|
38 | pirq_wfp : INTEGER := 1; | |
39 |
|
39 | |||
40 | hindex : INTEGER := 2; |
|
40 | hindex : INTEGER := 2; | |
41 |
|
41 | |||
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') |
|
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') | |
43 |
|
43 | |||
44 | ); |
|
44 | ); | |
45 | PORT ( |
|
45 | PORT ( | |
46 | clk : IN STD_LOGIC; |
|
46 | clk : IN STD_LOGIC; | |
47 | rstn : IN STD_LOGIC; |
|
47 | rstn : IN STD_LOGIC; | |
48 | -- SAMPLE |
|
48 | -- SAMPLE | |
49 | sample_B : IN Samples(2 DOWNTO 0); |
|
49 | sample_B : IN Samples(2 DOWNTO 0); | |
50 | sample_E : IN Samples(4 DOWNTO 0); |
|
50 | sample_E : IN Samples(4 DOWNTO 0); | |
51 | sample_val : IN STD_LOGIC; |
|
51 | sample_val : IN STD_LOGIC; | |
52 | -- APB |
|
52 | -- APB | |
53 | apbi : IN apb_slv_in_type; |
|
53 | apbi : IN apb_slv_in_type; | |
54 | apbo : OUT apb_slv_out_type; |
|
54 | apbo : OUT apb_slv_out_type; | |
55 | -- AHB |
|
55 | -- AHB | |
56 | ahbi : IN AHB_Mst_In_Type; |
|
56 | ahbi : IN AHB_Mst_In_Type; | |
57 | ahbo : OUT AHB_Mst_Out_Type; |
|
57 | ahbo : OUT AHB_Mst_Out_Type; | |
58 | -- TIME |
|
58 | -- TIME | |
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
61 | -- |
|
61 | -- | |
62 | data_shaping_BW : OUT STD_LOGIC; |
|
62 | data_shaping_BW : OUT STD_LOGIC; | |
63 | -- |
|
63 | -- | |
64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
65 |
|
65 | |||
66 | --debug |
|
66 | --debug | |
67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
68 | --debug_f0_data_valid : OUT STD_LOGIC; |
|
68 | --debug_f0_data_valid : OUT STD_LOGIC; | |
69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
70 | --debug_f1_data_valid : OUT STD_LOGIC; |
|
70 | --debug_f1_data_valid : OUT STD_LOGIC; | |
71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
72 | --debug_f2_data_valid : OUT STD_LOGIC; |
|
72 | --debug_f2_data_valid : OUT STD_LOGIC; | |
73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
74 | --debug_f3_data_valid : OUT STD_LOGIC; |
|
74 | --debug_f3_data_valid : OUT STD_LOGIC; | |
75 |
|
75 | |||
76 | ---- debug FIFO_IN |
|
76 | ---- debug FIFO_IN | |
77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; | |
85 |
|
85 | |||
86 | ----debug FIFO OUT |
|
86 | ----debug FIFO OUT | |
87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; | |
89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; | |
91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; | |
93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; | |
95 |
|
95 | |||
96 | ----debug DMA IN |
|
96 | ----debug DMA IN | |
97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; | |
99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; | |
101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; | |
103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC | |
105 | ); |
|
105 | ); | |
106 | END lpp_lfr; |
|
106 | END lpp_lfr; | |
107 |
|
107 | |||
108 | ARCHITECTURE beh OF lpp_lfr IS |
|
108 | ARCHITECTURE beh OF lpp_lfr IS | |
109 | --SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
109 | --SIGNAL sample : Samples14v(7 DOWNTO 0); | |
110 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
110 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
111 | -- |
|
111 | -- | |
112 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
112 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
113 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
113 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
114 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
114 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
115 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
115 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
116 | -- |
|
116 | -- | |
117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
120 | -- |
|
120 | -- | |
121 | SIGNAL sample_f0_val : STD_LOGIC; |
|
121 | SIGNAL sample_f0_val : STD_LOGIC; | |
122 | SIGNAL sample_f1_val : STD_LOGIC; |
|
122 | SIGNAL sample_f1_val : STD_LOGIC; | |
123 | SIGNAL sample_f2_val : STD_LOGIC; |
|
123 | SIGNAL sample_f2_val : STD_LOGIC; | |
124 | SIGNAL sample_f3_val : STD_LOGIC; |
|
124 | SIGNAL sample_f3_val : STD_LOGIC; | |
125 | -- |
|
125 | -- | |
126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
130 | -- |
|
130 | -- | |
131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
134 |
|
134 | |||
135 | -- SM |
|
135 | -- SM | |
136 |
SIGNAL ready_matrix_f0 |
|
136 | SIGNAL ready_matrix_f0 : STD_LOGIC; | |
137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
138 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
138 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
139 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
139 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
140 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
140 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
141 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
141 | SIGNAL error_bad_component_error : STD_LOGIC; | |
142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
143 |
SIGNAL status_ready_matrix_f0 |
|
143 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; | |
144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
147 | -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
147 | -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
148 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
148 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; | |
149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
150 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
150 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
151 |
SIGNAL addr_matrix_f0 |
|
151 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
152 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
152 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
155 |
|
155 | |||
156 | -- WFP |
|
156 | -- WFP | |
157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
166 |
|
166 | |||
167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
170 | SIGNAL enable_f0 : STD_LOGIC; |
|
170 | SIGNAL enable_f0 : STD_LOGIC; | |
171 | SIGNAL enable_f1 : STD_LOGIC; |
|
171 | SIGNAL enable_f1 : STD_LOGIC; | |
172 | SIGNAL enable_f2 : STD_LOGIC; |
|
172 | SIGNAL enable_f2 : STD_LOGIC; | |
173 | SIGNAL enable_f3 : STD_LOGIC; |
|
173 | SIGNAL enable_f3 : STD_LOGIC; | |
174 | SIGNAL burst_f0 : STD_LOGIC; |
|
174 | SIGNAL burst_f0 : STD_LOGIC; | |
175 | SIGNAL burst_f1 : STD_LOGIC; |
|
175 | SIGNAL burst_f1 : STD_LOGIC; | |
176 | SIGNAL burst_f2 : STD_LOGIC; |
|
176 | SIGNAL burst_f2 : STD_LOGIC; | |
177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
181 |
|
181 | |||
182 | SIGNAL run : STD_LOGIC; |
|
182 | SIGNAL run : STD_LOGIC; | |
183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
184 |
|
184 | |||
185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
|
189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; | |
190 | --f1 |
|
190 | --f1 | |
191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
|
195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; | |
196 | --f2 |
|
196 | --f2 | |
197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
|
201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; | |
202 | --f3 |
|
202 | --f3 | |
203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
|
207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; | |
208 |
|
208 | |||
209 | ----------------------------------------------------------------------------- |
|
209 | ----------------------------------------------------------------------------- | |
210 | -- |
|
210 | -- | |
211 | ----------------------------------------------------------------------------- |
|
211 | ----------------------------------------------------------------------------- | |
212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
|
213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
|
214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
215 | --f1 |
|
215 | --f1 | |
216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
|
217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
|
218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
219 | --f2 |
|
219 | --f2 | |
220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
|
221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
|
222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
223 | --f3 |
|
223 | --f3 | |
224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
|
225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
|
226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
227 |
|
227 | |||
228 | ----------------------------------------------------------------------------- |
|
228 | ----------------------------------------------------------------------------- | |
229 | -- DMA RR |
|
229 | -- DMA RR | |
230 | ----------------------------------------------------------------------------- |
|
230 | ----------------------------------------------------------------------------- | |
231 | SIGNAL dma_sel_valid : STD_LOGIC; |
|
231 | SIGNAL dma_sel_valid : STD_LOGIC; | |
232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
236 |
|
236 | |||
237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
239 |
|
239 | |||
240 | ----------------------------------------------------------------------------- |
|
240 | ----------------------------------------------------------------------------- | |
241 | -- DMA_REG |
|
241 | -- DMA_REG | |
242 | ----------------------------------------------------------------------------- |
|
242 | ----------------------------------------------------------------------------- | |
243 | SIGNAL ongoing_reg : STD_LOGIC; |
|
243 | SIGNAL ongoing_reg : STD_LOGIC; | |
244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
245 | SIGNAL dma_send_reg : STD_LOGIC; |
|
245 | SIGNAL dma_send_reg : STD_LOGIC; | |
246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
249 |
|
249 | |||
250 |
|
250 | |||
251 | ----------------------------------------------------------------------------- |
|
251 | ----------------------------------------------------------------------------- | |
252 | -- DMA |
|
252 | -- DMA | |
253 | ----------------------------------------------------------------------------- |
|
253 | ----------------------------------------------------------------------------- | |
254 | SIGNAL dma_send : STD_LOGIC; |
|
254 | SIGNAL dma_send : STD_LOGIC; | |
255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
256 | SIGNAL dma_done : STD_LOGIC; |
|
256 | SIGNAL dma_done : STD_LOGIC; | |
257 | SIGNAL dma_ren : STD_LOGIC; |
|
257 | SIGNAL dma_ren : STD_LOGIC; | |
258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
261 |
|
261 | |||
262 | ----------------------------------------------------------------------------- |
|
262 | ----------------------------------------------------------------------------- | |
263 | -- DEBUG |
|
|||
264 | ----------------------------------------------------------------------------- |
|
|||
265 | -- |
|
|||
266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|||
267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|||
268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|||
269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|||
270 |
|
||||
271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
279 |
|
||||
280 | ----------------------------------------------------------------------------- |
|
|||
281 | -- MS |
|
263 | -- MS | |
282 | ----------------------------------------------------------------------------- |
|
264 | ----------------------------------------------------------------------------- | |
283 |
|
265 | |||
284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
266 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
267 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
286 | SIGNAL data_ms_valid : STD_LOGIC; |
|
268 | SIGNAL data_ms_valid : STD_LOGIC; | |
287 | SIGNAL data_ms_valid_burst : STD_LOGIC; |
|
269 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |
288 | SIGNAL data_ms_ren : STD_LOGIC; |
|
270 | SIGNAL data_ms_ren : STD_LOGIC; | |
289 | SIGNAL data_ms_done : STD_LOGIC; |
|
271 | SIGNAL data_ms_done : STD_LOGIC; | |
290 |
|
272 | |||
291 | SIGNAL run_ms : STD_LOGIC; |
|
273 | SIGNAL run_ms : STD_LOGIC; | |
292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; |
|
274 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
293 |
|
275 | |||
294 |
SIGNAL matrix_time_f0 |
|
276 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
295 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
277 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
278 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
279 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
298 |
|
280 | |||
299 |
|
281 | |||
300 | SIGNAL error_buffer_full : STD_LOGIC; |
|
282 | SIGNAL error_buffer_full : STD_LOGIC; | |
301 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
283 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
302 |
|
284 | |||
303 | BEGIN |
|
285 | BEGIN | |
304 |
|
286 | |||
305 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
287 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
306 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
288 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
307 |
|
289 | |||
308 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
|
290 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE | |
309 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
291 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |
310 | --END GENERATE all_channel; |
|
292 | --END GENERATE all_channel; | |
311 |
|
293 | |||
312 | ----------------------------------------------------------------------------- |
|
294 | ----------------------------------------------------------------------------- | |
313 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
295 | lpp_lfr_filter_1 : lpp_lfr_filter | |
314 | GENERIC MAP ( |
|
296 | GENERIC MAP ( | |
315 | Mem_use => Mem_use) |
|
297 | Mem_use => Mem_use) | |
316 | PORT MAP ( |
|
298 | PORT MAP ( | |
317 | sample => sample_s, |
|
299 | sample => sample_s, | |
318 | sample_val => sample_val, |
|
300 | sample_val => sample_val, | |
319 | clk => clk, |
|
301 | clk => clk, | |
320 | rstn => rstn, |
|
302 | rstn => rstn, | |
321 | data_shaping_SP0 => data_shaping_SP0, |
|
303 | data_shaping_SP0 => data_shaping_SP0, | |
322 | data_shaping_SP1 => data_shaping_SP1, |
|
304 | data_shaping_SP1 => data_shaping_SP1, | |
323 | data_shaping_R0 => data_shaping_R0, |
|
305 | data_shaping_R0 => data_shaping_R0, | |
324 | data_shaping_R1 => data_shaping_R1, |
|
306 | data_shaping_R1 => data_shaping_R1, | |
325 | sample_f0_val => sample_f0_val, |
|
307 | sample_f0_val => sample_f0_val, | |
326 | sample_f1_val => sample_f1_val, |
|
308 | sample_f1_val => sample_f1_val, | |
327 | sample_f2_val => sample_f2_val, |
|
309 | sample_f2_val => sample_f2_val, | |
328 | sample_f3_val => sample_f3_val, |
|
310 | sample_f3_val => sample_f3_val, | |
329 | sample_f0_wdata => sample_f0_data, |
|
311 | sample_f0_wdata => sample_f0_data, | |
330 | sample_f1_wdata => sample_f1_data, |
|
312 | sample_f1_wdata => sample_f1_data, | |
331 | sample_f2_wdata => sample_f2_data, |
|
313 | sample_f2_wdata => sample_f2_data, | |
332 | sample_f3_wdata => sample_f3_data); |
|
314 | sample_f3_wdata => sample_f3_data); | |
333 |
|
315 | |||
334 | ----------------------------------------------------------------------------- |
|
316 | ----------------------------------------------------------------------------- | |
335 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
317 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |
336 | GENERIC MAP ( |
|
318 | GENERIC MAP ( | |
337 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
319 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
338 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
320 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
339 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
321 | nb_snapshot_param_size => nb_snapshot_param_size, | |
340 | delta_vector_size => delta_vector_size, |
|
322 | delta_vector_size => delta_vector_size, | |
341 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
323 | delta_vector_size_f0_2 => delta_vector_size_f0_2, | |
342 | pindex => pindex, |
|
324 | pindex => pindex, | |
343 | paddr => paddr, |
|
325 | paddr => paddr, | |
344 | pmask => pmask, |
|
326 | pmask => pmask, | |
345 | pirq_ms => pirq_ms, |
|
327 | pirq_ms => pirq_ms, | |
346 | pirq_wfp => pirq_wfp, |
|
328 | pirq_wfp => pirq_wfp, | |
347 | top_lfr_version => top_lfr_version) |
|
329 | top_lfr_version => top_lfr_version) | |
348 | PORT MAP ( |
|
330 | PORT MAP ( | |
349 | HCLK => clk, |
|
331 | HCLK => clk, | |
350 | HRESETn => rstn, |
|
332 | HRESETn => rstn, | |
351 | apbi => apbi, |
|
333 | apbi => apbi, | |
352 | apbo => apbo, |
|
334 | apbo => apbo, | |
353 |
|
335 | |||
354 | run_ms => run_ms, |
|
336 | run_ms => run_ms, | |
355 |
|
337 | |||
356 |
ready_matrix_f0 |
|
338 | ready_matrix_f0 => ready_matrix_f0, | |
357 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
339 | -- ready_matrix_f0_1 => ready_matrix_f0_1, | |
358 | ready_matrix_f1 => ready_matrix_f1, |
|
340 | ready_matrix_f1 => ready_matrix_f1, | |
359 | ready_matrix_f2 => ready_matrix_f2, |
|
341 | ready_matrix_f2 => ready_matrix_f2, | |
360 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
342 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
361 | error_bad_component_error => error_bad_component_error, |
|
343 | error_bad_component_error => error_bad_component_error, | |
362 | error_buffer_full => error_buffer_full, -- TODO |
|
344 | error_buffer_full => error_buffer_full, -- TODO | |
363 | error_input_fifo_write => error_input_fifo_write, -- TODO |
|
345 | error_input_fifo_write => error_input_fifo_write, -- TODO | |
364 | debug_reg => debug_reg, |
|
346 | -- debug_reg => debug_reg, | |
365 |
status_ready_matrix_f0 |
|
347 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
366 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
348 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
367 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
349 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
368 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
350 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
369 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
351 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
370 | -- status_error_bad_component_error => status_error_bad_component_error, |
|
352 | -- status_error_bad_component_error => status_error_bad_component_error, | |
371 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
353 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
372 | config_active_interruption_onError => config_active_interruption_onError, |
|
354 | config_active_interruption_onError => config_active_interruption_onError, | |
373 |
|
355 | |||
374 |
matrix_time_f0 |
|
356 | matrix_time_f0 => matrix_time_f0, | |
375 | -- matrix_time_f0_1 => matrix_time_f0_1, |
|
357 | -- matrix_time_f0_1 => matrix_time_f0_1, | |
376 | matrix_time_f1 => matrix_time_f1, |
|
358 | matrix_time_f1 => matrix_time_f1, | |
377 | matrix_time_f2 => matrix_time_f2, |
|
359 | matrix_time_f2 => matrix_time_f2, | |
378 |
|
360 | |||
379 |
addr_matrix_f0 |
|
361 | addr_matrix_f0 => addr_matrix_f0, | |
380 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
|
362 | -- addr_matrix_f0_1 => addr_matrix_f0_1, | |
381 | addr_matrix_f1 => addr_matrix_f1, |
|
363 | addr_matrix_f1 => addr_matrix_f1, | |
382 | addr_matrix_f2 => addr_matrix_f2, |
|
364 | addr_matrix_f2 => addr_matrix_f2, | |
383 | ------------------------------------------------------------------------- |
|
365 | ------------------------------------------------------------------------- | |
384 | status_full => status_full, |
|
366 | status_full => status_full, | |
385 | status_full_ack => status_full_ack, |
|
367 | status_full_ack => status_full_ack, | |
386 | status_full_err => status_full_err, |
|
368 | status_full_err => status_full_err, | |
387 | status_new_err => status_new_err, |
|
369 | status_new_err => status_new_err, | |
388 | data_shaping_BW => data_shaping_BW, |
|
370 | data_shaping_BW => data_shaping_BW, | |
389 | data_shaping_SP0 => data_shaping_SP0, |
|
371 | data_shaping_SP0 => data_shaping_SP0, | |
390 | data_shaping_SP1 => data_shaping_SP1, |
|
372 | data_shaping_SP1 => data_shaping_SP1, | |
391 | data_shaping_R0 => data_shaping_R0, |
|
373 | data_shaping_R0 => data_shaping_R0, | |
392 | data_shaping_R1 => data_shaping_R1, |
|
374 | data_shaping_R1 => data_shaping_R1, | |
393 | delta_snapshot => delta_snapshot, |
|
375 | delta_snapshot => delta_snapshot, | |
394 | delta_f0 => delta_f0, |
|
376 | delta_f0 => delta_f0, | |
395 | delta_f0_2 => delta_f0_2, |
|
377 | delta_f0_2 => delta_f0_2, | |
396 | delta_f1 => delta_f1, |
|
378 | delta_f1 => delta_f1, | |
397 | delta_f2 => delta_f2, |
|
379 | delta_f2 => delta_f2, | |
398 | nb_data_by_buffer => nb_data_by_buffer, |
|
380 | nb_data_by_buffer => nb_data_by_buffer, | |
399 | nb_word_by_buffer => nb_word_by_buffer, |
|
381 | nb_word_by_buffer => nb_word_by_buffer, | |
400 | nb_snapshot_param => nb_snapshot_param, |
|
382 | nb_snapshot_param => nb_snapshot_param, | |
401 | enable_f0 => enable_f0, |
|
383 | enable_f0 => enable_f0, | |
402 | enable_f1 => enable_f1, |
|
384 | enable_f1 => enable_f1, | |
403 | enable_f2 => enable_f2, |
|
385 | enable_f2 => enable_f2, | |
404 | enable_f3 => enable_f3, |
|
386 | enable_f3 => enable_f3, | |
405 | burst_f0 => burst_f0, |
|
387 | burst_f0 => burst_f0, | |
406 | burst_f1 => burst_f1, |
|
388 | burst_f1 => burst_f1, | |
407 | burst_f2 => burst_f2, |
|
389 | burst_f2 => burst_f2, | |
408 | run => run, |
|
390 | run => run, | |
409 | addr_data_f0 => addr_data_f0, |
|
391 | addr_data_f0 => addr_data_f0, | |
410 | addr_data_f1 => addr_data_f1, |
|
392 | addr_data_f1 => addr_data_f1, | |
411 | addr_data_f2 => addr_data_f2, |
|
393 | addr_data_f2 => addr_data_f2, | |
412 | addr_data_f3 => addr_data_f3, |
|
394 | addr_data_f3 => addr_data_f3, | |
413 |
start_date => start_date |
|
395 | start_date => start_date); | |
414 | --------------------------------------------------------------------------- |
|
|||
415 | debug_reg0 => debug_reg0, |
|
|||
416 | debug_reg1 => debug_reg1, |
|
|||
417 | debug_reg2 => debug_reg2, |
|
|||
418 | debug_reg3 => debug_reg3, |
|
|||
419 | debug_reg4 => debug_reg4, |
|
|||
420 | debug_reg5 => debug_reg5, |
|
|||
421 | debug_reg6 => debug_reg6, |
|
|||
422 | debug_reg7 => debug_reg7); |
|
|||
423 |
|
396 | |||
424 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); |
|
|||
425 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); |
|
|||
426 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); |
|
|||
427 | ----------------------------------------------------------------------------- |
|
397 | ----------------------------------------------------------------------------- | |
428 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug |
|
|||
429 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug |
|
|||
430 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug |
|
|||
431 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug |
|
|||
432 |
|
||||
433 |
|
||||
434 | ----------------------------------------------------------------------------- |
|
398 | ----------------------------------------------------------------------------- | |
435 | lpp_waveform_1 : lpp_waveform |
|
399 | lpp_waveform_1 : lpp_waveform | |
436 | GENERIC MAP ( |
|
400 | GENERIC MAP ( | |
437 | tech => inferred, |
|
401 | tech => inferred, | |
438 | data_size => 6*16, |
|
402 | data_size => 6*16, | |
439 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
403 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
440 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
404 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
441 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
405 | nb_snapshot_param_size => nb_snapshot_param_size, | |
442 | delta_vector_size => delta_vector_size, |
|
406 | delta_vector_size => delta_vector_size, | |
443 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
407 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
444 | ) |
|
408 | ) | |
445 | PORT MAP ( |
|
409 | PORT MAP ( | |
446 | clk => clk, |
|
410 | clk => clk, | |
447 | rstn => rstn, |
|
411 | rstn => rstn, | |
448 |
|
412 | |||
449 | reg_run => run, |
|
413 | reg_run => run, | |
450 | reg_start_date => start_date, |
|
414 | reg_start_date => start_date, | |
451 | reg_delta_snapshot => delta_snapshot, |
|
415 | reg_delta_snapshot => delta_snapshot, | |
452 | reg_delta_f0 => delta_f0, |
|
416 | reg_delta_f0 => delta_f0, | |
453 | reg_delta_f0_2 => delta_f0_2, |
|
417 | reg_delta_f0_2 => delta_f0_2, | |
454 | reg_delta_f1 => delta_f1, |
|
418 | reg_delta_f1 => delta_f1, | |
455 | reg_delta_f2 => delta_f2, |
|
419 | reg_delta_f2 => delta_f2, | |
456 |
|
420 | |||
457 | enable_f0 => enable_f0, |
|
421 | enable_f0 => enable_f0, | |
458 | enable_f1 => enable_f1, |
|
422 | enable_f1 => enable_f1, | |
459 | enable_f2 => enable_f2, |
|
423 | enable_f2 => enable_f2, | |
460 | enable_f3 => enable_f3, |
|
424 | enable_f3 => enable_f3, | |
461 | burst_f0 => burst_f0, |
|
425 | burst_f0 => burst_f0, | |
462 | burst_f1 => burst_f1, |
|
426 | burst_f1 => burst_f1, | |
463 | burst_f2 => burst_f2, |
|
427 | burst_f2 => burst_f2, | |
464 |
|
428 | |||
465 | nb_data_by_buffer => nb_data_by_buffer, |
|
429 | nb_data_by_buffer => nb_data_by_buffer, | |
466 | nb_word_by_buffer => nb_word_by_buffer, |
|
430 | nb_word_by_buffer => nb_word_by_buffer, | |
467 | nb_snapshot_param => nb_snapshot_param, |
|
431 | nb_snapshot_param => nb_snapshot_param, | |
468 | status_full => status_full, |
|
432 | status_full => status_full, | |
469 | status_full_ack => status_full_ack, |
|
433 | status_full_ack => status_full_ack, | |
470 | status_full_err => status_full_err, |
|
434 | status_full_err => status_full_err, | |
471 | status_new_err => status_new_err, |
|
435 | status_new_err => status_new_err, | |
472 |
|
436 | |||
473 | coarse_time => coarse_time, |
|
437 | coarse_time => coarse_time, | |
474 | fine_time => fine_time, |
|
438 | fine_time => fine_time, | |
475 |
|
439 | |||
476 | --f0 |
|
440 | --f0 | |
477 | addr_data_f0 => addr_data_f0, |
|
441 | addr_data_f0 => addr_data_f0, | |
478 | data_f0_in_valid => sample_f0_val, |
|
442 | data_f0_in_valid => sample_f0_val, | |
479 |
data_f0_in => sample_f0_data, |
|
443 | data_f0_in => sample_f0_data, | |
480 |
|
|
444 | --f1 | |
481 | addr_data_f1 => addr_data_f1, |
|
445 | addr_data_f1 => addr_data_f1, | |
482 | data_f1_in_valid => sample_f1_val, |
|
446 | data_f1_in_valid => sample_f1_val, | |
483 |
data_f1_in => sample_f1_data, |
|
447 | data_f1_in => sample_f1_data, | |
484 |
|
|
448 | --f2 | |
485 | addr_data_f2 => addr_data_f2, |
|
449 | addr_data_f2 => addr_data_f2, | |
486 | data_f2_in_valid => sample_f2_val, |
|
450 | data_f2_in_valid => sample_f2_val, | |
487 |
data_f2_in => sample_f2_data, |
|
451 | data_f2_in => sample_f2_data, | |
488 |
|
|
452 | --f3 | |
489 | addr_data_f3 => addr_data_f3, |
|
453 | addr_data_f3 => addr_data_f3, | |
490 | data_f3_in_valid => sample_f3_val, |
|
454 | data_f3_in_valid => sample_f3_val, | |
491 |
data_f3_in => sample_f3_data, |
|
455 | data_f3_in => sample_f3_data, | |
492 |
|
|
456 | -- OUTPUT -- DMA interface | |
493 | --f0 |
|
457 | --f0 | |
494 | data_f0_addr_out => data_f0_addr_out_s, |
|
458 | data_f0_addr_out => data_f0_addr_out_s, | |
495 | data_f0_data_out => data_f0_data_out, |
|
459 | data_f0_data_out => data_f0_data_out, | |
496 | data_f0_data_out_valid => data_f0_data_out_valid_s, |
|
460 | data_f0_data_out_valid => data_f0_data_out_valid_s, | |
497 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
|
461 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, | |
498 | data_f0_data_out_ren => data_f0_data_out_ren, |
|
462 | data_f0_data_out_ren => data_f0_data_out_ren, | |
499 | --f1 |
|
463 | --f1 | |
500 | data_f1_addr_out => data_f1_addr_out_s, |
|
464 | data_f1_addr_out => data_f1_addr_out_s, | |
501 | data_f1_data_out => data_f1_data_out, |
|
465 | data_f1_data_out => data_f1_data_out, | |
502 | data_f1_data_out_valid => data_f1_data_out_valid_s, |
|
466 | data_f1_data_out_valid => data_f1_data_out_valid_s, | |
503 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, |
|
467 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, | |
504 | data_f1_data_out_ren => data_f1_data_out_ren, |
|
468 | data_f1_data_out_ren => data_f1_data_out_ren, | |
505 | --f2 |
|
469 | --f2 | |
506 | data_f2_addr_out => data_f2_addr_out_s, |
|
470 | data_f2_addr_out => data_f2_addr_out_s, | |
507 | data_f2_data_out => data_f2_data_out, |
|
471 | data_f2_data_out => data_f2_data_out, | |
508 | data_f2_data_out_valid => data_f2_data_out_valid_s, |
|
472 | data_f2_data_out_valid => data_f2_data_out_valid_s, | |
509 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, |
|
473 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, | |
510 | data_f2_data_out_ren => data_f2_data_out_ren, |
|
474 | data_f2_data_out_ren => data_f2_data_out_ren, | |
511 | --f3 |
|
475 | --f3 | |
512 | data_f3_addr_out => data_f3_addr_out_s, |
|
476 | data_f3_addr_out => data_f3_addr_out_s, | |
513 | data_f3_data_out => data_f3_data_out, |
|
477 | data_f3_data_out => data_f3_data_out, | |
514 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
478 | data_f3_data_out_valid => data_f3_data_out_valid_s, | |
515 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
479 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |
516 | data_f3_data_out_ren => data_f3_data_out_ren , |
|
480 | data_f3_data_out_ren => data_f3_data_out_ren , | |
517 |
|
481 | |||
518 | ------------------------------------------------------------------------- |
|
482 | ------------------------------------------------------------------------- | |
519 | observation_reg => OPEN |
|
483 | observation_reg => OPEN | |
520 |
|
484 | |||
521 | ); |
|
485 | ); | |
522 |
|
486 | |||
523 |
|
487 | |||
524 | ----------------------------------------------------------------------------- |
|
488 | ----------------------------------------------------------------------------- | |
525 | -- TEMP |
|
489 | -- TEMP | |
526 | ----------------------------------------------------------------------------- |
|
490 | ----------------------------------------------------------------------------- | |
527 |
|
491 | |||
528 | PROCESS (clk, rstn) |
|
492 | PROCESS (clk, rstn) | |
529 | BEGIN -- PROCESS |
|
493 | BEGIN -- PROCESS | |
530 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
494 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
531 | data_f0_data_out_valid <= '0'; |
|
495 | data_f0_data_out_valid <= '0'; | |
532 | data_f0_data_out_valid_burst <= '0'; |
|
496 | data_f0_data_out_valid_burst <= '0'; | |
533 | data_f1_data_out_valid <= '0'; |
|
497 | data_f1_data_out_valid <= '0'; | |
534 | data_f1_data_out_valid_burst <= '0'; |
|
498 | data_f1_data_out_valid_burst <= '0'; | |
535 | data_f2_data_out_valid <= '0'; |
|
499 | data_f2_data_out_valid <= '0'; | |
536 | data_f2_data_out_valid_burst <= '0'; |
|
500 | data_f2_data_out_valid_burst <= '0'; | |
537 | data_f3_data_out_valid <= '0'; |
|
501 | data_f3_data_out_valid <= '0'; | |
538 | data_f3_data_out_valid_burst <= '0'; |
|
502 | data_f3_data_out_valid_burst <= '0'; | |
539 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
503 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
540 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
504 | data_f0_data_out_valid <= data_f0_data_out_valid_s; | |
541 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
|
505 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |
542 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
506 | data_f1_data_out_valid <= data_f1_data_out_valid_s; | |
543 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
|
507 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |
544 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
508 | data_f2_data_out_valid <= data_f2_data_out_valid_s; | |
545 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
|
509 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |
546 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
|
510 | data_f3_data_out_valid <= data_f3_data_out_valid_s; | |
547 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
|
511 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; | |
548 | END IF; |
|
512 | END IF; | |
549 | END PROCESS; |
|
513 | END PROCESS; | |
550 |
|
514 | |||
551 | data_f0_addr_out <= data_f0_addr_out_s; |
|
515 | data_f0_addr_out <= data_f0_addr_out_s; | |
552 | data_f1_addr_out <= data_f1_addr_out_s; |
|
516 | data_f1_addr_out <= data_f1_addr_out_s; | |
553 | data_f2_addr_out <= data_f2_addr_out_s; |
|
517 | data_f2_addr_out <= data_f2_addr_out_s; | |
554 | data_f3_addr_out <= data_f3_addr_out_s; |
|
518 | data_f3_addr_out <= data_f3_addr_out_s; | |
555 |
|
519 | |||
556 | ----------------------------------------------------------------------------- |
|
520 | ----------------------------------------------------------------------------- | |
557 | -- RoundRobin Selection For DMA |
|
521 | -- RoundRobin Selection For DMA | |
558 | ----------------------------------------------------------------------------- |
|
522 | ----------------------------------------------------------------------------- | |
559 |
|
523 | |||
560 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
|
524 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; | |
561 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
|
525 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; | |
562 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
|
526 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; | |
563 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
|
527 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; | |
564 |
|
528 | |||
565 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
529 | RR_Arbiter_4_1 : RR_Arbiter_4 | |
566 | PORT MAP ( |
|
530 | PORT MAP ( | |
567 | clk => clk, |
|
531 | clk => clk, | |
568 | rstn => rstn, |
|
532 | rstn => rstn, | |
569 | in_valid => dma_rr_valid, |
|
533 | in_valid => dma_rr_valid, | |
570 | out_grant => dma_rr_grant_s); |
|
534 | out_grant => dma_rr_grant_s); | |
571 |
|
535 | |||
572 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; |
|
536 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; | |
573 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; |
|
537 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; | |
574 | dma_rr_valid_ms(2) <= '0'; |
|
538 | dma_rr_valid_ms(2) <= '0'; | |
575 | dma_rr_valid_ms(3) <= '0'; |
|
539 | dma_rr_valid_ms(3) <= '0'; | |
576 |
|
540 | |||
577 | RR_Arbiter_4_2 : RR_Arbiter_4 |
|
541 | RR_Arbiter_4_2 : RR_Arbiter_4 | |
578 | PORT MAP ( |
|
542 | PORT MAP ( | |
579 | clk => clk, |
|
543 | clk => clk, | |
580 | rstn => rstn, |
|
544 | rstn => rstn, | |
581 | in_valid => dma_rr_valid_ms, |
|
545 | in_valid => dma_rr_valid_ms, | |
582 | out_grant => dma_rr_grant_ms); |
|
546 | out_grant => dma_rr_grant_ms); | |
583 |
|
547 | |||
584 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; |
|
548 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; | |
585 |
|
549 | |||
586 |
|
550 | |||
587 | ----------------------------------------------------------------------------- |
|
551 | ----------------------------------------------------------------------------- | |
588 | -- in : dma_rr_grant |
|
552 | -- in : dma_rr_grant | |
589 | -- send |
|
553 | -- send | |
590 | -- out : dma_sel |
|
554 | -- out : dma_sel | |
591 | -- dma_valid_burst |
|
555 | -- dma_valid_burst | |
592 | -- dma_sel_valid |
|
556 | -- dma_sel_valid | |
593 | ----------------------------------------------------------------------------- |
|
557 | ----------------------------------------------------------------------------- | |
594 | PROCESS (clk, rstn) |
|
558 | PROCESS (clk, rstn) | |
595 | BEGIN -- PROCESS |
|
559 | BEGIN -- PROCESS | |
596 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
560 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
597 | dma_sel <= (OTHERS => '0'); |
|
561 | dma_sel <= (OTHERS => '0'); | |
598 | dma_send <= '0'; |
|
562 | dma_send <= '0'; | |
599 | dma_valid_burst <= '0'; |
|
563 | dma_valid_burst <= '0'; | |
600 | data_ms_done <= '0'; |
|
564 | data_ms_done <= '0'; | |
601 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
565 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
602 | IF run = '1' THEN |
|
566 | IF run = '1' THEN | |
603 | data_ms_done <= '0'; |
|
567 | data_ms_done <= '0'; | |
604 | IF dma_sel = "00000" OR dma_done = '1' THEN |
|
568 | IF dma_sel = "00000" OR dma_done = '1' THEN | |
605 | dma_sel <= dma_rr_grant; |
|
569 | dma_sel <= dma_rr_grant; | |
606 | IF dma_rr_grant(0) = '1' THEN |
|
570 | IF dma_rr_grant(0) = '1' THEN | |
607 | dma_send <= '1'; |
|
571 | dma_send <= '1'; | |
608 | dma_valid_burst <= data_f0_data_out_valid_burst; |
|
572 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
609 | dma_sel_valid <= data_f0_data_out_valid; |
|
573 | dma_sel_valid <= data_f0_data_out_valid; | |
610 | ELSIF dma_rr_grant(1) = '1' THEN |
|
574 | ELSIF dma_rr_grant(1) = '1' THEN | |
611 | dma_send <= '1'; |
|
575 | dma_send <= '1'; | |
612 | dma_valid_burst <= data_f1_data_out_valid_burst; |
|
576 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
613 | dma_sel_valid <= data_f1_data_out_valid; |
|
577 | dma_sel_valid <= data_f1_data_out_valid; | |
614 | ELSIF dma_rr_grant(2) = '1' THEN |
|
578 | ELSIF dma_rr_grant(2) = '1' THEN | |
615 | dma_send <= '1'; |
|
579 | dma_send <= '1'; | |
616 | dma_valid_burst <= data_f2_data_out_valid_burst; |
|
580 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
617 | dma_sel_valid <= data_f2_data_out_valid; |
|
581 | dma_sel_valid <= data_f2_data_out_valid; | |
618 | ELSIF dma_rr_grant(3) = '1' THEN |
|
582 | ELSIF dma_rr_grant(3) = '1' THEN | |
619 | dma_send <= '1'; |
|
583 | dma_send <= '1'; | |
620 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
584 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
621 | dma_sel_valid <= data_f3_data_out_valid; |
|
585 | dma_sel_valid <= data_f3_data_out_valid; | |
622 | ELSIF dma_rr_grant(4) = '1' THEN |
|
586 | ELSIF dma_rr_grant(4) = '1' THEN | |
623 | dma_send <= '1'; |
|
587 | dma_send <= '1'; | |
624 | dma_valid_burst <= data_ms_valid_burst; |
|
588 | dma_valid_burst <= data_ms_valid_burst; | |
625 | dma_sel_valid <= data_ms_valid; |
|
589 | dma_sel_valid <= data_ms_valid; | |
626 | END IF; |
|
590 | END IF; | |
627 |
|
591 | |||
628 | IF dma_sel(4) = '1' THEN |
|
592 | IF dma_sel(4) = '1' THEN | |
629 | data_ms_done <= '1'; |
|
593 | data_ms_done <= '1'; | |
630 | END IF; |
|
594 | END IF; | |
631 | ELSE |
|
595 | ELSE | |
632 | dma_sel <= dma_sel; |
|
596 | dma_sel <= dma_sel; | |
633 | dma_send <= '0'; |
|
597 | dma_send <= '0'; | |
634 | END IF; |
|
598 | END IF; | |
635 | ELSE |
|
599 | ELSE | |
636 | data_ms_done <= '0'; |
|
600 | data_ms_done <= '0'; | |
637 | dma_sel <= (OTHERS => '0'); |
|
601 | dma_sel <= (OTHERS => '0'); | |
638 | dma_send <= '0'; |
|
602 | dma_send <= '0'; | |
639 | dma_valid_burst <= '0'; |
|
603 | dma_valid_burst <= '0'; | |
640 | END IF; |
|
604 | END IF; | |
641 | END IF; |
|
605 | END IF; | |
642 | END PROCESS; |
|
606 | END PROCESS; | |
643 |
|
607 | |||
644 |
|
608 | |||
645 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
609 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE | |
646 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
610 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE | |
647 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
611 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE | |
648 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE |
|
612 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE | |
649 | data_ms_addr; |
|
613 | data_ms_addr; | |
650 |
|
614 | |||
651 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE |
|
615 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE | |
652 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
616 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE | |
653 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
617 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE | |
654 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE |
|
618 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE | |
655 | data_ms_data; |
|
619 | data_ms_data; | |
656 |
|
620 | |||
657 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
621 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; | |
658 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
622 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; | |
659 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
623 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; | |
660 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
624 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; | |
661 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; |
|
625 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; | |
662 |
|
626 | |||
663 | dma_data_2 <= dma_data; |
|
627 | dma_data_2 <= dma_data; | |
664 |
|
628 | |||
665 |
|
629 | |||
666 |
|
||||
667 |
|
||||
668 |
|
||||
669 | ----------------------------------------------------------------------------- |
|
|||
670 | -- DEBUG -- DMA IN |
|
|||
671 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; |
|
|||
672 | --debug_f0_data_dma_in <= dma_data; |
|
|||
673 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; |
|
|||
674 | --debug_f1_data_dma_in <= dma_data; |
|
|||
675 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; |
|
|||
676 | --debug_f2_data_dma_in <= dma_data; |
|
|||
677 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; |
|
|||
678 | --debug_f3_data_dma_in <= dma_data; |
|
|||
679 | ----------------------------------------------------------------------------- |
|
|||
680 |
|
||||
681 | ----------------------------------------------------------------------------- |
|
630 | ----------------------------------------------------------------------------- | |
682 | -- DMA |
|
631 | -- DMA | |
683 | ----------------------------------------------------------------------------- |
|
632 | ----------------------------------------------------------------------------- | |
684 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
633 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |
685 | GENERIC MAP ( |
|
634 | GENERIC MAP ( | |
686 | tech => inferred, |
|
635 | tech => inferred, | |
687 | hindex => hindex) |
|
636 | hindex => hindex) | |
688 | PORT MAP ( |
|
637 | PORT MAP ( | |
689 | HCLK => clk, |
|
638 | HCLK => clk, | |
690 | HRESETn => rstn, |
|
639 | HRESETn => rstn, | |
691 | run => run, |
|
640 | run => run, | |
692 | AHB_Master_In => ahbi, |
|
641 | AHB_Master_In => ahbi, | |
693 | AHB_Master_Out => ahbo, |
|
642 | AHB_Master_Out => ahbo, | |
694 |
|
643 | |||
695 | send => dma_send, |
|
644 | send => dma_send, | |
696 | valid_burst => dma_valid_burst, |
|
645 | valid_burst => dma_valid_burst, | |
697 | done => dma_done, |
|
646 | done => dma_done, | |
698 | ren => dma_ren, |
|
647 | ren => dma_ren, | |
699 | address => dma_address, |
|
648 | address => dma_address, | |
700 | data => dma_data_2); |
|
649 | data => dma_data_2); | |
701 |
|
650 | |||
702 | ----------------------------------------------------------------------------- |
|
651 | ----------------------------------------------------------------------------- | |
703 | -- Matrix Spectral |
|
652 | -- Matrix Spectral | |
704 | ----------------------------------------------------------------------------- |
|
653 | ----------------------------------------------------------------------------- | |
705 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
654 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |
706 | NOT(sample_f0_val) & NOT(sample_f0_val); |
|
655 | NOT(sample_f0_val) & NOT(sample_f0_val); | |
707 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
656 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
708 | NOT(sample_f1_val) & NOT(sample_f1_val); |
|
657 | NOT(sample_f1_val) & NOT(sample_f1_val); | |
709 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & |
|
658 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | |
710 | NOT(sample_f3_val) & NOT(sample_f3_val); |
|
659 | NOT(sample_f3_val) & NOT(sample_f3_val); | |
711 |
|
660 | |||
712 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
661 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
713 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
662 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
714 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
663 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
715 |
|
664 | |||
716 | ------------------------------------------------------------------------------- |
|
665 | ------------------------------------------------------------------------------- | |
717 |
|
666 | |||
718 | ms_softandhard_rstn <= rstn AND run_ms AND run; |
|
667 | ms_softandhard_rstn <= rstn AND run_ms AND run; | |
719 |
|
668 | |||
720 | ----------------------------------------------------------------------------- |
|
669 | ----------------------------------------------------------------------------- | |
721 | lpp_lfr_ms_1 : lpp_lfr_ms |
|
670 | lpp_lfr_ms_1 : lpp_lfr_ms | |
722 | GENERIC MAP ( |
|
671 | GENERIC MAP ( | |
723 | Mem_use => Mem_use) |
|
672 | Mem_use => Mem_use) | |
724 | PORT MAP ( |
|
673 | PORT MAP ( | |
725 | clk => clk, |
|
674 | clk => clk, | |
726 | rstn => ms_softandhard_rstn, --rstn, |
|
675 | rstn => ms_softandhard_rstn, --rstn, | |
727 |
|
676 | |||
728 | coarse_time => coarse_time, |
|
677 | coarse_time => coarse_time, | |
729 | fine_time => fine_time, |
|
678 | fine_time => fine_time, | |
730 |
|
679 | |||
731 | sample_f0_wen => sample_f0_wen, |
|
680 | sample_f0_wen => sample_f0_wen, | |
732 | sample_f0_wdata => sample_f0_wdata, |
|
681 | sample_f0_wdata => sample_f0_wdata, | |
733 | sample_f1_wen => sample_f1_wen, |
|
682 | sample_f1_wen => sample_f1_wen, | |
734 | sample_f1_wdata => sample_f1_wdata, |
|
683 | sample_f1_wdata => sample_f1_wdata, | |
735 |
sample_f2_wen => sample_f3_wen, -- TODO |
|
684 | sample_f2_wen => sample_f3_wen, -- TODO | |
736 |
sample_f2_wdata => sample_f3_wdata,-- TODO |
|
685 | sample_f2_wdata => sample_f3_wdata,-- TODO | |
737 |
|
686 | |||
738 | dma_addr => data_ms_addr, -- |
|
687 | dma_addr => data_ms_addr, -- | |
739 | dma_data => data_ms_data, -- |
|
688 | dma_data => data_ms_data, -- | |
740 | dma_valid => data_ms_valid, -- |
|
689 | dma_valid => data_ms_valid, -- | |
741 | dma_valid_burst => data_ms_valid_burst, -- |
|
690 | dma_valid_burst => data_ms_valid_burst, -- | |
742 | dma_ren => data_ms_ren, -- |
|
691 | dma_ren => data_ms_ren, -- | |
743 | dma_done => data_ms_done, -- |
|
692 | dma_done => data_ms_done, -- | |
744 |
|
693 | |||
745 |
ready_matrix_f0 => ready_matrix_f0 |
|
694 | ready_matrix_f0 => ready_matrix_f0, | |
746 | ready_matrix_f1 => ready_matrix_f1, |
|
695 | ready_matrix_f1 => ready_matrix_f1, | |
747 | ready_matrix_f2 => ready_matrix_f2, |
|
696 | ready_matrix_f2 => ready_matrix_f2, | |
748 | --error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
|||
749 | error_bad_component_error => error_bad_component_error, |
|
697 | error_bad_component_error => error_bad_component_error, | |
750 |
error_buffer_full => error_buffer_full, |
|
698 | error_buffer_full => error_buffer_full, | |
751 |
|
|
699 | error_input_fifo_write => error_input_fifo_write, | |
752 |
|
|
700 | ||
753 | debug_reg => observation_reg, |
|
701 | debug_reg => observation_reg, | |
754 |
|
702 | |||
755 |
status_ready_matrix_f0 => status_ready_matrix_f0 |
|
703 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
756 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
704 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
757 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
705 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
758 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO |
|
|||
759 | -- status_error_bad_component_error => status_error_bad_component_error,-- TODO |
|
|||
760 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
706 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
761 | config_active_interruption_onError => config_active_interruption_onError, |
|
707 | config_active_interruption_onError => config_active_interruption_onError, | |
762 |
addr_matrix_f0 => addr_matrix_f0 |
|
708 | addr_matrix_f0 => addr_matrix_f0, | |
763 | addr_matrix_f1 => addr_matrix_f1, |
|
709 | addr_matrix_f1 => addr_matrix_f1, | |
764 | addr_matrix_f2 => addr_matrix_f2, |
|
710 | addr_matrix_f2 => addr_matrix_f2, | |
765 |
|
711 | |||
766 |
matrix_time_f0 => matrix_time_f0 |
|
712 | matrix_time_f0 => matrix_time_f0, | |
767 | matrix_time_f1 => matrix_time_f1, |
|
713 | matrix_time_f1 => matrix_time_f1, | |
768 | matrix_time_f2 => matrix_time_f2); |
|
714 | matrix_time_f2 => matrix_time_f2); | |
769 |
|
715 | |||
770 | END beh; No newline at end of file |
|
716 | END beh; |
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1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 | LIBRARY ieee; |
|
23 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
|
24 | USE ieee.std_logic_1164.ALL; | |
25 | USE ieee.numeric_std.ALL; |
|
25 | USE ieee.numeric_std.ALL; | |
26 | LIBRARY grlib; |
|
26 | LIBRARY grlib; | |
27 | USE grlib.amba.ALL; |
|
27 | USE grlib.amba.ALL; | |
28 | USE grlib.stdlib.ALL; |
|
28 | USE grlib.stdlib.ALL; | |
29 | USE grlib.devices.ALL; |
|
29 | USE grlib.devices.ALL; | |
30 | LIBRARY lpp; |
|
30 | LIBRARY lpp; | |
|
31 | USE lpp.lpp_lfr_pkg.ALL; | |||
31 | USE lpp.lpp_amba.ALL; |
|
32 | USE lpp.lpp_amba.ALL; | |
32 | USE lpp.apb_devices_list.ALL; |
|
33 | USE lpp.apb_devices_list.ALL; | |
33 | USE lpp.lpp_memory.ALL; |
|
34 | USE lpp.lpp_memory.ALL; | |
34 | LIBRARY techmap; |
|
35 | LIBRARY techmap; | |
35 | USE techmap.gencomp.ALL; |
|
36 | USE techmap.gencomp.ALL; | |
36 |
|
37 | |||
37 | ENTITY lpp_lfr_apbreg IS |
|
38 | ENTITY lpp_lfr_apbreg IS | |
38 | GENERIC ( |
|
39 | GENERIC ( | |
39 | nb_data_by_buffer_size : INTEGER := 11; |
|
40 | nb_data_by_buffer_size : INTEGER := 11; | |
40 | nb_word_by_buffer_size : INTEGER := 11; |
|
41 | nb_word_by_buffer_size : INTEGER := 11; | |
41 |
nb_snapshot_param_size |
|
42 | nb_snapshot_param_size : INTEGER := 11; | |
42 |
delta_vector_size |
|
43 | delta_vector_size : INTEGER := 20; | |
43 |
delta_vector_size_f0_2 |
|
44 | delta_vector_size_f0_2 : INTEGER := 3; | |
44 |
|
45 | |||
45 | pindex : INTEGER := 4; |
|
46 | pindex : INTEGER := 4; | |
46 | paddr : INTEGER := 4; |
|
47 | paddr : INTEGER := 4; | |
47 | pmask : INTEGER := 16#fff#; |
|
48 | pmask : INTEGER := 16#fff#; | |
48 | pirq_ms : INTEGER := 0; |
|
49 | pirq_ms : INTEGER := 0; | |
49 | pirq_wfp : INTEGER := 1; |
|
50 | pirq_wfp : INTEGER := 1; | |
50 |
top_lfr_version |
|
51 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); | |
51 | PORT ( |
|
52 | PORT ( | |
52 | -- AMBA AHB system signals |
|
53 | -- AMBA AHB system signals | |
53 | HCLK : IN STD_ULOGIC; |
|
54 | HCLK : IN STD_ULOGIC; | |
54 | HRESETn : IN STD_ULOGIC; |
|
55 | HRESETn : IN STD_ULOGIC; | |
55 |
|
56 | |||
56 | -- AMBA APB Slave Interface |
|
57 | -- AMBA APB Slave Interface | |
57 | apbi : IN apb_slv_in_type; |
|
58 | apbi : IN apb_slv_in_type; | |
58 | apbo : OUT apb_slv_out_type; |
|
59 | apbo : OUT apb_slv_out_type; | |
59 |
|
60 | |||
60 | --------------------------------------------------------------------------- |
|
61 | --------------------------------------------------------------------------- | |
61 | -- Spectral Matrix Reg |
|
62 | -- Spectral Matrix Reg | |
62 |
run_ms |
|
63 | run_ms : OUT STD_LOGIC; | |
63 | -- IN |
|
64 | -- IN | |
64 |
ready_matrix_f0 |
|
65 | ready_matrix_f0 : IN STD_LOGIC; | |
65 |
ready_matrix_f1 |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
66 |
ready_matrix_f2 |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
67 |
|
68 | |||
68 |
error_bad_component_error |
|
69 | error_bad_component_error : IN STD_LOGIC; | |
69 |
error_buffer_full |
|
70 | error_buffer_full : IN STD_LOGIC; -- TODO | |
70 |
error_input_fifo_write |
|
71 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO | |
71 |
|
72 | |||
72 |
debug_reg |
|
73 | -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
73 |
|
74 | |||
74 | -- OUT |
|
75 | -- OUT | |
75 |
status_ready_matrix_f0 |
|
76 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
76 |
status_ready_matrix_f1 |
|
77 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
77 |
status_ready_matrix_f2 |
|
78 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
78 |
|
79 | |||
79 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
80 | config_active_interruption_onError : OUT STD_LOGIC; |
|
81 | config_active_interruption_onError : OUT STD_LOGIC; | |
81 |
|
82 | |||
82 |
addr_matrix_f0 |
|
83 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 |
|
|
84 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 |
addr_matrix_f |
|
85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
86 | ||
86 |
|
87 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | ||
87 |
matrix_time_f |
|
88 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
88 |
|
|
89 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
89 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
90 | ||
90 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|||
91 |
|
||||
92 | --------------------------------------------------------------------------- |
|
91 | --------------------------------------------------------------------------- | |
93 | --------------------------------------------------------------------------- |
|
92 | --------------------------------------------------------------------------- | |
94 | -- WaveForm picker Reg |
|
93 | -- WaveForm picker Reg | |
95 |
status_full |
|
94 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
96 |
status_full_ack |
|
95 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
97 |
status_full_err |
|
96 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
98 |
status_new_err |
|
97 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
99 |
|
98 | |||
100 | -- OUT |
|
99 | -- OUT | |
101 | data_shaping_BW : OUT STD_LOGIC; |
|
100 | data_shaping_BW : OUT STD_LOGIC; | |
102 | data_shaping_SP0 : OUT STD_LOGIC; |
|
101 | data_shaping_SP0 : OUT STD_LOGIC; | |
103 | data_shaping_SP1 : OUT STD_LOGIC; |
|
102 | data_shaping_SP1 : OUT STD_LOGIC; | |
104 | data_shaping_R0 : OUT STD_LOGIC; |
|
103 | data_shaping_R0 : OUT STD_LOGIC; | |
105 | data_shaping_R1 : OUT STD_LOGIC; |
|
104 | data_shaping_R1 : OUT STD_LOGIC; | |
106 |
|
105 | |||
107 |
delta_snapshot |
|
106 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
108 |
delta_f0 |
|
107 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
109 |
delta_f0_2 |
|
108 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
110 |
delta_f1 |
|
109 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
111 |
delta_f2 |
|
110 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
112 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
111 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
113 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
112 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
114 |
nb_snapshot_param |
|
113 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
115 |
|
114 | |||
116 | enable_f0 : OUT STD_LOGIC; |
|
115 | enable_f0 : OUT STD_LOGIC; | |
117 | enable_f1 : OUT STD_LOGIC; |
|
116 | enable_f1 : OUT STD_LOGIC; | |
118 | enable_f2 : OUT STD_LOGIC; |
|
117 | enable_f2 : OUT STD_LOGIC; | |
119 | enable_f3 : OUT STD_LOGIC; |
|
118 | enable_f3 : OUT STD_LOGIC; | |
120 |
|
119 | |||
121 | burst_f0 : OUT STD_LOGIC; |
|
120 | burst_f0 : OUT STD_LOGIC; | |
122 | burst_f1 : OUT STD_LOGIC; |
|
121 | burst_f1 : OUT STD_LOGIC; | |
123 | burst_f2 : OUT STD_LOGIC; |
|
122 | burst_f2 : OUT STD_LOGIC; | |
124 |
|
123 | |||
125 | run : OUT STD_LOGIC; |
|
124 | run : OUT STD_LOGIC; | |
126 |
|
125 | |||
127 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
126 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
128 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
127 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
129 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
128 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
130 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
129 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
131 |
start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) |
|
130 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) | |
132 | --------------------------------------------------------------------------- |
|
|||
133 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
134 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
135 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
136 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
137 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
138 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
139 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
140 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
|||
141 |
|
||||
142 | --------------------------------------------------------------------------- |
|
131 | --------------------------------------------------------------------------- | |
143 | ); |
|
132 | ); | |
144 |
|
133 | |||
145 | END lpp_lfr_apbreg; |
|
134 | END lpp_lfr_apbreg; | |
146 |
|
135 | |||
147 | ARCHITECTURE beh OF lpp_lfr_apbreg IS |
|
136 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |
148 |
|
137 | |||
149 | CONSTANT REVISION : INTEGER := 1; |
|
138 | CONSTANT REVISION : INTEGER := 1; | |
150 |
|
139 | |||
151 | CONSTANT pconfig : apb_config_type := ( |
|
140 | CONSTANT pconfig : apb_config_type := ( | |
152 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), |
|
141 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), | |
153 | 1 => apb_iobar(paddr, pmask)); |
|
142 | 1 => apb_iobar(paddr, pmask)); | |
154 |
|
143 | |||
155 | TYPE lpp_SpectralMatrix_regs IS RECORD |
|
144 | TYPE lpp_SpectralMatrix_regs IS RECORD | |
156 | config_active_interruption_onNewMatrix : STD_LOGIC; |
|
145 | config_active_interruption_onNewMatrix : STD_LOGIC; | |
157 | config_active_interruption_onError : STD_LOGIC; |
|
146 | config_active_interruption_onError : STD_LOGIC; | |
158 | config_ms_run : STD_LOGIC; |
|
147 | config_ms_run : STD_LOGIC; | |
159 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
148 | status_ready_matrix_f0_0 : STD_LOGIC; | |
160 |
|
|
149 | status_ready_matrix_f1_0 : STD_LOGIC; | |
161 |
status_ready_matrix_f |
|
150 | status_ready_matrix_f2_0 : STD_LOGIC; | |
162 |
status_ready_matrix_f |
|
151 | status_ready_matrix_f0_1 : STD_LOGIC; | |
163 | -- status_error_anticipating_empty_fifo : STD_LOGIC; |
|
152 | status_ready_matrix_f1_1 : STD_LOGIC; | |
|
153 | status_ready_matrix_f2_1 : STD_LOGIC; | |||
164 | status_error_bad_component_error : STD_LOGIC; |
|
154 | status_error_bad_component_error : STD_LOGIC; | |
165 |
status_error_buffer_full : STD_LOGIC; |
|
155 | status_error_buffer_full : STD_LOGIC; | |
166 |
status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
156 | status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
157 | ||||
167 |
|
|
158 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
168 |
|
|
159 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
169 |
addr_matrix_f1 |
|
160 | addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
170 |
addr_matrix_f |
|
161 | addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
162 | addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
163 | addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
171 |
|
164 | |||
172 |
|
|
165 | time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
173 |
|
|
166 | time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
174 |
|
|
167 | time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
175 |
|
|
168 | time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
176 |
|
169 | time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | ||
177 |
|
|
170 | time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
178 | -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|||
179 | -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|||
180 | -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|||
181 | END RECORD; |
|
171 | END RECORD; | |
182 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
172 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |
183 |
|
173 | |||
184 | TYPE lpp_WaveformPicker_regs IS RECORD |
|
174 | TYPE lpp_WaveformPicker_regs IS RECORD | |
185 |
status_full |
|
175 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
186 |
status_full_err |
|
176 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
187 |
status_new_err |
|
177 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
188 |
data_shaping_BW |
|
178 | data_shaping_BW : STD_LOGIC; | |
189 |
data_shaping_SP0 |
|
179 | data_shaping_SP0 : STD_LOGIC; | |
190 |
data_shaping_SP1 |
|
180 | data_shaping_SP1 : STD_LOGIC; | |
191 |
data_shaping_R0 |
|
181 | data_shaping_R0 : STD_LOGIC; | |
192 |
data_shaping_R1 |
|
182 | data_shaping_R1 : STD_LOGIC; | |
193 |
delta_snapshot |
|
183 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
194 |
delta_f0 |
|
184 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
195 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
185 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
196 |
delta_f1 |
|
186 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
197 |
delta_f2 |
|
187 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
198 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
188 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
199 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
189 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
200 |
nb_snapshot_param |
|
190 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
201 |
enable_f0 |
|
191 | enable_f0 : STD_LOGIC; | |
202 |
enable_f1 |
|
192 | enable_f1 : STD_LOGIC; | |
203 |
enable_f2 |
|
193 | enable_f2 : STD_LOGIC; | |
204 |
enable_f3 |
|
194 | enable_f3 : STD_LOGIC; | |
205 |
burst_f0 |
|
195 | burst_f0 : STD_LOGIC; | |
206 |
burst_f1 |
|
196 | burst_f1 : STD_LOGIC; | |
207 |
burst_f2 |
|
197 | burst_f2 : STD_LOGIC; | |
208 |
run |
|
198 | run : STD_LOGIC; | |
209 |
addr_data_f0 |
|
199 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
210 |
addr_data_f1 |
|
200 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
211 |
addr_data_f2 |
|
201 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
212 |
addr_data_f3 |
|
202 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
213 |
start_date |
|
203 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
214 | END RECORD; |
|
204 | END RECORD; | |
215 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
|
205 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
216 |
|
206 | |||
217 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
207 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
218 |
|
208 | |||
219 | ----------------------------------------------------------------------------- |
|
209 | ----------------------------------------------------------------------------- | |
220 | -- IRQ |
|
210 | -- IRQ | |
221 | ----------------------------------------------------------------------------- |
|
211 | ----------------------------------------------------------------------------- | |
222 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; |
|
212 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
223 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
213 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
224 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
214 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
225 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
215 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
226 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
216 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
227 | SIGNAL ored_irq_wfp : STD_LOGIC; |
|
217 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
|
218 | ||||
|
219 | ----------------------------------------------------------------------------- | |||
|
220 | -- | |||
|
221 | ----------------------------------------------------------------------------- | |||
|
222 | SIGNAL reg0_ready_matrix_f0 : STD_LOGIC; | |||
|
223 | SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
224 | SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
225 | ||||
|
226 | SIGNAL reg1_ready_matrix_f0 : STD_LOGIC; | |||
|
227 | SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
228 | SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
229 | ||||
|
230 | SIGNAL reg0_ready_matrix_f1 : STD_LOGIC; | |||
|
231 | SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
232 | SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
233 | ||||
|
234 | SIGNAL reg1_ready_matrix_f1 : STD_LOGIC; | |||
|
235 | SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
236 | SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
237 | ||||
|
238 | SIGNAL reg0_ready_matrix_f2 : STD_LOGIC; | |||
|
239 | SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
240 | SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
241 | ||||
|
242 | SIGNAL reg1_ready_matrix_f2 : STD_LOGIC; | |||
|
243 | SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
244 | SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
228 |
|
|
245 | ||
229 | BEGIN -- beh |
|
246 | BEGIN -- beh | |
230 |
|
247 | |||
231 |
status_ready_matrix_f0 |
|
248 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; | |
232 |
-- status_ready_matrix_f |
|
249 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
233 |
status_ready_matrix_f |
|
250 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
234 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
|
|||
235 | -- status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; |
|
|||
236 | -- status_error_bad_component_error <= reg_sp.status_error_bad_component_error; |
|
|||
237 |
|
251 | |||
238 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; |
|
252 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |
239 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; |
|
253 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |
240 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; |
|
254 | ||
241 | -- addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; |
|
255 | ||
242 |
addr_matrix_f |
|
256 | -- addr_matrix_f0 <= reg_sp.addr_matrix_f0; | |
243 |
addr_matrix_f |
|
257 | -- addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
|
258 | -- addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |||
244 |
|
259 | |||
245 |
|
260 | |||
246 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; |
|
261 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
247 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; |
|
262 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
248 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; |
|
263 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
249 | data_shaping_R0 <= reg_wp.data_shaping_R0; |
|
264 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
250 | data_shaping_R1 <= reg_wp.data_shaping_R1; |
|
265 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
251 |
|
266 | |||
252 |
delta_snapshot |
|
267 | delta_snapshot <= reg_wp.delta_snapshot; | |
253 |
delta_f0 |
|
268 | delta_f0 <= reg_wp.delta_f0; | |
254 |
delta_f0_2 |
|
269 | delta_f0_2 <= reg_wp.delta_f0_2; | |
255 |
delta_f1 |
|
270 | delta_f1 <= reg_wp.delta_f1; | |
256 |
delta_f2 |
|
271 | delta_f2 <= reg_wp.delta_f2; | |
257 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; |
|
272 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; | |
258 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; |
|
273 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
259 |
nb_snapshot_param |
|
274 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
260 |
|
275 | |||
261 | enable_f0 <= reg_wp.enable_f0; |
|
276 | enable_f0 <= reg_wp.enable_f0; | |
262 | enable_f1 <= reg_wp.enable_f1; |
|
277 | enable_f1 <= reg_wp.enable_f1; | |
263 | enable_f2 <= reg_wp.enable_f2; |
|
278 | enable_f2 <= reg_wp.enable_f2; | |
264 | enable_f3 <= reg_wp.enable_f3; |
|
279 | enable_f3 <= reg_wp.enable_f3; | |
265 |
|
280 | |||
266 | burst_f0 <= reg_wp.burst_f0; |
|
281 | burst_f0 <= reg_wp.burst_f0; | |
267 | burst_f1 <= reg_wp.burst_f1; |
|
282 | burst_f1 <= reg_wp.burst_f1; | |
268 | burst_f2 <= reg_wp.burst_f2; |
|
283 | burst_f2 <= reg_wp.burst_f2; | |
269 |
|
284 | |||
270 | run <= reg_wp.run; |
|
285 | run <= reg_wp.run; | |
271 |
|
286 | |||
272 | addr_data_f0 <= reg_wp.addr_data_f0; |
|
287 | addr_data_f0 <= reg_wp.addr_data_f0; | |
273 | addr_data_f1 <= reg_wp.addr_data_f1; |
|
288 | addr_data_f1 <= reg_wp.addr_data_f1; | |
274 | addr_data_f2 <= reg_wp.addr_data_f2; |
|
289 | addr_data_f2 <= reg_wp.addr_data_f2; | |
275 | addr_data_f3 <= reg_wp.addr_data_f3; |
|
290 | addr_data_f3 <= reg_wp.addr_data_f3; | |
276 |
|
291 | |||
277 | start_date <= reg_wp.start_date; |
|
292 | start_date <= reg_wp.start_date; | |
278 |
|
293 | |||
279 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
|
294 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
280 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
295 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
281 | BEGIN -- PROCESS lpp_dma_top |
|
296 | BEGIN -- PROCESS lpp_dma_top | |
282 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
297 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
283 | reg_sp.config_active_interruption_onNewMatrix <= '0'; |
|
298 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |
284 | reg_sp.config_active_interruption_onError <= '0'; |
|
299 | reg_sp.config_active_interruption_onError <= '0'; | |
285 | reg_sp.config_ms_run <= '1'; |
|
300 | reg_sp.config_ms_run <= '1'; | |
286 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
|
301 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |
287 |
|
|
302 | reg_sp.status_ready_matrix_f1_0 <= '0'; | |
288 |
reg_sp.status_ready_matrix_f |
|
303 | reg_sp.status_ready_matrix_f2_0 <= '0'; | |
289 |
reg_sp.status_ready_matrix_f |
|
304 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
290 |
|
|
305 | reg_sp.status_ready_matrix_f1_1 <= '0'; | |
|
306 | reg_sp.status_ready_matrix_f2_1 <= '0'; | |||
291 | reg_sp.status_error_bad_component_error <= '0'; |
|
307 | reg_sp.status_error_bad_component_error <= '0'; | |
292 | reg_sp.status_error_buffer_full <= '0'; |
|
308 | reg_sp.status_error_buffer_full <= '0'; | |
293 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); |
|
309 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); | |
294 |
|
310 | |||
295 |
reg_sp.addr_matrix_f0_0 |
|
311 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
296 |
|
|
312 | reg_sp.addr_matrix_f1_0 <= (OTHERS => '0'); | |
297 |
reg_sp.addr_matrix_f |
|
313 | reg_sp.addr_matrix_f2_0 <= (OTHERS => '0'); | |
298 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); |
|
314 | ||
|
315 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |||
|
316 | reg_sp.addr_matrix_f1_1 <= (OTHERS => '0'); | |||
|
317 | reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); | |||
299 |
|
318 | |||
300 |
reg_sp. |
|
319 | reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok | |
301 |
|
|
320 | reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok | |
302 |
reg_sp. |
|
321 | reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok | |
303 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); |
|
322 | ||
304 |
|
|
323 | reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok | |
305 |
|
|
324 | reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok | |
306 |
|
|
325 | reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok | |
307 | --reg_sp.fine_time_f2 <= (OTHERS => '0'); |
|
326 | ||
308 |
|
327 | prdata <= (OTHERS => '0'); | ||
309 | prdata <= (OTHERS => '0'); |
|
|||
310 |
|
328 | |||
311 | apbo.pirq <= (OTHERS => '0'); |
|
329 | apbo.pirq <= (OTHERS => '0'); | |
312 |
|
330 | |||
313 | status_full_ack <= (OTHERS => '0'); |
|
331 | status_full_ack <= (OTHERS => '0'); | |
314 |
|
332 | |||
315 |
reg_wp.data_shaping_BW |
|
333 | reg_wp.data_shaping_BW <= '0'; | |
316 |
reg_wp.data_shaping_SP0 |
|
334 | reg_wp.data_shaping_SP0 <= '0'; | |
317 |
reg_wp.data_shaping_SP1 |
|
335 | reg_wp.data_shaping_SP1 <= '0'; | |
318 |
reg_wp.data_shaping_R0 |
|
336 | reg_wp.data_shaping_R0 <= '0'; | |
319 |
reg_wp.data_shaping_R1 |
|
337 | reg_wp.data_shaping_R1 <= '0'; | |
320 |
reg_wp.enable_f0 |
|
338 | reg_wp.enable_f0 <= '0'; | |
321 |
reg_wp.enable_f1 |
|
339 | reg_wp.enable_f1 <= '0'; | |
322 |
reg_wp.enable_f2 |
|
340 | reg_wp.enable_f2 <= '0'; | |
323 |
reg_wp.enable_f3 |
|
341 | reg_wp.enable_f3 <= '0'; | |
324 |
reg_wp.burst_f0 |
|
342 | reg_wp.burst_f0 <= '0'; | |
325 |
reg_wp.burst_f1 |
|
343 | reg_wp.burst_f1 <= '0'; | |
326 |
reg_wp.burst_f2 |
|
344 | reg_wp.burst_f2 <= '0'; | |
327 |
reg_wp.run |
|
345 | reg_wp.run <= '0'; | |
328 |
reg_wp.addr_data_f0 |
|
346 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
329 |
reg_wp.addr_data_f1 |
|
347 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
330 |
reg_wp.addr_data_f2 |
|
348 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
331 |
reg_wp.addr_data_f3 |
|
349 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
332 |
reg_wp.status_full |
|
350 | reg_wp.status_full <= (OTHERS => '0'); | |
333 |
reg_wp.status_full_err |
|
351 | reg_wp.status_full_err <= (OTHERS => '0'); | |
334 |
reg_wp.status_new_err |
|
352 | reg_wp.status_new_err <= (OTHERS => '0'); | |
335 |
reg_wp.delta_snapshot |
|
353 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
336 |
reg_wp.delta_f0 |
|
354 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
337 |
reg_wp.delta_f0_2 |
|
355 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
338 |
reg_wp.delta_f1 |
|
356 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
339 |
reg_wp.delta_f2 |
|
357 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
340 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); |
|
358 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
341 |
reg_wp.nb_snapshot_param |
|
359 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
342 |
reg_wp.start_date |
|
360 | reg_wp.start_date <= (OTHERS => '0'); | |
343 |
|
361 | |||
344 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
362 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
345 |
|
363 | |||
346 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); |
|
364 | reg_sp.time_matrix_f0_0 <= reg0_matrix_time_f0; -- ok | |
347 | -- reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); |
|
365 | reg_sp.time_matrix_f1_0 <= reg0_matrix_time_f1; -- ok | |
348 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); |
|
366 | reg_sp.time_matrix_f2_0 <= reg0_matrix_time_f2; -- ok | |
349 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); |
|
367 | ||
350 |
|
368 | reg_sp.time_matrix_f0_1 <= reg1_matrix_time_f0; -- ok | ||
351 | --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); |
|
369 | reg_sp.time_matrix_f1_1 <= reg1_matrix_time_f1; -- ok | |
352 | --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); |
|
370 | reg_sp.time_matrix_f2_1 <= reg1_matrix_time_f2; -- ok | |
353 | --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); |
|
371 | ||
354 | --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); |
|
|||
355 |
|
||||
356 | status_full_ack <= (OTHERS => '0'); |
|
372 | status_full_ack <= (OTHERS => '0'); | |
357 |
|
373 | |||
358 |
reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0 |
|
374 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0; | |
359 |
|
|
375 | reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1; | |
360 |
reg_sp.status_ready_matrix_f |
|
376 | reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2; | |
361 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; |
|
|||
362 |
|
377 | |||
363 | -- reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
|
378 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0; | |
364 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
|
379 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; | |
365 |
|
380 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; | ||
366 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; |
|
381 | ||
367 |
reg_sp.status_error_ |
|
382 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
368 | reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1); |
|
383 | ||
369 |
reg_sp.status_error_ |
|
384 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; | |
|
385 | reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); | |||
|
386 | reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1); | |||
|
387 | reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2); | |||
370 |
|
388 | |||
371 |
|
389 | |||
372 |
|
390 | |||
373 | all_status: FOR I IN 3 DOWNTO 0 LOOP |
|
391 | all_status : FOR I IN 3 DOWNTO 0 LOOP | |
374 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; |
|
|||
375 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; |
|
|||
376 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; |
|
|||
377 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; |
|
392 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
378 |
reg_wp.status_full_err(I) <= status_full_err(I) |
|
393 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
379 |
reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run |
|
394 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run; | |
380 | END LOOP all_status; |
|
395 | END LOOP all_status; | |
381 |
|
396 | |||
382 | paddr := "000000"; |
|
397 | paddr := "000000"; | |
383 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
398 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
384 | prdata <= (OTHERS => '0'); |
|
399 | prdata <= (OTHERS => '0'); | |
385 | IF apbi.psel(pindex) = '1' THEN |
|
400 | IF apbi.psel(pindex) = '1' THEN | |
386 | -- APB DMA READ -- |
|
401 | -- APB DMA READ -- | |
387 | CASE paddr(7 DOWNTO 2) IS |
|
402 | CASE paddr(7 DOWNTO 2) IS | |
388 | -- |
|
403 | --0 | |
389 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; |
|
404 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |
390 | prdata(1) <= reg_sp.config_active_interruption_onError; |
|
405 | prdata(1) <= reg_sp.config_active_interruption_onError; | |
391 | prdata(2) <= reg_sp.config_ms_run; |
|
406 | prdata(2) <= reg_sp.config_ms_run; | |
|
407 | --1 | |||
392 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
408 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
393 |
|
|
409 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
394 | prdata(2) <= reg_sp.status_ready_matrix_f1; |
|
410 | prdata(2) <= reg_sp.status_ready_matrix_f1_0; | |
395 |
prdata(3) <= reg_sp.status_ready_matrix_f |
|
411 | prdata(3) <= reg_sp.status_ready_matrix_f1_1; | |
396 |
|
|
412 | prdata(4) <= reg_sp.status_ready_matrix_f2_0; | |
397 |
prdata(5) <= reg_sp.status_ |
|
413 | prdata(5) <= reg_sp.status_ready_matrix_f2_1; | |
398 |
prdata(6) <= reg_sp.status_error_b |
|
414 | prdata(6) <= reg_sp.status_error_bad_component_error; | |
399 |
prdata(7) <= reg_sp.status_error_ |
|
415 | prdata(7) <= reg_sp.status_error_buffer_full; | |
400 |
prdata(8) <= reg_sp.status_error_input_fifo_write( |
|
416 | prdata(8) <= reg_sp.status_error_input_fifo_write(0); | |
401 |
prdata(9) <= reg_sp.status_error_input_fifo_write( |
|
417 | prdata(9) <= reg_sp.status_error_input_fifo_write(1); | |
402 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; |
|
418 | prdata(10) <= reg_sp.status_error_input_fifo_write(2); | |
403 | -- WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; |
|
419 | --2 | |
404 |
WHEN "000 |
|
420 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
405 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; |
|
421 | --3 | |
406 |
|
422 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | ||
407 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; |
|
423 | --4 | |
408 |
|
|
424 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0; | |
409 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; |
|
425 | --5 | |
410 |
WHEN "00 |
|
426 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1; | |
411 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; |
|
427 | --6 | |
412 | -- WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; |
|
428 | WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0; | |
413 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; |
|
429 | --7 | |
414 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; |
|
430 | WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1; | |
415 |
|
431 | --8 | ||
416 | WHEN "001111" => prdata <= debug_reg; |
|
432 | WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16); | |
417 | --------------------------------------------------------------------- |
|
433 | --9 | |
418 |
WHEN "0 |
|
434 | WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0); | |
|
435 | --10 | |||
|
436 | WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16); | |||
|
437 | --11 | |||
|
438 | WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0); | |||
|
439 | --12 | |||
|
440 | WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16); | |||
|
441 | --13 | |||
|
442 | WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0); | |||
|
443 | --14 | |||
|
444 | WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16); | |||
|
445 | --15 | |||
|
446 | WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0); | |||
|
447 | --16 | |||
|
448 | WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16); | |||
|
449 | --17 | |||
|
450 | WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0); | |||
|
451 | --18 | |||
|
452 | WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); | |||
|
453 | --19 | |||
|
454 | WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); | |||
|
455 | --------------------------------------------------------------------- | |||
|
456 | --20 | |||
|
457 | WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW; | |||
419 | prdata(1) <= reg_wp.data_shaping_SP0; |
|
458 | prdata(1) <= reg_wp.data_shaping_SP0; | |
420 | prdata(2) <= reg_wp.data_shaping_SP1; |
|
459 | prdata(2) <= reg_wp.data_shaping_SP1; | |
421 | prdata(3) <= reg_wp.data_shaping_R0; |
|
460 | prdata(3) <= reg_wp.data_shaping_R0; | |
422 | prdata(4) <= reg_wp.data_shaping_R1; |
|
461 | prdata(4) <= reg_wp.data_shaping_R1; | |
423 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; |
|
462 | --21 | |
|
463 | WHEN "010101" => prdata(0) <= reg_wp.enable_f0; | |||
424 | prdata(1) <= reg_wp.enable_f1; |
|
464 | prdata(1) <= reg_wp.enable_f1; | |
425 | prdata(2) <= reg_wp.enable_f2; |
|
465 | prdata(2) <= reg_wp.enable_f2; | |
426 | prdata(3) <= reg_wp.enable_f3; |
|
466 | prdata(3) <= reg_wp.enable_f3; | |
427 | prdata(4) <= reg_wp.burst_f0; |
|
467 | prdata(4) <= reg_wp.burst_f0; | |
428 | prdata(5) <= reg_wp.burst_f1; |
|
468 | prdata(5) <= reg_wp.burst_f1; | |
429 | prdata(6) <= reg_wp.burst_f2; |
|
469 | prdata(6) <= reg_wp.burst_f2; | |
430 | prdata(7) <= reg_wp.run; |
|
470 | prdata(7) <= reg_wp.run; | |
431 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; |
|
471 | --22 | |
432 |
WHEN "010 |
|
472 | WHEN "010110" => prdata <= reg_wp.addr_data_f0; | |
433 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; |
|
473 | --23 | |
434 |
WHEN "0101 |
|
474 | WHEN "010111" => prdata <= reg_wp.addr_data_f1; | |
435 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; |
|
475 | --24 | |
|
476 | WHEN "011000" => prdata <= reg_wp.addr_data_f2; | |||
|
477 | --25 | |||
|
478 | WHEN "011001" => prdata <= reg_wp.addr_data_f3; | |||
|
479 | --26 | |||
|
480 | WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |||
436 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
|
481 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |
437 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; |
|
482 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |
438 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; |
|
483 | --27 | |
439 |
WHEN "0110 |
|
484 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
440 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; |
|
485 | --28 | |
441 |
WHEN "011 |
|
486 | WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
442 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; |
|
487 | --29 | |
443 |
WHEN "01110 |
|
488 | WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
444 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; |
|
489 | --30 | |
445 |
WHEN "011110" => prdata( |
|
490 | WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
446 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; |
|
491 | --31 | |
447 | ---------------------------------------------------- |
|
492 | WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
448 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); |
|
493 | --32 | |
449 |
WHEN "10000 |
|
494 | WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
450 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); |
|
495 | --33 | |
451 |
WHEN "1000 |
|
496 | WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
452 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); |
|
497 | --34 | |
453 |
WHEN "100 |
|
498 | WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
454 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); |
|
499 | --35 | |
455 |
WHEN "100 |
|
500 | WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
456 | ---------------------------------------------------- |
|
501 | ---------------------------------------------------- | |
457 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); |
|
502 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
458 | WHEN OTHERS => NULL; |
|
503 | WHEN OTHERS => NULL; | |
459 |
|
504 | |||
460 | END CASE; |
|
505 | END CASE; | |
461 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
506 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
462 | -- APB DMA WRITE -- |
|
507 | -- APB DMA WRITE -- | |
463 | CASE paddr(7 DOWNTO 2) IS |
|
508 | CASE paddr(7 DOWNTO 2) IS | |
464 | -- |
|
509 | -- | |
465 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
510 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
466 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
511 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
467 | reg_sp.config_ms_run <= apbi.pwdata(2); |
|
512 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
468 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); |
|
513 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
469 |
|
|
514 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
470 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); |
|
515 | reg_sp.status_ready_matrix_f1_0 <= apbi.pwdata(2); | |
471 |
reg_sp.status_ready_matrix_f |
|
516 | reg_sp.status_ready_matrix_f1_1 <= apbi.pwdata(3); | |
472 |
|
|
517 | reg_sp.status_ready_matrix_f2_0 <= apbi.pwdata(4); | |
473 |
reg_sp.status_ |
|
518 | reg_sp.status_ready_matrix_f2_1 <= apbi.pwdata(5); | |
474 |
reg_sp.status_error_b |
|
519 | reg_sp.status_error_bad_component_error <= apbi.pwdata(6); | |
475 |
reg_sp.status_error_ |
|
520 | reg_sp.status_error_buffer_full <= apbi.pwdata(7); | |
476 |
reg_sp.status_error_input_fifo_write( |
|
521 | reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(8); | |
477 |
reg_sp.status_error_input_fifo_write( |
|
522 | reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(9); | |
478 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; |
|
523 | reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(10); | |
479 | -- WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; |
|
524 | --2 | |
480 |
WHEN "000 |
|
525 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
481 |
WHEN "000 |
|
526 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
482 | -- |
|
527 | WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata; | |
483 |
WHEN "0 |
|
528 | WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata; | |
|
529 | WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata; | |||
|
530 | WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; | |||
|
531 | --8 to 19 | |||
|
532 | --20 | |||
|
533 | WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |||
484 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
|
534 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
485 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); |
|
535 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |
486 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
|
536 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
487 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); |
|
537 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
488 |
WHEN "010 |
|
538 | WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
489 | reg_wp.enable_f1 <= apbi.pwdata(1); |
|
539 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
490 | reg_wp.enable_f2 <= apbi.pwdata(2); |
|
540 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
491 | reg_wp.enable_f3 <= apbi.pwdata(3); |
|
541 | reg_wp.enable_f3 <= apbi.pwdata(3); | |
492 | reg_wp.burst_f0 <= apbi.pwdata(4); |
|
542 | reg_wp.burst_f0 <= apbi.pwdata(4); | |
493 | reg_wp.burst_f1 <= apbi.pwdata(5); |
|
543 | reg_wp.burst_f1 <= apbi.pwdata(5); | |
494 | reg_wp.burst_f2 <= apbi.pwdata(6); |
|
544 | reg_wp.burst_f2 <= apbi.pwdata(6); | |
495 | reg_wp.run <= apbi.pwdata(7); |
|
545 | reg_wp.run <= apbi.pwdata(7); | |
496 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; |
|
546 | --22 | |
497 |
WHEN "010 |
|
547 | WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
498 |
WHEN "0101 |
|
548 | WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
499 |
WHEN "01 |
|
549 | WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
500 |
WHEN "0101 |
|
550 | WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
|
551 | --26 | |||
|
552 | WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |||
501 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
|
553 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |
502 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
|
554 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |
503 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); |
|
555 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
504 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); |
|
556 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
505 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); |
|
557 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
506 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); |
|
558 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
507 |
WHEN "01 |
|
559 | WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
508 |
WHEN "011 |
|
560 | WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
509 |
WHEN "011 |
|
561 | WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
510 |
WHEN "011 |
|
562 | WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
511 |
WHEN "011 |
|
563 | WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
512 |
WHEN " |
|
564 | WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
513 |
WHEN " |
|
565 | WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
514 |
WHEN " |
|
566 | WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
515 |
WHEN " |
|
567 | WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
516 | -- |
|
568 | -- | |
517 | WHEN OTHERS => NULL; |
|
569 | WHEN OTHERS => NULL; | |
518 | END CASE; |
|
570 | END CASE; | |
519 | END IF; |
|
571 | END IF; | |
520 | END IF; |
|
572 | END IF; | |
521 |
|
573 | |||
522 |
apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 |
|
574 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR | |
523 | -- ready_matrix_f0_1 OR |
|
|||
524 | ready_matrix_f1 OR |
|
575 | ready_matrix_f1 OR | |
525 | ready_matrix_f2) |
|
576 | ready_matrix_f2) | |
526 | ) |
|
577 | ) | |
527 | OR |
|
578 | OR | |
528 | (reg_sp.config_active_interruption_onError AND ( |
|
579 | (reg_sp.config_active_interruption_onError AND ( | |
529 |
|
|
580 | error_bad_component_error | |
530 | error_bad_component_error |
|
581 | OR error_buffer_full | |
531 | OR error_buffer_full |
|
582 | OR error_input_fifo_write(0) | |
532 |
|
|
583 | OR error_input_fifo_write(1) | |
533 |
|
|
584 | OR error_input_fifo_write(2)) | |
534 | OR error_input_fifo_write(2)) |
|
585 | )); | |
535 | )); |
|
|||
536 |
|
586 | |||
537 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; |
|
587 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; | |
538 |
|
588 | |||
539 | END IF; |
|
589 | END IF; | |
540 | END PROCESS lpp_lfr_apbreg; |
|
590 | END PROCESS lpp_lfr_apbreg; | |
541 |
|
591 | |||
542 | apbo.pindex <= pindex; |
|
592 | apbo.pindex <= pindex; | |
543 | apbo.pconfig <= pconfig; |
|
593 | apbo.pconfig <= pconfig; | |
544 | apbo.prdata <= prdata; |
|
594 | apbo.prdata <= prdata; | |
545 |
|
595 | |||
546 | ----------------------------------------------------------------------------- |
|
596 | ----------------------------------------------------------------------------- | |
547 | -- IRQ |
|
597 | -- IRQ | |
548 | ----------------------------------------------------------------------------- |
|
598 | ----------------------------------------------------------------------------- | |
549 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; |
|
599 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; | |
550 |
|
600 | |||
551 | PROCESS (HCLK, HRESETn) |
|
601 | PROCESS (HCLK, HRESETn) | |
552 | BEGIN -- PROCESS |
|
602 | BEGIN -- PROCESS | |
553 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
603 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
554 |
irq_wfp_reg |
|
604 | irq_wfp_reg <= (OTHERS => '0'); | |
555 |
ELSIF HCLK' |
|
605 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
556 |
irq_wfp_reg <= irq_wfp_reg_s; |
|
606 | irq_wfp_reg <= irq_wfp_reg_s; | |
557 | END IF; |
|
607 | END IF; | |
558 | END PROCESS; |
|
608 | END PROCESS; | |
559 |
|
609 | |||
560 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE |
|
610 | all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
561 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); |
|
611 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); | |
562 | END GENERATE all_irq_wfp; |
|
612 | END GENERATE all_irq_wfp; | |
563 |
|
613 | |||
564 | irq_wfp_ZERO <= (OTHERS => '0'); |
|
614 | irq_wfp_ZERO <= (OTHERS => '0'); | |
565 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; |
|
615 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; | |
566 |
|
616 | |||
567 | run_ms <= reg_sp.config_ms_run; |
|
617 | run_ms <= reg_sp.config_ms_run; | |
|
618 | ||||
|
619 | ----------------------------------------------------------------------------- | |||
|
620 | -- | |||
|
621 | ----------------------------------------------------------------------------- | |||
|
622 | lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer | |||
|
623 | PORT MAP ( | |||
|
624 | clk => HCLK, | |||
|
625 | rstn => HRESETn, | |||
|
626 | ||||
|
627 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, | |||
|
628 | reg0_ready_matrix => reg0_ready_matrix_f0, | |||
|
629 | reg0_addr_matrix => reg0_addr_matrix_f0, | |||
|
630 | reg0_matrix_time => reg0_matrix_time_f0, | |||
|
631 | ||||
|
632 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1, | |||
|
633 | reg1_ready_matrix => reg1_ready_matrix_f0, | |||
|
634 | reg1_addr_matrix => reg1_addr_matrix_f0, | |||
|
635 | reg1_matrix_time => reg1_matrix_time_f0, | |||
|
636 | ||||
|
637 | ready_matrix => ready_matrix_f0, | |||
|
638 | status_ready_matrix => status_ready_matrix_f0, | |||
|
639 | addr_matrix => addr_matrix_f0, | |||
|
640 | matrix_time => matrix_time_f0); | |||
|
641 | ||||
|
642 | lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer | |||
|
643 | PORT MAP ( | |||
|
644 | clk => HCLK, | |||
|
645 | rstn => HRESETn, | |||
|
646 | ||||
|
647 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, | |||
|
648 | reg0_ready_matrix => reg0_ready_matrix_f1, | |||
|
649 | reg0_addr_matrix => reg0_addr_matrix_f1, | |||
|
650 | reg0_matrix_time => reg0_matrix_time_f1, | |||
|
651 | ||||
|
652 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1, | |||
|
653 | reg1_ready_matrix => reg1_ready_matrix_f1, | |||
|
654 | reg1_addr_matrix => reg1_addr_matrix_f1, | |||
|
655 | reg1_matrix_time => reg1_matrix_time_f1, | |||
|
656 | ||||
|
657 | ready_matrix => ready_matrix_f1, | |||
|
658 | status_ready_matrix => status_ready_matrix_f1, | |||
|
659 | addr_matrix => addr_matrix_f1, | |||
|
660 | matrix_time => matrix_time_f1); | |||
568 |
|
661 | |||
569 | END beh; |
|
662 | lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer | |
|
663 | PORT MAP ( | |||
|
664 | clk => HCLK, | |||
|
665 | rstn => HRESETn, | |||
|
666 | ||||
|
667 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, | |||
|
668 | reg0_ready_matrix => reg0_ready_matrix_f2, | |||
|
669 | reg0_addr_matrix => reg0_addr_matrix_f2, | |||
|
670 | reg0_matrix_time => reg0_matrix_time_f2, | |||
|
671 | ||||
|
672 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1, | |||
|
673 | reg1_ready_matrix => reg1_ready_matrix_f2, | |||
|
674 | reg1_addr_matrix => reg1_addr_matrix_f2, | |||
|
675 | reg1_matrix_time => reg1_matrix_time_f2, | |||
|
676 | ||||
|
677 | ready_matrix => ready_matrix_f2, | |||
|
678 | status_ready_matrix => status_ready_matrix_f2, | |||
|
679 | addr_matrix => addr_matrix_f2, | |||
|
680 | matrix_time => matrix_time_f2); | |||
|
681 | ||||
|
682 | ||||
|
683 | END beh; No newline at end of file |
@@ -1,395 +1,406 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | LIBRARY grlib; |
|
4 | LIBRARY grlib; | |
5 | USE grlib.amba.ALL; |
|
5 | USE grlib.amba.ALL; | |
6 |
|
6 | |||
7 | LIBRARY lpp; |
|
7 | LIBRARY lpp; | |
8 | USE lpp.lpp_ad_conv.ALL; |
|
8 | USE lpp.lpp_ad_conv.ALL; | |
9 | USE lpp.iir_filter.ALL; |
|
9 | USE lpp.iir_filter.ALL; | |
10 | USE lpp.FILTERcfg.ALL; |
|
10 | USE lpp.FILTERcfg.ALL; | |
11 | USE lpp.lpp_memory.ALL; |
|
11 | USE lpp.lpp_memory.ALL; | |
12 | LIBRARY techmap; |
|
12 | LIBRARY techmap; | |
13 | USE techmap.gencomp.ALL; |
|
13 | USE techmap.gencomp.ALL; | |
14 |
|
14 | |||
15 | PACKAGE lpp_lfr_pkg IS |
|
15 | PACKAGE lpp_lfr_pkg IS | |
16 | ----------------------------------------------------------------------------- |
|
16 | ----------------------------------------------------------------------------- | |
17 | -- TEMP |
|
17 | -- TEMP | |
18 | ----------------------------------------------------------------------------- |
|
18 | ----------------------------------------------------------------------------- | |
19 | COMPONENT lpp_lfr_ms_test |
|
19 | COMPONENT lpp_lfr_ms_test | |
20 | GENERIC ( |
|
20 | GENERIC ( | |
21 | Mem_use : INTEGER); |
|
21 | Mem_use : INTEGER); | |
22 | PORT ( |
|
22 | PORT ( | |
23 | clk : IN STD_LOGIC; |
|
23 | clk : IN STD_LOGIC; | |
24 | rstn : IN STD_LOGIC; |
|
24 | rstn : IN STD_LOGIC; | |
25 |
|
25 | |||
26 | -- TIME |
|
26 | -- TIME | |
27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
29 | -- |
|
29 | -- | |
30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
32 | -- |
|
32 | -- | |
33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
35 | -- |
|
35 | -- | |
36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
38 |
|
38 | |||
39 |
|
39 | |||
40 |
|
40 | |||
41 | --------------------------------------------------------------------------- |
|
41 | --------------------------------------------------------------------------- | |
42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
43 |
|
43 | |||
44 | -- |
|
44 | -- | |
45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
49 |
|
49 | |||
50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); | |
51 |
|
51 | |||
52 | -- IN |
|
52 | -- IN | |
53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
54 |
|
54 | |||
55 | ----------------------------------------------------------------------------- |
|
55 | ----------------------------------------------------------------------------- | |
56 |
|
56 | |||
57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); | |
58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
61 |
|
61 | |||
62 | SM_correlation_start : OUT STD_LOGIC; |
|
62 | SM_correlation_start : OUT STD_LOGIC; | |
63 | SM_correlation_auto : OUT STD_LOGIC; |
|
63 | SM_correlation_auto : OUT STD_LOGIC; | |
64 | SM_correlation_done : IN STD_LOGIC |
|
64 | SM_correlation_done : IN STD_LOGIC | |
65 | ); |
|
65 | ); | |
66 | END COMPONENT; |
|
66 | END COMPONENT; | |
67 |
|
67 | |||
68 |
|
68 | |||
69 | ----------------------------------------------------------------------------- |
|
69 | ----------------------------------------------------------------------------- | |
70 | COMPONENT lpp_lfr_ms |
|
70 | COMPONENT lpp_lfr_ms | |
71 | GENERIC ( |
|
71 | GENERIC ( | |
72 | Mem_use : INTEGER |
|
72 | Mem_use : INTEGER | |
73 | ); |
|
73 | ); | |
74 | PORT ( |
|
74 | PORT ( | |
75 | clk : IN STD_LOGIC; |
|
75 | clk : IN STD_LOGIC; | |
76 | rstn : IN STD_LOGIC; |
|
76 | rstn : IN STD_LOGIC; | |
77 |
|
77 | |||
78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
79 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
79 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
80 |
|
80 | |||
81 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
81 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
82 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
82 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
83 |
|
83 | |||
84 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
84 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
85 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
85 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
86 |
|
86 | |||
87 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
87 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
88 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
88 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
89 |
|
89 | |||
90 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | dma_valid : OUT STD_LOGIC; |
|
92 | dma_valid : OUT STD_LOGIC; | |
93 | dma_valid_burst : OUT STD_LOGIC; |
|
93 | dma_valid_burst : OUT STD_LOGIC; | |
94 | dma_ren : IN STD_LOGIC; |
|
94 | dma_ren : IN STD_LOGIC; | |
95 | dma_done : IN STD_LOGIC; |
|
95 | dma_done : IN STD_LOGIC; | |
96 |
|
96 | |||
97 | ready_matrix_f0 : OUT STD_LOGIC; |
|
97 | ready_matrix_f0 : OUT STD_LOGIC; | |
98 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
98 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
99 | ready_matrix_f1 : OUT STD_LOGIC; |
|
99 | ready_matrix_f1 : OUT STD_LOGIC; | |
100 | ready_matrix_f2 : OUT STD_LOGIC; |
|
100 | ready_matrix_f2 : OUT STD_LOGIC; | |
101 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
101 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; | |
102 | error_bad_component_error : OUT STD_LOGIC; |
|
102 | error_bad_component_error : OUT STD_LOGIC; | |
103 | error_buffer_full : OUT STD_LOGIC; |
|
103 | error_buffer_full : OUT STD_LOGIC; | |
104 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
104 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
105 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
105 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
106 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
106 | status_ready_matrix_f0 : IN STD_LOGIC; | |
107 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
107 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
108 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
108 | status_ready_matrix_f1 : IN STD_LOGIC; | |
109 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
109 | status_ready_matrix_f2 : IN STD_LOGIC; | |
110 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
110 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
111 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
111 | -- status_error_bad_component_error : IN STD_LOGIC; | |
112 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
112 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
113 | config_active_interruption_onError : IN STD_LOGIC; |
|
113 | config_active_interruption_onError : IN STD_LOGIC; | |
114 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
114 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
115 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
115 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
116 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
116 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
117 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
117 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
118 |
|
118 | |||
119 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
119 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
120 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
120 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
121 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
121 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
122 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
122 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
123 | END COMPONENT; |
|
123 | END COMPONENT; | |
124 |
|
124 | |||
125 | COMPONENT lpp_lfr_ms_fsmdma |
|
125 | COMPONENT lpp_lfr_ms_fsmdma | |
126 | PORT ( |
|
126 | PORT ( | |
127 | HCLK : IN STD_ULOGIC; |
|
127 | HCLK : IN STD_ULOGIC; | |
128 | HRESETn : IN STD_ULOGIC; |
|
128 | HRESETn : IN STD_ULOGIC; | |
129 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
129 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
130 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
130 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
131 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
131 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
132 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
132 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
133 | fifo_empty : IN STD_LOGIC; |
|
133 | fifo_empty : IN STD_LOGIC; | |
134 | fifo_ren : OUT STD_LOGIC; |
|
134 | fifo_ren : OUT STD_LOGIC; | |
135 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
135 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
136 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
136 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
137 | --fifo_empty : IN STD_LOGIC; |
|
137 | --fifo_empty : IN STD_LOGIC; | |
138 | --fifo_ren : OUT STD_LOGIC; |
|
138 | --fifo_ren : OUT STD_LOGIC; | |
139 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
139 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
140 | --header_val : IN STD_LOGIC; |
|
140 | --header_val : IN STD_LOGIC; | |
141 | --header_ack : OUT STD_LOGIC; |
|
141 | --header_ack : OUT STD_LOGIC; | |
142 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
143 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
143 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
144 | dma_valid : OUT STD_LOGIC; |
|
144 | dma_valid : OUT STD_LOGIC; | |
145 | dma_valid_burst : OUT STD_LOGIC; |
|
145 | dma_valid_burst : OUT STD_LOGIC; | |
146 | dma_ren : IN STD_LOGIC; |
|
146 | dma_ren : IN STD_LOGIC; | |
147 | dma_done : IN STD_LOGIC; |
|
147 | dma_done : IN STD_LOGIC; | |
148 | ready_matrix_f0 : OUT STD_LOGIC; |
|
148 | ready_matrix_f0 : OUT STD_LOGIC; | |
149 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
149 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
150 | ready_matrix_f1 : OUT STD_LOGIC; |
|
150 | ready_matrix_f1 : OUT STD_LOGIC; | |
151 | ready_matrix_f2 : OUT STD_LOGIC; |
|
151 | ready_matrix_f2 : OUT STD_LOGIC; | |
152 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
152 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; | |
153 | error_bad_component_error : OUT STD_LOGIC; |
|
153 | error_bad_component_error : OUT STD_LOGIC; | |
154 | error_buffer_full : OUT STD_LOGIC; |
|
154 | error_buffer_full : OUT STD_LOGIC; | |
155 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
155 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
156 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
156 | status_ready_matrix_f0 : IN STD_LOGIC; | |
157 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
157 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
158 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
158 | status_ready_matrix_f1 : IN STD_LOGIC; | |
159 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
159 | status_ready_matrix_f2 : IN STD_LOGIC; | |
160 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
160 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
161 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
161 | -- status_error_bad_component_error : IN STD_LOGIC; | |
162 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
162 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
163 | config_active_interruption_onError : IN STD_LOGIC; |
|
163 | config_active_interruption_onError : IN STD_LOGIC; | |
164 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
164 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
165 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
165 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
166 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
166 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
167 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
167 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
168 |
|
168 | |||
169 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
169 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
170 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
170 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
171 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
171 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
172 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
172 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
173 | ); |
|
173 | ); | |
174 | END COMPONENT; |
|
174 | END COMPONENT; | |
175 |
|
175 | |||
176 | COMPONENT lpp_lfr_ms_FFT |
|
176 | COMPONENT lpp_lfr_ms_FFT | |
177 | PORT ( |
|
177 | PORT ( | |
178 | clk : IN STD_LOGIC; |
|
178 | clk : IN STD_LOGIC; | |
179 | rstn : IN STD_LOGIC; |
|
179 | rstn : IN STD_LOGIC; | |
180 | sample_valid : IN STD_LOGIC; |
|
180 | sample_valid : IN STD_LOGIC; | |
181 | fft_read : IN STD_LOGIC; |
|
181 | fft_read : IN STD_LOGIC; | |
182 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
182 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
183 | sample_load : OUT STD_LOGIC; |
|
183 | sample_load : OUT STD_LOGIC; | |
184 | fft_pong : OUT STD_LOGIC; |
|
184 | fft_pong : OUT STD_LOGIC; | |
185 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
185 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
186 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
186 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
187 | fft_data_valid : OUT STD_LOGIC; |
|
187 | fft_data_valid : OUT STD_LOGIC; | |
188 | fft_ready : OUT STD_LOGIC); |
|
188 | fft_ready : OUT STD_LOGIC); | |
189 | END COMPONENT; |
|
189 | END COMPONENT; | |
190 |
|
190 | |||
191 | COMPONENT lpp_lfr_filter |
|
191 | COMPONENT lpp_lfr_filter | |
192 | GENERIC ( |
|
192 | GENERIC ( | |
193 | Mem_use : INTEGER); |
|
193 | Mem_use : INTEGER); | |
194 | PORT ( |
|
194 | PORT ( | |
195 | sample : IN Samples(7 DOWNTO 0); |
|
195 | sample : IN Samples(7 DOWNTO 0); | |
196 | sample_val : IN STD_LOGIC; |
|
196 | sample_val : IN STD_LOGIC; | |
197 | clk : IN STD_LOGIC; |
|
197 | clk : IN STD_LOGIC; | |
198 | rstn : IN STD_LOGIC; |
|
198 | rstn : IN STD_LOGIC; | |
199 | data_shaping_SP0 : IN STD_LOGIC; |
|
199 | data_shaping_SP0 : IN STD_LOGIC; | |
200 | data_shaping_SP1 : IN STD_LOGIC; |
|
200 | data_shaping_SP1 : IN STD_LOGIC; | |
201 | data_shaping_R0 : IN STD_LOGIC; |
|
201 | data_shaping_R0 : IN STD_LOGIC; | |
202 | data_shaping_R1 : IN STD_LOGIC; |
|
202 | data_shaping_R1 : IN STD_LOGIC; | |
203 | sample_f0_val : OUT STD_LOGIC; |
|
203 | sample_f0_val : OUT STD_LOGIC; | |
204 | sample_f1_val : OUT STD_LOGIC; |
|
204 | sample_f1_val : OUT STD_LOGIC; | |
205 | sample_f2_val : OUT STD_LOGIC; |
|
205 | sample_f2_val : OUT STD_LOGIC; | |
206 | sample_f3_val : OUT STD_LOGIC; |
|
206 | sample_f3_val : OUT STD_LOGIC; | |
207 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
207 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
208 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
208 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
209 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
209 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
210 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); |
|
210 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); | |
211 | END COMPONENT; |
|
211 | END COMPONENT; | |
212 |
|
212 | |||
213 | COMPONENT lpp_lfr |
|
213 | COMPONENT lpp_lfr | |
214 | GENERIC ( |
|
214 | GENERIC ( | |
215 | Mem_use : INTEGER; |
|
215 | Mem_use : INTEGER; | |
216 | nb_data_by_buffer_size : INTEGER; |
|
216 | nb_data_by_buffer_size : INTEGER; | |
217 | nb_word_by_buffer_size : INTEGER; |
|
217 | nb_word_by_buffer_size : INTEGER; | |
218 | nb_snapshot_param_size : INTEGER; |
|
218 | nb_snapshot_param_size : INTEGER; | |
219 | delta_vector_size : INTEGER; |
|
219 | delta_vector_size : INTEGER; | |
220 | delta_vector_size_f0_2 : INTEGER; |
|
220 | delta_vector_size_f0_2 : INTEGER; | |
221 | pindex : INTEGER; |
|
221 | pindex : INTEGER; | |
222 | paddr : INTEGER; |
|
222 | paddr : INTEGER; | |
223 | pmask : INTEGER; |
|
223 | pmask : INTEGER; | |
224 | pirq_ms : INTEGER; |
|
224 | pirq_ms : INTEGER; | |
225 | pirq_wfp : INTEGER; |
|
225 | pirq_wfp : INTEGER; | |
226 | hindex : INTEGER; |
|
226 | hindex : INTEGER; | |
227 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
|
227 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) | |
228 | ); |
|
228 | ); | |
229 | PORT ( |
|
229 | PORT ( | |
230 | clk : IN STD_LOGIC; |
|
230 | clk : IN STD_LOGIC; | |
231 | rstn : IN STD_LOGIC; |
|
231 | rstn : IN STD_LOGIC; | |
232 | sample_B : IN Samples(2 DOWNTO 0); |
|
232 | sample_B : IN Samples(2 DOWNTO 0); | |
233 | sample_E : IN Samples(4 DOWNTO 0); |
|
233 | sample_E : IN Samples(4 DOWNTO 0); | |
234 | sample_val : IN STD_LOGIC; |
|
234 | sample_val : IN STD_LOGIC; | |
235 | apbi : IN apb_slv_in_type; |
|
235 | apbi : IN apb_slv_in_type; | |
236 | apbo : OUT apb_slv_out_type; |
|
236 | apbo : OUT apb_slv_out_type; | |
237 | ahbi : IN AHB_Mst_In_Type; |
|
237 | ahbi : IN AHB_Mst_In_Type; | |
238 | ahbo : OUT AHB_Mst_Out_Type; |
|
238 | ahbo : OUT AHB_Mst_Out_Type; | |
239 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
239 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
240 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
240 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
241 | data_shaping_BW : OUT STD_LOGIC; |
|
241 | data_shaping_BW : OUT STD_LOGIC; | |
242 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
242 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
243 | ); |
|
243 | ); | |
244 | END COMPONENT; |
|
244 | END COMPONENT; | |
245 |
|
245 | |||
246 | ----------------------------------------------------------------------------- |
|
246 | ----------------------------------------------------------------------------- | |
247 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) |
|
247 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) | |
248 | ----------------------------------------------------------------------------- |
|
248 | ----------------------------------------------------------------------------- | |
249 | COMPONENT lpp_lfr_WFP_nMS |
|
249 | COMPONENT lpp_lfr_WFP_nMS | |
250 | GENERIC ( |
|
250 | GENERIC ( | |
251 | Mem_use : INTEGER; |
|
251 | Mem_use : INTEGER; | |
252 | nb_data_by_buffer_size : INTEGER; |
|
252 | nb_data_by_buffer_size : INTEGER; | |
253 | nb_word_by_buffer_size : INTEGER; |
|
253 | nb_word_by_buffer_size : INTEGER; | |
254 | nb_snapshot_param_size : INTEGER; |
|
254 | nb_snapshot_param_size : INTEGER; | |
255 | delta_vector_size : INTEGER; |
|
255 | delta_vector_size : INTEGER; | |
256 | delta_vector_size_f0_2 : INTEGER; |
|
256 | delta_vector_size_f0_2 : INTEGER; | |
257 | pindex : INTEGER; |
|
257 | pindex : INTEGER; | |
258 | paddr : INTEGER; |
|
258 | paddr : INTEGER; | |
259 | pmask : INTEGER; |
|
259 | pmask : INTEGER; | |
260 | pirq_ms : INTEGER; |
|
260 | pirq_ms : INTEGER; | |
261 | pirq_wfp : INTEGER; |
|
261 | pirq_wfp : INTEGER; | |
262 | hindex : INTEGER; |
|
262 | hindex : INTEGER; | |
263 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
263 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
264 | PORT ( |
|
264 | PORT ( | |
265 | clk : IN STD_LOGIC; |
|
265 | clk : IN STD_LOGIC; | |
266 | rstn : IN STD_LOGIC; |
|
266 | rstn : IN STD_LOGIC; | |
267 | sample_B : IN Samples(2 DOWNTO 0); |
|
267 | sample_B : IN Samples(2 DOWNTO 0); | |
268 | sample_E : IN Samples(4 DOWNTO 0); |
|
268 | sample_E : IN Samples(4 DOWNTO 0); | |
269 | sample_val : IN STD_LOGIC; |
|
269 | sample_val : IN STD_LOGIC; | |
270 | apbi : IN apb_slv_in_type; |
|
270 | apbi : IN apb_slv_in_type; | |
271 | apbo : OUT apb_slv_out_type; |
|
271 | apbo : OUT apb_slv_out_type; | |
272 | ahbi : IN AHB_Mst_In_Type; |
|
272 | ahbi : IN AHB_Mst_In_Type; | |
273 | ahbo : OUT AHB_Mst_Out_Type; |
|
273 | ahbo : OUT AHB_Mst_Out_Type; | |
274 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
274 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
275 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
275 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
276 | data_shaping_BW : OUT STD_LOGIC; |
|
276 | data_shaping_BW : OUT STD_LOGIC; | |
277 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
277 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
278 | END COMPONENT; |
|
278 | END COMPONENT; | |
279 | ----------------------------------------------------------------------------- |
|
279 | ----------------------------------------------------------------------------- | |
280 | COMPONENT lpp_lfr_apbreg |
|
280 | COMPONENT lpp_lfr_apbreg | |
281 | GENERIC ( |
|
281 | GENERIC ( | |
282 | nb_data_by_buffer_size : INTEGER; |
|
282 | nb_data_by_buffer_size : INTEGER; | |
283 | nb_word_by_buffer_size : INTEGER; |
|
283 | nb_word_by_buffer_size : INTEGER; | |
284 | nb_snapshot_param_size : INTEGER; |
|
284 | nb_snapshot_param_size : INTEGER; | |
285 | delta_vector_size : INTEGER; |
|
285 | delta_vector_size : INTEGER; | |
286 | delta_vector_size_f0_2 : INTEGER; |
|
286 | delta_vector_size_f0_2 : INTEGER; | |
287 | pindex : INTEGER; |
|
287 | pindex : INTEGER; | |
288 | paddr : INTEGER; |
|
288 | paddr : INTEGER; | |
289 | pmask : INTEGER; |
|
289 | pmask : INTEGER; | |
290 | pirq_ms : INTEGER; |
|
290 | pirq_ms : INTEGER; | |
291 | pirq_wfp : INTEGER; |
|
291 | pirq_wfp : INTEGER; | |
292 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
292 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
293 | PORT ( |
|
293 | PORT ( | |
294 | HCLK : IN STD_ULOGIC; |
|
294 | HCLK : IN STD_ULOGIC; | |
295 | HRESETn : IN STD_ULOGIC; |
|
295 | HRESETn : IN STD_ULOGIC; | |
296 | apbi : IN apb_slv_in_type; |
|
296 | apbi : IN apb_slv_in_type; | |
297 | apbo : OUT apb_slv_out_type; |
|
297 | apbo : OUT apb_slv_out_type; | |
298 | run_ms : OUT STD_LOGIC; |
|
298 | run_ms : OUT STD_LOGIC; | |
299 |
ready_matrix_f0 |
|
299 | ready_matrix_f0 : IN STD_LOGIC; | |
300 | ready_matrix_f1 : IN STD_LOGIC; |
|
300 | ready_matrix_f1 : IN STD_LOGIC; | |
301 | ready_matrix_f2 : IN STD_LOGIC; |
|
301 | ready_matrix_f2 : IN STD_LOGIC; | |
302 | error_bad_component_error : IN STD_LOGIC; |
|
302 | error_bad_component_error : IN STD_LOGIC; | |
303 | error_buffer_full : in STD_LOGIC; |
|
303 | error_buffer_full : in STD_LOGIC; | |
304 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
304 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); | |
305 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
305 | --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
306 |
status_ready_matrix_f0 |
|
306 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
307 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
307 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
308 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
308 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
309 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
309 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
310 | config_active_interruption_onError : OUT STD_LOGIC; |
|
310 | config_active_interruption_onError : OUT STD_LOGIC; | |
311 |
addr_matrix_f0 |
|
311 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
312 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
312 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
313 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
313 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
314 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
314 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
315 |
matrix_time_f0 |
|
315 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
316 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
316 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
317 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
317 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
318 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
318 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
319 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
319 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
320 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
320 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
321 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
321 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
322 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
322 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
323 | data_shaping_BW : OUT STD_LOGIC; |
|
323 | data_shaping_BW : OUT STD_LOGIC; | |
324 | data_shaping_SP0 : OUT STD_LOGIC; |
|
324 | data_shaping_SP0 : OUT STD_LOGIC; | |
325 | data_shaping_SP1 : OUT STD_LOGIC; |
|
325 | data_shaping_SP1 : OUT STD_LOGIC; | |
326 | data_shaping_R0 : OUT STD_LOGIC; |
|
326 | data_shaping_R0 : OUT STD_LOGIC; | |
327 | data_shaping_R1 : OUT STD_LOGIC; |
|
327 | data_shaping_R1 : OUT STD_LOGIC; | |
328 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
328 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
329 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
329 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
330 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
330 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
331 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
331 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
332 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
332 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
333 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
333 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
334 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
334 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
335 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
335 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
336 | enable_f0 : OUT STD_LOGIC; |
|
336 | enable_f0 : OUT STD_LOGIC; | |
337 | enable_f1 : OUT STD_LOGIC; |
|
337 | enable_f1 : OUT STD_LOGIC; | |
338 | enable_f2 : OUT STD_LOGIC; |
|
338 | enable_f2 : OUT STD_LOGIC; | |
339 | enable_f3 : OUT STD_LOGIC; |
|
339 | enable_f3 : OUT STD_LOGIC; | |
340 | burst_f0 : OUT STD_LOGIC; |
|
340 | burst_f0 : OUT STD_LOGIC; | |
341 | burst_f1 : OUT STD_LOGIC; |
|
341 | burst_f1 : OUT STD_LOGIC; | |
342 | burst_f2 : OUT STD_LOGIC; |
|
342 | burst_f2 : OUT STD_LOGIC; | |
343 | run : OUT STD_LOGIC; |
|
343 | run : OUT STD_LOGIC; | |
344 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
344 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
345 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
345 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
346 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
346 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
347 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
347 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
348 |
start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) |
|
348 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) | |
349 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
349 | ); | |
350 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
351 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
352 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
353 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
354 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
355 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
356 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
|||
357 | END COMPONENT; |
|
350 | END COMPONENT; | |
358 |
|
351 | |||
359 |
|
352 | |||
360 |
|
353 | |||
361 | COMPONENT lpp_top_ms |
|
354 | COMPONENT lpp_top_ms | |
362 | GENERIC ( |
|
355 | GENERIC ( | |
363 | Mem_use : INTEGER; |
|
356 | Mem_use : INTEGER; | |
364 | nb_burst_available_size : INTEGER; |
|
357 | nb_burst_available_size : INTEGER; | |
365 | nb_snapshot_param_size : INTEGER; |
|
358 | nb_snapshot_param_size : INTEGER; | |
366 | delta_snapshot_size : INTEGER; |
|
359 | delta_snapshot_size : INTEGER; | |
367 | delta_f2_f0_size : INTEGER; |
|
360 | delta_f2_f0_size : INTEGER; | |
368 | delta_f2_f1_size : INTEGER; |
|
361 | delta_f2_f1_size : INTEGER; | |
369 | pindex : INTEGER; |
|
362 | pindex : INTEGER; | |
370 | paddr : INTEGER; |
|
363 | paddr : INTEGER; | |
371 | pmask : INTEGER; |
|
364 | pmask : INTEGER; | |
372 | pirq_ms : INTEGER; |
|
365 | pirq_ms : INTEGER; | |
373 | pirq_wfp : INTEGER; |
|
366 | pirq_wfp : INTEGER; | |
374 | hindex_wfp : INTEGER; |
|
367 | hindex_wfp : INTEGER; | |
375 | hindex_ms : INTEGER); |
|
368 | hindex_ms : INTEGER); | |
376 | PORT ( |
|
369 | PORT ( | |
377 | clk : IN STD_LOGIC; |
|
370 | clk : IN STD_LOGIC; | |
378 | rstn : IN STD_LOGIC; |
|
371 | rstn : IN STD_LOGIC; | |
379 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
372 | sample_B : IN Samples14v(2 DOWNTO 0); | |
380 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
373 | sample_E : IN Samples14v(4 DOWNTO 0); | |
381 | sample_val : IN STD_LOGIC; |
|
374 | sample_val : IN STD_LOGIC; | |
382 | apbi : IN apb_slv_in_type; |
|
375 | apbi : IN apb_slv_in_type; | |
383 | apbo : OUT apb_slv_out_type; |
|
376 | apbo : OUT apb_slv_out_type; | |
384 | ahbi_ms : IN AHB_Mst_In_Type; |
|
377 | ahbi_ms : IN AHB_Mst_In_Type; | |
385 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
378 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
386 | data_shaping_BW : OUT STD_LOGIC; |
|
379 | data_shaping_BW : OUT STD_LOGIC; | |
387 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
380 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
388 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
381 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
389 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
382 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
390 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
383 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |
391 |
|
384 | |||
392 | ); |
|
385 | ); | |
393 | END COMPONENT; |
|
386 | END COMPONENT; | |
|
387 | ||||
|
388 | COMPONENT lpp_apbreg_ms_pointer | |||
|
389 | PORT ( | |||
|
390 | clk : IN STD_LOGIC; | |||
|
391 | rstn : IN STD_LOGIC; | |||
|
392 | reg0_status_ready_matrix : IN STD_LOGIC; | |||
|
393 | reg0_ready_matrix : OUT STD_LOGIC; | |||
|
394 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
395 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
396 | reg1_status_ready_matrix : IN STD_LOGIC; | |||
|
397 | reg1_ready_matrix : OUT STD_LOGIC; | |||
|
398 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
399 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
|
400 | ready_matrix : IN STD_LOGIC; | |||
|
401 | status_ready_matrix : OUT STD_LOGIC; | |||
|
402 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
403 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); | |||
|
404 | END COMPONENT; | |||
394 |
|
405 | |||
395 | END lpp_lfr_pkg; |
|
406 | END lpp_lfr_pkg; |
@@ -1,8 +1,9 | |||||
1 | lpp_top_lfr_pkg.vhd |
|
1 | lpp_top_lfr_pkg.vhd | |
2 | lpp_lfr_pkg.vhd |
|
2 | lpp_lfr_pkg.vhd | |
3 | lpp_lfr_filter.vhd |
|
3 | lpp_lfr_filter.vhd | |
4 | lpp_lfr_apbreg.vhd |
|
4 | lpp_lfr_apbreg.vhd | |
|
5 | lpp_lfr_apbreg_ms_pointer.vhd | |||
5 | lpp_lfr_ms_fsmdma.vhd |
|
6 | lpp_lfr_ms_fsmdma.vhd | |
6 | lpp_lfr_ms_FFT.vhd |
|
7 | lpp_lfr_ms_FFT.vhd | |
7 | lpp_lfr_ms.vhd |
|
8 | lpp_lfr_ms.vhd | |
8 | lpp_lfr.vhd |
|
9 | lpp_lfr.vhd |
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