@@ -426,7 +426,7 BEGIN -- beh | |||
|
426 | 426 | pirq_ms => 6, |
|
427 | 427 | pirq_wfp => 14, |
|
428 | 428 | hindex => 2, |
|
429 |
top_lfr_version => X"00010 |
|
|
429 | top_lfr_version => X"00010E") -- aa.bb.cc version | |
|
430 | 430 | PORT MAP ( |
|
431 | 431 | clk => clk_25, |
|
432 | 432 | rstn => reset, |
@@ -133,14 +133,14 ARCHITECTURE beh OF lpp_lfr IS | |||
|
133 | 133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
134 | 134 | |
|
135 | 135 | -- SM |
|
136 |
SIGNAL ready_matrix_f0 |
|
|
136 | SIGNAL ready_matrix_f0 : STD_LOGIC; | |
|
137 | 137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
138 | 138 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
139 | 139 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
140 | 140 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
141 | 141 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
143 |
SIGNAL status_ready_matrix_f0 |
|
|
142 | -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
143 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; | |
|
144 | 144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
145 | 145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
146 | 146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
@@ -148,7 +148,7 ARCHITECTURE beh OF lpp_lfr IS | |||
|
148 | 148 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
149 | 149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
150 | 150 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
151 |
SIGNAL addr_matrix_f0 |
|
|
151 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
152 | 152 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
153 | 153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
154 | 154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
@@ -260,24 +260,6 ARCHITECTURE beh OF lpp_lfr IS | |||
|
260 | 260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
261 | 261 | |
|
262 | 262 | ----------------------------------------------------------------------------- |
|
263 | -- DEBUG | |
|
264 | ----------------------------------------------------------------------------- | |
|
265 | -- | |
|
266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
270 | ||
|
271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
279 | ||
|
280 | ----------------------------------------------------------------------------- | |
|
281 | 263 | -- MS |
|
282 | 264 | ----------------------------------------------------------------------------- |
|
283 | 265 | |
@@ -291,7 +273,7 ARCHITECTURE beh OF lpp_lfr IS | |||
|
291 | 273 | SIGNAL run_ms : STD_LOGIC; |
|
292 | 274 | SIGNAL ms_softandhard_rstn : STD_LOGIC; |
|
293 | 275 | |
|
294 |
SIGNAL matrix_time_f0 |
|
|
276 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
295 | 277 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
296 | 278 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
297 | 279 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
@@ -353,7 +335,7 BEGIN | |||
|
353 | 335 | |
|
354 | 336 | run_ms => run_ms, |
|
355 | 337 | |
|
356 |
ready_matrix_f0 |
|
|
338 | ready_matrix_f0 => ready_matrix_f0, | |
|
357 | 339 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
358 | 340 | ready_matrix_f1 => ready_matrix_f1, |
|
359 | 341 | ready_matrix_f2 => ready_matrix_f2, |
@@ -361,8 +343,8 BEGIN | |||
|
361 | 343 | error_bad_component_error => error_bad_component_error, |
|
362 | 344 | error_buffer_full => error_buffer_full, -- TODO |
|
363 | 345 | error_input_fifo_write => error_input_fifo_write, -- TODO |
|
364 | debug_reg => debug_reg, | |
|
365 |
status_ready_matrix_f0 |
|
|
346 | -- debug_reg => debug_reg, | |
|
347 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
|
366 | 348 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
367 | 349 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
368 | 350 | status_ready_matrix_f2 => status_ready_matrix_f2, |
@@ -371,12 +353,12 BEGIN | |||
|
371 | 353 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
372 | 354 | config_active_interruption_onError => config_active_interruption_onError, |
|
373 | 355 | |
|
374 |
matrix_time_f0 |
|
|
356 | matrix_time_f0 => matrix_time_f0, | |
|
375 | 357 | -- matrix_time_f0_1 => matrix_time_f0_1, |
|
376 | 358 | matrix_time_f1 => matrix_time_f1, |
|
377 | 359 | matrix_time_f2 => matrix_time_f2, |
|
378 | 360 | |
|
379 |
addr_matrix_f0 |
|
|
361 | addr_matrix_f0 => addr_matrix_f0, | |
|
380 | 362 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
|
381 | 363 | addr_matrix_f1 => addr_matrix_f1, |
|
382 | 364 | addr_matrix_f2 => addr_matrix_f2, |
@@ -410,27 +392,9 BEGIN | |||
|
410 | 392 | addr_data_f1 => addr_data_f1, |
|
411 | 393 | addr_data_f2 => addr_data_f2, |
|
412 | 394 | addr_data_f3 => addr_data_f3, |
|
413 |
start_date => start_date |
|
|
414 | --------------------------------------------------------------------------- | |
|
415 | debug_reg0 => debug_reg0, | |
|
416 | debug_reg1 => debug_reg1, | |
|
417 | debug_reg2 => debug_reg2, | |
|
418 | debug_reg3 => debug_reg3, | |
|
419 | debug_reg4 => debug_reg4, | |
|
420 | debug_reg5 => debug_reg5, | |
|
421 | debug_reg6 => debug_reg6, | |
|
422 | debug_reg7 => debug_reg7); | |
|
395 | start_date => start_date); | |
|
423 | 396 | |
|
424 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); | |
|
425 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); | |
|
426 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); | |
|
427 | 397 | ----------------------------------------------------------------------------- |
|
428 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug | |
|
429 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug | |
|
430 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug | |
|
431 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug | |
|
432 | ||
|
433 | ||
|
434 | 398 | ----------------------------------------------------------------------------- |
|
435 | 399 | lpp_waveform_1 : lpp_waveform |
|
436 | 400 | GENERIC MAP ( |
@@ -476,19 +440,19 BEGIN | |||
|
476 | 440 | --f0 |
|
477 | 441 | addr_data_f0 => addr_data_f0, |
|
478 | 442 | data_f0_in_valid => sample_f0_val, |
|
479 |
data_f0_in => sample_f0_data, |
|
|
443 | data_f0_in => sample_f0_data, | |
|
480 | 444 |
|
|
481 | 445 | addr_data_f1 => addr_data_f1, |
|
482 | 446 | data_f1_in_valid => sample_f1_val, |
|
483 |
data_f1_in => sample_f1_data, |
|
|
447 | data_f1_in => sample_f1_data, | |
|
484 | 448 |
|
|
485 | 449 | addr_data_f2 => addr_data_f2, |
|
486 | 450 | data_f2_in_valid => sample_f2_val, |
|
487 |
data_f2_in => sample_f2_data, |
|
|
451 | data_f2_in => sample_f2_data, | |
|
488 | 452 |
|
|
489 | 453 | addr_data_f3 => addr_data_f3, |
|
490 | 454 | data_f3_in_valid => sample_f3_val, |
|
491 |
data_f3_in => sample_f3_data, |
|
|
455 | data_f3_in => sample_f3_data, | |
|
492 | 456 |
|
|
493 | 457 | --f0 |
|
494 | 458 | data_f0_addr_out => data_f0_addr_out_s, |
@@ -663,21 +627,6 BEGIN | |||
|
663 | 627 | dma_data_2 <= dma_data; |
|
664 | 628 | |
|
665 | 629 | |
|
666 | ||
|
667 | ||
|
668 | ||
|
669 | ----------------------------------------------------------------------------- | |
|
670 | -- DEBUG -- DMA IN | |
|
671 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; | |
|
672 | --debug_f0_data_dma_in <= dma_data; | |
|
673 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; | |
|
674 | --debug_f1_data_dma_in <= dma_data; | |
|
675 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; | |
|
676 | --debug_f2_data_dma_in <= dma_data; | |
|
677 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; | |
|
678 | --debug_f3_data_dma_in <= dma_data; | |
|
679 | ----------------------------------------------------------------------------- | |
|
680 | ||
|
681 | 630 | ----------------------------------------------------------------------------- |
|
682 | 631 | -- DMA |
|
683 | 632 | ----------------------------------------------------------------------------- |
@@ -732,8 +681,8 BEGIN | |||
|
732 | 681 | sample_f0_wdata => sample_f0_wdata, |
|
733 | 682 | sample_f1_wen => sample_f1_wen, |
|
734 | 683 | sample_f1_wdata => sample_f1_wdata, |
|
735 |
sample_f2_wen => sample_f3_wen, -- TODO |
|
|
736 |
sample_f2_wdata => sample_f3_wdata,-- TODO |
|
|
684 | sample_f2_wen => sample_f3_wen, -- TODO | |
|
685 | sample_f2_wdata => sample_f3_wdata,-- TODO | |
|
737 | 686 | |
|
738 | 687 | dma_addr => data_ms_addr, -- |
|
739 | 688 | dma_data => data_ms_data, -- |
@@ -742,29 +691,26 BEGIN | |||
|
742 | 691 | dma_ren => data_ms_ren, -- |
|
743 | 692 | dma_done => data_ms_done, -- |
|
744 | 693 | |
|
745 |
ready_matrix_f0 => ready_matrix_f0 |
|
|
694 | ready_matrix_f0 => ready_matrix_f0, | |
|
746 | 695 | ready_matrix_f1 => ready_matrix_f1, |
|
747 | 696 | ready_matrix_f2 => ready_matrix_f2, |
|
748 | --error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
749 | 697 | error_bad_component_error => error_bad_component_error, |
|
750 |
error_buffer_full => error_buffer_full, |
|
|
751 |
|
|
|
698 | error_buffer_full => error_buffer_full, | |
|
699 | error_input_fifo_write => error_input_fifo_write, | |
|
752 | 700 |
|
|
753 | 701 | debug_reg => observation_reg, |
|
754 | 702 | |
|
755 |
status_ready_matrix_f0 => status_ready_matrix_f0 |
|
|
703 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
|
756 | 704 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
757 | 705 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
758 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO | |
|
759 | -- status_error_bad_component_error => status_error_bad_component_error,-- TODO | |
|
760 | 706 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
761 | 707 | config_active_interruption_onError => config_active_interruption_onError, |
|
762 |
addr_matrix_f0 => addr_matrix_f0 |
|
|
708 | addr_matrix_f0 => addr_matrix_f0, | |
|
763 | 709 | addr_matrix_f1 => addr_matrix_f1, |
|
764 | 710 | addr_matrix_f2 => addr_matrix_f2, |
|
765 | 711 | |
|
766 |
matrix_time_f0 => matrix_time_f0 |
|
|
712 | matrix_time_f0 => matrix_time_f0, | |
|
767 | 713 | matrix_time_f1 => matrix_time_f1, |
|
768 | 714 | matrix_time_f2 => matrix_time_f2); |
|
769 | 715 | |
|
770 | END beh; No newline at end of file | |
|
716 | END beh; |
This diff has been collapsed as it changes many lines, (706 lines changed) Show them Hide them | |||
@@ -28,6 +28,7 USE grlib.amba.ALL; | |||
|
28 | 28 | USE grlib.stdlib.ALL; |
|
29 | 29 | USE grlib.devices.ALL; |
|
30 | 30 | LIBRARY lpp; |
|
31 | USE lpp.lpp_lfr_pkg.ALL; | |
|
31 | 32 | USE lpp.lpp_amba.ALL; |
|
32 | 33 | USE lpp.apb_devices_list.ALL; |
|
33 | 34 | USE lpp.lpp_memory.ALL; |
@@ -38,16 +39,16 ENTITY lpp_lfr_apbreg IS | |||
|
38 | 39 | GENERIC ( |
|
39 | 40 | nb_data_by_buffer_size : INTEGER := 11; |
|
40 | 41 | nb_word_by_buffer_size : INTEGER := 11; |
|
41 |
nb_snapshot_param_size |
|
|
42 |
delta_vector_size |
|
|
43 |
delta_vector_size_f0_2 |
|
|
42 | nb_snapshot_param_size : INTEGER := 11; | |
|
43 | delta_vector_size : INTEGER := 20; | |
|
44 | delta_vector_size_f0_2 : INTEGER := 3; | |
|
44 | 45 | |
|
45 | pindex : INTEGER := 4; | |
|
46 | paddr : INTEGER := 4; | |
|
47 | pmask : INTEGER := 16#fff#; | |
|
48 | pirq_ms : INTEGER := 0; | |
|
49 | pirq_wfp : INTEGER := 1; | |
|
50 |
top_lfr_version |
|
|
46 | pindex : INTEGER := 4; | |
|
47 | paddr : INTEGER := 4; | |
|
48 | pmask : INTEGER := 16#fff#; | |
|
49 | pirq_ms : INTEGER := 0; | |
|
50 | pirq_wfp : INTEGER := 1; | |
|
51 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); | |
|
51 | 52 | PORT ( |
|
52 | 53 | -- AMBA AHB system signals |
|
53 | 54 | HCLK : IN STD_ULOGIC; |
@@ -59,44 +60,42 ENTITY lpp_lfr_apbreg IS | |||
|
59 | 60 | |
|
60 | 61 | --------------------------------------------------------------------------- |
|
61 | 62 | -- Spectral Matrix Reg |
|
62 |
run_ms |
|
|
63 | run_ms : OUT STD_LOGIC; | |
|
63 | 64 | -- IN |
|
64 |
ready_matrix_f0 |
|
|
65 |
ready_matrix_f1 |
|
|
66 |
ready_matrix_f2 |
|
|
65 | ready_matrix_f0 : IN STD_LOGIC; | |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
|
67 | 68 | |
|
68 |
error_bad_component_error |
|
|
69 |
error_buffer_full |
|
|
70 |
error_input_fifo_write |
|
|
69 | error_bad_component_error : IN STD_LOGIC; | |
|
70 | error_buffer_full : IN STD_LOGIC; -- TODO | |
|
71 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO | |
|
71 | 72 | |
|
72 |
debug_reg |
|
|
73 | -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
73 | 74 | |
|
74 | 75 | -- OUT |
|
75 |
status_ready_matrix_f0 |
|
|
76 |
status_ready_matrix_f1 |
|
|
77 |
status_ready_matrix_f2 |
|
|
76 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
|
77 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
|
78 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
|
78 | 79 | |
|
79 | 80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
80 | 81 | config_active_interruption_onError : OUT STD_LOGIC; |
|
81 | ||
|
82 |
addr_matrix_f0 |
|
|
83 |
|
|
|
84 |
addr_matrix_f |
|
|
85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | ||
|
87 |
matrix_time_f |
|
|
88 |
|
|
|
89 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
91 | ||
|
82 | ||
|
83 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | ||
|
87 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
88 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
89 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | ||
|
92 | 91 | --------------------------------------------------------------------------- |
|
93 | 92 | --------------------------------------------------------------------------- |
|
94 | 93 | -- WaveForm picker Reg |
|
95 |
status_full |
|
|
96 |
status_full_ack |
|
|
97 |
status_full_err |
|
|
98 |
status_new_err |
|
|
99 | ||
|
94 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
95 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
96 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
97 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
98 | ||
|
100 | 99 | -- OUT |
|
101 | 100 | data_shaping_BW : OUT STD_LOGIC; |
|
102 | 101 | data_shaping_SP0 : OUT STD_LOGIC; |
@@ -104,14 +103,14 ENTITY lpp_lfr_apbreg IS | |||
|
104 | 103 | data_shaping_R0 : OUT STD_LOGIC; |
|
105 | 104 | data_shaping_R1 : OUT STD_LOGIC; |
|
106 | 105 | |
|
107 |
delta_snapshot |
|
|
108 |
delta_f0 |
|
|
109 |
delta_f0_2 |
|
|
110 |
delta_f1 |
|
|
111 |
delta_f2 |
|
|
106 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
107 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
108 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
109 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
110 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
112 | 111 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
113 | 112 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
114 |
nb_snapshot_param |
|
|
113 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
115 | 114 | |
|
116 | 115 | enable_f0 : OUT STD_LOGIC; |
|
117 | 116 | enable_f1 : OUT STD_LOGIC; |
@@ -128,17 +127,7 ENTITY lpp_lfr_apbreg IS | |||
|
128 | 127 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
129 | 128 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
130 | 129 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
131 |
start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) |
|
|
132 | --------------------------------------------------------------------------- | |
|
133 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
134 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
135 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
136 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
137 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
138 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
139 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
140 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
141 | ||
|
130 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) | |
|
142 | 131 | --------------------------------------------------------------------------- |
|
143 | 132 | ); |
|
144 | 133 | |
@@ -157,60 +146,61 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
157 | 146 | config_active_interruption_onError : STD_LOGIC; |
|
158 | 147 | config_ms_run : STD_LOGIC; |
|
159 | 148 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
160 |
|
|
|
161 |
status_ready_matrix_f |
|
|
162 |
status_ready_matrix_f |
|
|
163 | -- status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
149 | status_ready_matrix_f1_0 : STD_LOGIC; | |
|
150 | status_ready_matrix_f2_0 : STD_LOGIC; | |
|
151 | status_ready_matrix_f0_1 : STD_LOGIC; | |
|
152 | status_ready_matrix_f1_1 : STD_LOGIC; | |
|
153 | status_ready_matrix_f2_1 : STD_LOGIC; | |
|
164 | 154 | status_error_bad_component_error : STD_LOGIC; |
|
165 |
status_error_buffer_full : STD_LOGIC; |
|
|
166 |
status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
|
155 | status_error_buffer_full : STD_LOGIC; | |
|
156 | status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
157 | ||
|
167 | 158 |
|
|
168 |
|
|
|
169 |
addr_matrix_f1 |
|
|
170 |
addr_matrix_f |
|
|
159 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
160 | addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
161 | addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
162 | addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
163 | addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
171 | 164 | |
|
172 |
|
|
|
173 |
|
|
|
174 |
|
|
|
175 |
|
|
|
176 | ||
|
177 |
|
|
|
178 | -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
179 | -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
180 | -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
165 | time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
166 | time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
167 | time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
168 | time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
169 | time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
170 | time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
181 | 171 | END RECORD; |
|
182 | 172 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
183 | 173 | |
|
184 | 174 | TYPE lpp_WaveformPicker_regs IS RECORD |
|
185 |
status_full |
|
|
186 |
status_full_err |
|
|
187 |
status_new_err |
|
|
188 |
data_shaping_BW |
|
|
189 |
data_shaping_SP0 |
|
|
190 |
data_shaping_SP1 |
|
|
191 |
data_shaping_R0 |
|
|
192 |
data_shaping_R1 |
|
|
193 |
delta_snapshot |
|
|
194 |
delta_f0 |
|
|
175 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
176 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
177 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
178 | data_shaping_BW : STD_LOGIC; | |
|
179 | data_shaping_SP0 : STD_LOGIC; | |
|
180 | data_shaping_SP1 : STD_LOGIC; | |
|
181 | data_shaping_R0 : STD_LOGIC; | |
|
182 | data_shaping_R1 : STD_LOGIC; | |
|
183 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
184 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
195 | 185 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
196 |
delta_f1 |
|
|
197 |
delta_f2 |
|
|
186 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
187 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
198 | 188 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
199 | 189 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
200 |
nb_snapshot_param |
|
|
201 |
enable_f0 |
|
|
202 |
enable_f1 |
|
|
203 |
enable_f2 |
|
|
204 |
enable_f3 |
|
|
205 |
burst_f0 |
|
|
206 |
burst_f1 |
|
|
207 |
burst_f2 |
|
|
208 |
run |
|
|
209 |
addr_data_f0 |
|
|
210 |
addr_data_f1 |
|
|
211 |
addr_data_f2 |
|
|
212 |
addr_data_f3 |
|
|
213 |
start_date |
|
|
190 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
191 | enable_f0 : STD_LOGIC; | |
|
192 | enable_f1 : STD_LOGIC; | |
|
193 | enable_f2 : STD_LOGIC; | |
|
194 | enable_f3 : STD_LOGIC; | |
|
195 | burst_f0 : STD_LOGIC; | |
|
196 | burst_f1 : STD_LOGIC; | |
|
197 | burst_f2 : STD_LOGIC; | |
|
198 | run : STD_LOGIC; | |
|
199 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
200 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
201 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
202 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
203 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
214 | 204 | END RECORD; |
|
215 | 205 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
|
216 | 206 | |
@@ -219,28 +209,53 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
219 | 209 | ----------------------------------------------------------------------------- |
|
220 | 210 | -- IRQ |
|
221 | 211 | ----------------------------------------------------------------------------- |
|
222 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
|
223 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
224 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
225 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
226 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
227 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
|
212 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
|
213 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
214 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
215 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
216 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
217 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
|
218 | ||
|
219 | ----------------------------------------------------------------------------- | |
|
220 | -- | |
|
221 | ----------------------------------------------------------------------------- | |
|
222 | SIGNAL reg0_ready_matrix_f0 : STD_LOGIC; | |
|
223 | SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
224 | SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
225 | ||
|
226 | SIGNAL reg1_ready_matrix_f0 : STD_LOGIC; | |
|
227 | SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
228 | SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
229 | ||
|
230 | SIGNAL reg0_ready_matrix_f1 : STD_LOGIC; | |
|
231 | SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
232 | SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
233 | ||
|
234 | SIGNAL reg1_ready_matrix_f1 : STD_LOGIC; | |
|
235 | SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
236 | SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
237 | ||
|
238 | SIGNAL reg0_ready_matrix_f2 : STD_LOGIC; | |
|
239 | SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
240 | SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
241 | ||
|
242 | SIGNAL reg1_ready_matrix_f2 : STD_LOGIC; | |
|
243 | SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
244 | SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
228 | 245 |
|
|
229 | 246 | BEGIN -- beh |
|
230 | 247 | |
|
231 |
status_ready_matrix_f0 |
|
|
232 |
-- status_ready_matrix_f |
|
|
233 |
status_ready_matrix_f |
|
|
234 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
|
235 | -- status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
|
236 | -- status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
|
248 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; | |
|
249 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
|
250 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
|
237 | 251 | |
|
238 | 252 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; |
|
239 | 253 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; |
|
240 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |
|
241 | -- addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
|
242 |
addr_matrix_f |
|
|
243 |
addr_matrix_f |
|
|
254 | ||
|
255 | ||
|
256 | -- addr_matrix_f0 <= reg_sp.addr_matrix_f0; | |
|
257 | -- addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
|
258 | -- addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
|
244 | 259 | |
|
245 | 260 | |
|
246 | 261 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; |
@@ -249,14 +264,14 BEGIN -- beh | |||
|
249 | 264 | data_shaping_R0 <= reg_wp.data_shaping_R0; |
|
250 | 265 | data_shaping_R1 <= reg_wp.data_shaping_R1; |
|
251 | 266 | |
|
252 |
delta_snapshot |
|
|
253 |
delta_f0 |
|
|
254 |
delta_f0_2 |
|
|
255 |
delta_f1 |
|
|
256 |
delta_f2 |
|
|
267 | delta_snapshot <= reg_wp.delta_snapshot; | |
|
268 | delta_f0 <= reg_wp.delta_f0; | |
|
269 | delta_f0_2 <= reg_wp.delta_f0_2; | |
|
270 | delta_f1 <= reg_wp.delta_f1; | |
|
271 | delta_f2 <= reg_wp.delta_f2; | |
|
257 | 272 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; |
|
258 | 273 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; |
|
259 |
nb_snapshot_param |
|
|
274 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
|
260 | 275 | |
|
261 | 276 | enable_f0 <= reg_wp.enable_f0; |
|
262 | 277 | enable_f1 <= reg_wp.enable_f1; |
@@ -284,99 +299,99 BEGIN -- beh | |||
|
284 | 299 | reg_sp.config_active_interruption_onError <= '0'; |
|
285 | 300 | reg_sp.config_ms_run <= '1'; |
|
286 | 301 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
|
287 |
|
|
|
288 |
reg_sp.status_ready_matrix_f |
|
|
289 |
reg_sp.status_ready_matrix_f |
|
|
290 |
|
|
|
302 | reg_sp.status_ready_matrix_f1_0 <= '0'; | |
|
303 | reg_sp.status_ready_matrix_f2_0 <= '0'; | |
|
304 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
|
305 | reg_sp.status_ready_matrix_f1_1 <= '0'; | |
|
306 | reg_sp.status_ready_matrix_f2_1 <= '0'; | |
|
291 | 307 | reg_sp.status_error_bad_component_error <= '0'; |
|
292 | 308 | reg_sp.status_error_buffer_full <= '0'; |
|
293 | 309 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); |
|
294 | ||
|
295 |
reg_sp.addr_matrix_f0_0 |
|
|
296 |
|
|
|
297 |
reg_sp.addr_matrix_f |
|
|
298 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
|
310 | ||
|
311 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
|
312 | reg_sp.addr_matrix_f1_0 <= (OTHERS => '0'); | |
|
313 | reg_sp.addr_matrix_f2_0 <= (OTHERS => '0'); | |
|
314 | ||
|
315 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
|
316 | reg_sp.addr_matrix_f1_1 <= (OTHERS => '0'); | |
|
317 | reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); | |
|
299 | 318 | |
|
300 |
reg_sp. |
|
|
301 |
|
|
|
302 |
reg_sp. |
|
|
303 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); | |
|
304 |
|
|
|
305 |
|
|
|
306 |
|
|
|
307 | --reg_sp.fine_time_f2 <= (OTHERS => '0'); | |
|
308 | ||
|
309 | prdata <= (OTHERS => '0'); | |
|
319 | reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok | |
|
320 | reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok | |
|
321 | reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok | |
|
322 | ||
|
323 | reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok | |
|
324 | reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok | |
|
325 | reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok | |
|
326 | ||
|
327 | prdata <= (OTHERS => '0'); | |
|
310 | 328 | |
|
311 | 329 | apbo.pirq <= (OTHERS => '0'); |
|
312 | 330 | |
|
313 | 331 | status_full_ack <= (OTHERS => '0'); |
|
314 | 332 | |
|
315 |
reg_wp.data_shaping_BW |
|
|
316 |
reg_wp.data_shaping_SP0 |
|
|
317 |
reg_wp.data_shaping_SP1 |
|
|
318 |
reg_wp.data_shaping_R0 |
|
|
319 |
reg_wp.data_shaping_R1 |
|
|
320 |
reg_wp.enable_f0 |
|
|
321 |
reg_wp.enable_f1 |
|
|
322 |
reg_wp.enable_f2 |
|
|
323 |
reg_wp.enable_f3 |
|
|
324 |
reg_wp.burst_f0 |
|
|
325 |
reg_wp.burst_f1 |
|
|
326 |
reg_wp.burst_f2 |
|
|
327 |
reg_wp.run |
|
|
328 |
reg_wp.addr_data_f0 |
|
|
329 |
reg_wp.addr_data_f1 |
|
|
330 |
reg_wp.addr_data_f2 |
|
|
331 |
reg_wp.addr_data_f3 |
|
|
332 |
reg_wp.status_full |
|
|
333 |
reg_wp.status_full_err |
|
|
334 |
reg_wp.status_new_err |
|
|
335 |
reg_wp.delta_snapshot |
|
|
336 |
reg_wp.delta_f0 |
|
|
337 |
reg_wp.delta_f0_2 |
|
|
338 |
reg_wp.delta_f1 |
|
|
339 |
reg_wp.delta_f2 |
|
|
333 | reg_wp.data_shaping_BW <= '0'; | |
|
334 | reg_wp.data_shaping_SP0 <= '0'; | |
|
335 | reg_wp.data_shaping_SP1 <= '0'; | |
|
336 | reg_wp.data_shaping_R0 <= '0'; | |
|
337 | reg_wp.data_shaping_R1 <= '0'; | |
|
338 | reg_wp.enable_f0 <= '0'; | |
|
339 | reg_wp.enable_f1 <= '0'; | |
|
340 | reg_wp.enable_f2 <= '0'; | |
|
341 | reg_wp.enable_f3 <= '0'; | |
|
342 | reg_wp.burst_f0 <= '0'; | |
|
343 | reg_wp.burst_f1 <= '0'; | |
|
344 | reg_wp.burst_f2 <= '0'; | |
|
345 | reg_wp.run <= '0'; | |
|
346 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
|
347 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
|
348 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
|
349 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
|
350 | reg_wp.status_full <= (OTHERS => '0'); | |
|
351 | reg_wp.status_full_err <= (OTHERS => '0'); | |
|
352 | reg_wp.status_new_err <= (OTHERS => '0'); | |
|
353 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
|
354 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
|
355 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
|
356 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
|
357 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
|
340 | 358 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); |
|
341 |
reg_wp.nb_snapshot_param |
|
|
342 |
reg_wp.start_date |
|
|
359 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
|
360 | reg_wp.start_date <= (OTHERS => '0'); | |
|
343 | 361 | |
|
344 | 362 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
345 | 363 | |
|
346 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); | |
|
347 | -- reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
|
348 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); | |
|
349 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); | |
|
350 | ||
|
351 | --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); | |
|
352 | --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); | |
|
353 | --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); | |
|
354 | --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); | |
|
355 | ||
|
364 | reg_sp.time_matrix_f0_0 <= reg0_matrix_time_f0; -- ok | |
|
365 | reg_sp.time_matrix_f1_0 <= reg0_matrix_time_f1; -- ok | |
|
366 | reg_sp.time_matrix_f2_0 <= reg0_matrix_time_f2; -- ok | |
|
367 | ||
|
368 | reg_sp.time_matrix_f0_1 <= reg1_matrix_time_f0; -- ok | |
|
369 | reg_sp.time_matrix_f1_1 <= reg1_matrix_time_f1; -- ok | |
|
370 | reg_sp.time_matrix_f2_1 <= reg1_matrix_time_f2; -- ok | |
|
371 | ||
|
356 | 372 | status_full_ack <= (OTHERS => '0'); |
|
357 | 373 | |
|
358 |
reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0 |
|
|
359 |
|
|
|
360 |
reg_sp.status_ready_matrix_f |
|
|
361 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
|
374 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0; | |
|
375 | reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1; | |
|
376 | reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2; | |
|
362 | 377 | |
|
363 | -- reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
|
364 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
365 | ||
|
366 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; | |
|
367 |
reg_sp.status_error_ |
|
|
368 | reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1); | |
|
369 |
reg_sp.status_error_ |
|
|
378 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0; | |
|
379 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; | |
|
380 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; | |
|
381 | ||
|
382 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
383 | ||
|
384 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; | |
|
385 | reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); | |
|
386 | reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1); | |
|
387 | reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2); | |
|
370 | 388 | |
|
371 | 389 | |
|
372 | ||
|
373 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
|
374 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
|
375 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
|
376 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
|
390 | ||
|
391 | all_status : FOR I IN 3 DOWNTO 0 LOOP | |
|
377 | 392 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; |
|
378 |
reg_wp.status_full_err(I) <= status_full_err(I) |
|
|
379 |
reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run |
|
|
393 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
|
394 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run; | |
|
380 | 395 | END LOOP all_status; |
|
381 | 396 | |
|
382 | 397 | paddr := "000000"; |
@@ -385,42 +400,67 BEGIN -- beh | |||
|
385 | 400 | IF apbi.psel(pindex) = '1' THEN |
|
386 | 401 | -- APB DMA READ -- |
|
387 | 402 | CASE paddr(7 DOWNTO 2) IS |
|
388 | -- | |
|
403 | --0 | |
|
389 | 404 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; |
|
390 | 405 | prdata(1) <= reg_sp.config_active_interruption_onError; |
|
391 | 406 | prdata(2) <= reg_sp.config_ms_run; |
|
407 | --1 | |
|
392 | 408 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
393 |
|
|
|
394 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
|
395 |
prdata(3) <= reg_sp.status_ready_matrix_f |
|
|
396 |
|
|
|
397 |
prdata(5) <= reg_sp.status_ |
|
|
398 |
prdata(6) <= reg_sp.status_error_b |
|
|
399 |
prdata(7) <= reg_sp.status_error_ |
|
|
400 |
prdata(8) <= reg_sp.status_error_input_fifo_write( |
|
|
401 |
prdata(9) <= reg_sp.status_error_input_fifo_write( |
|
|
402 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
|
403 | -- WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
404 |
WHEN "000 |
|
|
405 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
|
406 | ||
|
407 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; | |
|
408 |
|
|
|
409 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; | |
|
410 |
WHEN "00 |
|
|
411 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; | |
|
412 | -- WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; | |
|
413 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; | |
|
414 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; | |
|
415 | ||
|
416 | WHEN "001111" => prdata <= debug_reg; | |
|
417 | --------------------------------------------------------------------- | |
|
418 |
WHEN "0 |
|
|
409 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
410 | prdata(2) <= reg_sp.status_ready_matrix_f1_0; | |
|
411 | prdata(3) <= reg_sp.status_ready_matrix_f1_1; | |
|
412 | prdata(4) <= reg_sp.status_ready_matrix_f2_0; | |
|
413 | prdata(5) <= reg_sp.status_ready_matrix_f2_1; | |
|
414 | prdata(6) <= reg_sp.status_error_bad_component_error; | |
|
415 | prdata(7) <= reg_sp.status_error_buffer_full; | |
|
416 | prdata(8) <= reg_sp.status_error_input_fifo_write(0); | |
|
417 | prdata(9) <= reg_sp.status_error_input_fifo_write(1); | |
|
418 | prdata(10) <= reg_sp.status_error_input_fifo_write(2); | |
|
419 | --2 | |
|
420 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
|
421 | --3 | |
|
422 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
423 | --4 | |
|
424 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0; | |
|
425 | --5 | |
|
426 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1; | |
|
427 | --6 | |
|
428 | WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0; | |
|
429 | --7 | |
|
430 | WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1; | |
|
431 | --8 | |
|
432 | WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16); | |
|
433 | --9 | |
|
434 | WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0); | |
|
435 | --10 | |
|
436 | WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16); | |
|
437 | --11 | |
|
438 | WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0); | |
|
439 | --12 | |
|
440 | WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16); | |
|
441 | --13 | |
|
442 | WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0); | |
|
443 | --14 | |
|
444 | WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16); | |
|
445 | --15 | |
|
446 | WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0); | |
|
447 | --16 | |
|
448 | WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16); | |
|
449 | --17 | |
|
450 | WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0); | |
|
451 | --18 | |
|
452 | WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); | |
|
453 | --19 | |
|
454 | WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); | |
|
455 | --------------------------------------------------------------------- | |
|
456 | --20 | |
|
457 | WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW; | |
|
419 | 458 | prdata(1) <= reg_wp.data_shaping_SP0; |
|
420 | 459 | prdata(2) <= reg_wp.data_shaping_SP1; |
|
421 | 460 | prdata(3) <= reg_wp.data_shaping_R0; |
|
422 | 461 | prdata(4) <= reg_wp.data_shaping_R1; |
|
423 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; | |
|
462 | --21 | |
|
463 | WHEN "010101" => prdata(0) <= reg_wp.enable_f0; | |
|
424 | 464 | prdata(1) <= reg_wp.enable_f1; |
|
425 | 465 | prdata(2) <= reg_wp.enable_f2; |
|
426 | 466 | prdata(3) <= reg_wp.enable_f3; |
@@ -428,33 +468,38 BEGIN -- beh | |||
|
428 | 468 | prdata(5) <= reg_wp.burst_f1; |
|
429 | 469 | prdata(6) <= reg_wp.burst_f2; |
|
430 | 470 | prdata(7) <= reg_wp.run; |
|
431 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; | |
|
432 |
WHEN "010 |
|
|
433 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; | |
|
434 |
WHEN "0101 |
|
|
435 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
|
471 | --22 | |
|
472 | WHEN "010110" => prdata <= reg_wp.addr_data_f0; | |
|
473 | --23 | |
|
474 | WHEN "010111" => prdata <= reg_wp.addr_data_f1; | |
|
475 | --24 | |
|
476 | WHEN "011000" => prdata <= reg_wp.addr_data_f2; | |
|
477 | --25 | |
|
478 | WHEN "011001" => prdata <= reg_wp.addr_data_f3; | |
|
479 | --26 | |
|
480 | WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
|
436 | 481 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
|
437 | 482 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; |
|
438 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
|
439 |
WHEN "0110 |
|
|
440 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
|
441 |
WHEN "011 |
|
|
442 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
|
443 |
WHEN "01110 |
|
|
444 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
|
445 |
WHEN "011110" => prdata( |
|
|
446 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
447 | ---------------------------------------------------- | |
|
448 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); | |
|
449 |
WHEN "10000 |
|
|
450 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); | |
|
451 |
WHEN "1000 |
|
|
452 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); | |
|
453 |
WHEN "100 |
|
|
454 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); | |
|
455 |
WHEN "100 |
|
|
456 | ---------------------------------------------------- | |
|
457 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
|
483 | --27 | |
|
484 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
|
485 | --28 | |
|
486 | WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
|
487 | --29 | |
|
488 | WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
|
489 | --30 | |
|
490 | WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
|
491 | --31 | |
|
492 | WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
|
493 | --32 | |
|
494 | WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
|
495 | --33 | |
|
496 | WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
|
497 | --34 | |
|
498 | WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
|
499 | --35 | |
|
500 | WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
501 | ---------------------------------------------------- | |
|
502 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
|
458 | 503 | WHEN OTHERS => NULL; |
|
459 | 504 | |
|
460 | 505 | END CASE; |
@@ -465,27 +510,32 BEGIN -- beh | |||
|
465 | 510 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
466 | 511 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
467 | 512 | reg_sp.config_ms_run <= apbi.pwdata(2); |
|
468 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
|
469 |
|
|
|
470 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
|
471 |
reg_sp.status_ready_matrix_f |
|
|
472 |
|
|
|
473 |
reg_sp.status_ |
|
|
474 |
reg_sp.status_error_b |
|
|
475 |
reg_sp.status_error_ |
|
|
476 |
reg_sp.status_error_input_fifo_write( |
|
|
477 |
reg_sp.status_error_input_fifo_write( |
|
|
478 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
479 | -- WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
480 |
WHEN "000 |
|
|
481 |
WHEN "000 |
|
|
482 | -- | |
|
483 |
WHEN "0 |
|
|
513 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
|
514 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
|
515 | reg_sp.status_ready_matrix_f1_0 <= apbi.pwdata(2); | |
|
516 | reg_sp.status_ready_matrix_f1_1 <= apbi.pwdata(3); | |
|
517 | reg_sp.status_ready_matrix_f2_0 <= apbi.pwdata(4); | |
|
518 | reg_sp.status_ready_matrix_f2_1 <= apbi.pwdata(5); | |
|
519 | reg_sp.status_error_bad_component_error <= apbi.pwdata(6); | |
|
520 | reg_sp.status_error_buffer_full <= apbi.pwdata(7); | |
|
521 | reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(8); | |
|
522 | reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(9); | |
|
523 | reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(10); | |
|
524 | --2 | |
|
525 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
526 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
527 | WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata; | |
|
528 | WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata; | |
|
529 | WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata; | |
|
530 | WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; | |
|
531 | --8 to 19 | |
|
532 | --20 | |
|
533 | WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
|
484 | 534 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
|
485 | 535 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); |
|
486 | 536 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
|
487 | 537 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); |
|
488 |
WHEN "010 |
|
|
538 | WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
|
489 | 539 | reg_wp.enable_f1 <= apbi.pwdata(1); |
|
490 | 540 | reg_wp.enable_f2 <= apbi.pwdata(2); |
|
491 | 541 | reg_wp.enable_f3 <= apbi.pwdata(3); |
@@ -493,46 +543,46 BEGIN -- beh | |||
|
493 | 543 | reg_wp.burst_f1 <= apbi.pwdata(5); |
|
494 | 544 | reg_wp.burst_f2 <= apbi.pwdata(6); |
|
495 | 545 | reg_wp.run <= apbi.pwdata(7); |
|
496 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
|
497 |
WHEN "010 |
|
|
498 |
WHEN "0101 |
|
|
499 |
WHEN "01 |
|
|
500 |
WHEN "0101 |
|
|
546 | --22 | |
|
547 | WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
|
548 | WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
|
549 | WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
|
550 | WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
|
551 | --26 | |
|
552 | WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
|
501 | 553 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
|
502 | 554 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
|
503 | 555 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); |
|
504 | 556 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); |
|
505 | 557 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); |
|
506 | 558 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); |
|
507 |
WHEN "01 |
|
|
508 |
WHEN "011 |
|
|
509 |
WHEN "011 |
|
|
510 |
WHEN "011 |
|
|
511 |
WHEN "011 |
|
|
512 |
WHEN " |
|
|
513 |
WHEN " |
|
|
514 |
WHEN " |
|
|
515 |
WHEN " |
|
|
559 | WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
560 | WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
561 | WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
562 | WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
563 | WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
564 | WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
565 | WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
|
566 | WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
|
567 | WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
516 | 568 | -- |
|
517 | 569 | WHEN OTHERS => NULL; |
|
518 | 570 | END CASE; |
|
519 | 571 | END IF; |
|
520 | 572 | END IF; |
|
521 | 573 | |
|
522 |
apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 |
|
|
523 | -- ready_matrix_f0_1 OR | |
|
574 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR | |
|
524 | 575 | ready_matrix_f1 OR |
|
525 | 576 | ready_matrix_f2) |
|
526 | ) | |
|
527 | OR | |
|
528 | (reg_sp.config_active_interruption_onError AND ( | |
|
529 |
|
|
|
530 | error_bad_component_error | |
|
531 | OR error_buffer_full | |
|
532 |
|
|
|
533 |
|
|
|
534 | OR error_input_fifo_write(2)) | |
|
535 | )); | |
|
577 | ) | |
|
578 | OR | |
|
579 | (reg_sp.config_active_interruption_onError AND ( | |
|
580 | error_bad_component_error | |
|
581 | OR error_buffer_full | |
|
582 | OR error_input_fifo_write(0) | |
|
583 | OR error_input_fifo_write(1) | |
|
584 | OR error_input_fifo_write(2)) | |
|
585 | )); | |
|
536 | 586 | |
|
537 | 587 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; |
|
538 | 588 | |
@@ -547,17 +597,17 BEGIN -- beh | |||
|
547 | 597 | -- IRQ |
|
548 | 598 | ----------------------------------------------------------------------------- |
|
549 | 599 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; |
|
550 | ||
|
600 | ||
|
551 | 601 | PROCESS (HCLK, HRESETn) |
|
552 | 602 | BEGIN -- PROCESS |
|
553 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
554 |
irq_wfp_reg |
|
|
555 |
ELSIF HCLK' |
|
|
556 |
irq_wfp_reg <= irq_wfp_reg_s; |
|
|
603 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
604 | irq_wfp_reg <= (OTHERS => '0'); | |
|
605 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
606 | irq_wfp_reg <= irq_wfp_reg_s; | |
|
557 | 607 | END IF; |
|
558 | 608 | END PROCESS; |
|
559 | 609 | |
|
560 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
|
610 | all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
|
561 | 611 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); |
|
562 | 612 | END GENERATE all_irq_wfp; |
|
563 | 613 | |
@@ -565,5 +615,69 BEGIN -- beh | |||
|
565 | 615 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; |
|
566 | 616 | |
|
567 | 617 | run_ms <= reg_sp.config_ms_run; |
|
618 | ||
|
619 | ----------------------------------------------------------------------------- | |
|
620 | -- | |
|
621 | ----------------------------------------------------------------------------- | |
|
622 | lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer | |
|
623 | PORT MAP ( | |
|
624 | clk => HCLK, | |
|
625 | rstn => HRESETn, | |
|
626 | ||
|
627 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, | |
|
628 | reg0_ready_matrix => reg0_ready_matrix_f0, | |
|
629 | reg0_addr_matrix => reg0_addr_matrix_f0, | |
|
630 | reg0_matrix_time => reg0_matrix_time_f0, | |
|
631 | ||
|
632 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1, | |
|
633 | reg1_ready_matrix => reg1_ready_matrix_f0, | |
|
634 | reg1_addr_matrix => reg1_addr_matrix_f0, | |
|
635 | reg1_matrix_time => reg1_matrix_time_f0, | |
|
636 | ||
|
637 | ready_matrix => ready_matrix_f0, | |
|
638 | status_ready_matrix => status_ready_matrix_f0, | |
|
639 | addr_matrix => addr_matrix_f0, | |
|
640 | matrix_time => matrix_time_f0); | |
|
641 | ||
|
642 | lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer | |
|
643 | PORT MAP ( | |
|
644 | clk => HCLK, | |
|
645 | rstn => HRESETn, | |
|
646 | ||
|
647 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, | |
|
648 | reg0_ready_matrix => reg0_ready_matrix_f1, | |
|
649 | reg0_addr_matrix => reg0_addr_matrix_f1, | |
|
650 | reg0_matrix_time => reg0_matrix_time_f1, | |
|
651 | ||
|
652 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1, | |
|
653 | reg1_ready_matrix => reg1_ready_matrix_f1, | |
|
654 | reg1_addr_matrix => reg1_addr_matrix_f1, | |
|
655 | reg1_matrix_time => reg1_matrix_time_f1, | |
|
656 | ||
|
657 | ready_matrix => ready_matrix_f1, | |
|
658 | status_ready_matrix => status_ready_matrix_f1, | |
|
659 | addr_matrix => addr_matrix_f1, | |
|
660 | matrix_time => matrix_time_f1); | |
|
568 | 661 | |
|
569 | END beh; | |
|
662 | lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer | |
|
663 | PORT MAP ( | |
|
664 | clk => HCLK, | |
|
665 | rstn => HRESETn, | |
|
666 | ||
|
667 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, | |
|
668 | reg0_ready_matrix => reg0_ready_matrix_f2, | |
|
669 | reg0_addr_matrix => reg0_addr_matrix_f2, | |
|
670 | reg0_matrix_time => reg0_matrix_time_f2, | |
|
671 | ||
|
672 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1, | |
|
673 | reg1_ready_matrix => reg1_ready_matrix_f2, | |
|
674 | reg1_addr_matrix => reg1_addr_matrix_f2, | |
|
675 | reg1_matrix_time => reg1_matrix_time_f2, | |
|
676 | ||
|
677 | ready_matrix => ready_matrix_f2, | |
|
678 | status_ready_matrix => status_ready_matrix_f2, | |
|
679 | addr_matrix => addr_matrix_f2, | |
|
680 | matrix_time => matrix_time_f2); | |
|
681 | ||
|
682 | ||
|
683 | END beh; No newline at end of file |
@@ -296,23 +296,23 PACKAGE lpp_lfr_pkg IS | |||
|
296 | 296 | apbi : IN apb_slv_in_type; |
|
297 | 297 | apbo : OUT apb_slv_out_type; |
|
298 | 298 | run_ms : OUT STD_LOGIC; |
|
299 |
ready_matrix_f0 |
|
|
299 | ready_matrix_f0 : IN STD_LOGIC; | |
|
300 | 300 | ready_matrix_f1 : IN STD_LOGIC; |
|
301 | 301 | ready_matrix_f2 : IN STD_LOGIC; |
|
302 | 302 | error_bad_component_error : IN STD_LOGIC; |
|
303 | 303 | error_buffer_full : in STD_LOGIC; |
|
304 | 304 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
305 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
306 |
status_ready_matrix_f0 |
|
|
305 | --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
306 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
|
307 | 307 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
308 | 308 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
309 | 309 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
310 | 310 | config_active_interruption_onError : OUT STD_LOGIC; |
|
311 |
addr_matrix_f0 |
|
|
311 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
312 | 312 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
313 | 313 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
314 | 314 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
315 |
matrix_time_f0 |
|
|
315 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
316 | 316 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
317 | 317 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
318 | 318 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
@@ -345,15 +345,8 PACKAGE lpp_lfr_pkg IS | |||
|
345 | 345 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
346 | 346 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
347 | 347 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
348 |
start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) |
|
|
349 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
350 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
351 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
352 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
353 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
354 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
355 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
356 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
|
348 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) | |
|
349 | ); | |
|
357 | 350 | END COMPONENT; |
|
358 | 351 | |
|
359 | 352 | |
@@ -391,5 +384,23 PACKAGE lpp_lfr_pkg IS | |||
|
391 | 384 | |
|
392 | 385 | ); |
|
393 | 386 | END COMPONENT; |
|
387 | ||
|
388 | COMPONENT lpp_apbreg_ms_pointer | |
|
389 | PORT ( | |
|
390 | clk : IN STD_LOGIC; | |
|
391 | rstn : IN STD_LOGIC; | |
|
392 | reg0_status_ready_matrix : IN STD_LOGIC; | |
|
393 | reg0_ready_matrix : OUT STD_LOGIC; | |
|
394 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
395 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
396 | reg1_status_ready_matrix : IN STD_LOGIC; | |
|
397 | reg1_ready_matrix : OUT STD_LOGIC; | |
|
398 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
399 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
400 | ready_matrix : IN STD_LOGIC; | |
|
401 | status_ready_matrix : OUT STD_LOGIC; | |
|
402 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
403 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
|
404 | END COMPONENT; | |
|
394 | 405 | |
|
395 | 406 | END lpp_lfr_pkg; |
General Comments 0
You need to be logged in to leave comments.
Login now