@@ -1,587 +1,587 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | LIBRARY IEEE; |
|
23 | 23 | USE IEEE.numeric_std.ALL; |
|
24 | 24 | USE IEEE.std_logic_1164.ALL; |
|
25 | 25 | LIBRARY grlib; |
|
26 | 26 | USE grlib.amba.ALL; |
|
27 | 27 | USE grlib.stdlib.ALL; |
|
28 | 28 | LIBRARY techmap; |
|
29 | 29 | USE techmap.gencomp.ALL; |
|
30 | 30 | LIBRARY gaisler; |
|
31 | 31 | USE gaisler.memctrl.ALL; |
|
32 | 32 | USE gaisler.leon3.ALL; |
|
33 | 33 | USE gaisler.uart.ALL; |
|
34 | 34 | USE gaisler.misc.ALL; |
|
35 | 35 | USE gaisler.spacewire.ALL; |
|
36 | 36 | LIBRARY esa; |
|
37 | 37 | USE esa.memoryctrl.ALL; |
|
38 | 38 | LIBRARY lpp; |
|
39 | 39 | USE lpp.lpp_memory.ALL; |
|
40 | 40 | USE lpp.lpp_ad_conv.ALL; |
|
41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
43 | 43 | USE lpp.iir_filter.ALL; |
|
44 | 44 | USE lpp.general_purpose.ALL; |
|
45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
|
46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
47 | 47 | |
|
48 | 48 | ENTITY MINI_LFR_top IS |
|
49 | 49 | |
|
50 | 50 | PORT ( |
|
51 | 51 | clk_50 : IN STD_LOGIC; |
|
52 | 52 | clk_49 : IN STD_LOGIC; |
|
53 | 53 | reset : IN STD_LOGIC; |
|
54 | 54 | --BPs |
|
55 | 55 | BP0 : IN STD_LOGIC; |
|
56 | 56 | BP1 : IN STD_LOGIC; |
|
57 | 57 | --LEDs |
|
58 | 58 | LED0 : OUT STD_LOGIC; |
|
59 | 59 | LED1 : OUT STD_LOGIC; |
|
60 | 60 | LED2 : OUT STD_LOGIC; |
|
61 | 61 | --UARTs |
|
62 | 62 | TXD1 : IN STD_LOGIC; |
|
63 | 63 | RXD1 : OUT STD_LOGIC; |
|
64 | 64 | nCTS1 : OUT STD_LOGIC; |
|
65 | 65 | nRTS1 : IN STD_LOGIC; |
|
66 | 66 | |
|
67 | 67 | TXD2 : IN STD_LOGIC; |
|
68 | 68 | RXD2 : OUT STD_LOGIC; |
|
69 | 69 | nCTS2 : OUT STD_LOGIC; |
|
70 | 70 | nDTR2 : IN STD_LOGIC; |
|
71 | 71 | nRTS2 : IN STD_LOGIC; |
|
72 | 72 | nDCD2 : OUT STD_LOGIC; |
|
73 | 73 | |
|
74 | 74 | --EXT CONNECTOR |
|
75 | 75 | IO0 : INOUT STD_LOGIC; |
|
76 | 76 | IO1 : INOUT STD_LOGIC; |
|
77 | 77 | IO2 : INOUT STD_LOGIC; |
|
78 | 78 | IO3 : INOUT STD_LOGIC; |
|
79 | 79 | IO4 : INOUT STD_LOGIC; |
|
80 | 80 | IO5 : INOUT STD_LOGIC; |
|
81 | 81 | IO6 : INOUT STD_LOGIC; |
|
82 | 82 | IO7 : INOUT STD_LOGIC; |
|
83 | 83 | IO8 : INOUT STD_LOGIC; |
|
84 | 84 | IO9 : INOUT STD_LOGIC; |
|
85 | 85 | IO10 : INOUT STD_LOGIC; |
|
86 | 86 | IO11 : INOUT STD_LOGIC; |
|
87 | 87 | |
|
88 | 88 | --SPACE WIRE |
|
89 | 89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
|
90 | 90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
|
91 | 91 | SPW_NOM_SIN : IN STD_LOGIC; |
|
92 | 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
93 | 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
94 | 94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
|
95 | 95 | SPW_RED_SIN : IN STD_LOGIC; |
|
96 | 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
97 | 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
98 | 98 | -- MINI LFR ADC INPUTS |
|
99 | 99 | ADC_nCS : OUT STD_LOGIC; |
|
100 | 100 | ADC_CLK : OUT STD_LOGIC; |
|
101 | 101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
102 | 102 | |
|
103 | 103 | -- SRAM |
|
104 | 104 | SRAM_nWE : OUT STD_LOGIC; |
|
105 | 105 | SRAM_CE : OUT STD_LOGIC; |
|
106 | 106 | SRAM_nOE : OUT STD_LOGIC; |
|
107 | 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
108 | 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
109 | 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
110 | 110 | ); |
|
111 | 111 | |
|
112 | 112 | END MINI_LFR_top; |
|
113 | 113 | |
|
114 | 114 | |
|
115 | 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
|
116 | 116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
117 | 117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
118 | 118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
|
119 | 119 | ----------------------------------------------------------------------------- |
|
120 | 120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
121 | 121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
122 | 122 | -- |
|
123 | 123 | SIGNAL errorn : STD_LOGIC; |
|
124 | 124 | -- UART AHB --------------------------------------------------------------- |
|
125 | 125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
|
126 | 126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
|
127 | 127 | |
|
128 | 128 | -- UART APB --------------------------------------------------------------- |
|
129 | 129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
|
130 | 130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
|
131 | 131 | -- |
|
132 | 132 | SIGNAL I00_s : STD_LOGIC; |
|
133 | 133 | |
|
134 | 134 | -- CONSTANTS |
|
135 | 135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
136 | 136 | -- |
|
137 | 137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
138 | 138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
139 | 139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
140 | 140 | |
|
141 | 141 | SIGNAL apbi_ext : apb_slv_in_type; |
|
142 | 142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
|
143 | 143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
144 | 144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
|
145 | 145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
146 | 146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
|
147 | 147 | |
|
148 | 148 | -- Spacewire signals |
|
149 | 149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
150 | 150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
151 | 151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
152 | 152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
|
153 | 153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
|
154 | 154 | SIGNAL spw_clk : STD_LOGIC; |
|
155 | 155 | SIGNAL swni : grspw_in_type; |
|
156 | 156 | SIGNAL swno : grspw_out_type; |
|
157 | 157 | -- SIGNAL clkmn : STD_ULOGIC; |
|
158 | 158 | -- SIGNAL txclk : STD_ULOGIC; |
|
159 | 159 | |
|
160 | 160 | --GPIO |
|
161 | 161 | SIGNAL gpioi : gpio_in_type; |
|
162 | 162 | SIGNAL gpioo : gpio_out_type; |
|
163 | 163 | |
|
164 | 164 | -- AD Converter ADS7886 |
|
165 | 165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
166 | 166 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
167 | 167 | SIGNAL sample_val : STD_LOGIC; |
|
168 | 168 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
|
169 | 169 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
|
170 | 170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
171 | 171 | |
|
172 | 172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
|
173 | 173 | |
|
174 | 174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
175 | 175 | ----------------------------------------------------------------------------- |
|
176 | 176 | |
|
177 | 177 | BEGIN -- beh |
|
178 | 178 | |
|
179 | 179 | ----------------------------------------------------------------------------- |
|
180 | 180 | -- CLK |
|
181 | 181 | ----------------------------------------------------------------------------- |
|
182 | 182 | |
|
183 | 183 | PROCESS(clk_50) |
|
184 | 184 | BEGIN |
|
185 | 185 | IF clk_50'EVENT AND clk_50 = '1' THEN |
|
186 | 186 | clk_50_s <= NOT clk_50_s; |
|
187 | 187 | END IF; |
|
188 | 188 | END PROCESS; |
|
189 | 189 | |
|
190 | 190 | PROCESS(clk_50_s) |
|
191 | 191 | BEGIN |
|
192 | 192 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
193 | 193 | clk_25 <= NOT clk_25; |
|
194 | 194 | END IF; |
|
195 | 195 | END PROCESS; |
|
196 | 196 | |
|
197 | 197 | PROCESS(clk_49) |
|
198 | 198 | BEGIN |
|
199 | 199 | IF clk_49'EVENT AND clk_49 = '1' THEN |
|
200 | 200 | clk_24 <= NOT clk_24; |
|
201 | 201 | END IF; |
|
202 | 202 | END PROCESS; |
|
203 | 203 | |
|
204 | 204 | ----------------------------------------------------------------------------- |
|
205 | 205 | |
|
206 | 206 | PROCESS (clk_25, reset) |
|
207 | 207 | BEGIN -- PROCESS |
|
208 | 208 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
209 | 209 | LED0 <= '0'; |
|
210 | 210 | LED1 <= '0'; |
|
211 | 211 | LED2 <= '0'; |
|
212 | 212 | --IO1 <= '0'; |
|
213 | 213 | --IO2 <= '1'; |
|
214 | 214 | --IO3 <= '0'; |
|
215 | 215 | --IO4 <= '0'; |
|
216 | 216 | --IO5 <= '0'; |
|
217 | 217 | --IO6 <= '0'; |
|
218 | 218 | --IO7 <= '0'; |
|
219 | 219 | --IO8 <= '0'; |
|
220 | 220 | --IO9 <= '0'; |
|
221 | 221 | --IO10 <= '0'; |
|
222 | 222 | --IO11 <= '0'; |
|
223 | 223 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
224 | 224 | LED0 <= '0'; |
|
225 | 225 | LED1 <= '1'; |
|
226 | 226 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
227 | 227 | --IO1 <= '1'; |
|
228 | 228 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
229 | 229 | --IO3 <= ADC_SDO(0); |
|
230 | 230 | --IO4 <= ADC_SDO(1); |
|
231 | 231 | --IO5 <= ADC_SDO(2); |
|
232 | 232 | --IO6 <= ADC_SDO(3); |
|
233 | 233 | --IO7 <= ADC_SDO(4); |
|
234 | 234 | --IO8 <= ADC_SDO(5); |
|
235 | 235 | --IO9 <= ADC_SDO(6); |
|
236 | 236 | --IO10 <= ADC_SDO(7); |
|
237 | 237 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
238 | 238 | END IF; |
|
239 | 239 | END PROCESS; |
|
240 | 240 | |
|
241 | 241 | PROCESS (clk_24, reset) |
|
242 | 242 | BEGIN -- PROCESS |
|
243 | 243 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
244 | 244 | I00_s <= '0'; |
|
245 | 245 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
|
246 | 246 | I00_s <= NOT I00_s ; |
|
247 | 247 | END IF; |
|
248 | 248 | END PROCESS; |
|
249 | 249 | -- IO0 <= I00_s; |
|
250 | 250 | |
|
251 | 251 | --UARTs |
|
252 | 252 | nCTS1 <= '1'; |
|
253 | 253 | nCTS2 <= '1'; |
|
254 | 254 | nDCD2 <= '1'; |
|
255 | 255 | |
|
256 | 256 | --EXT CONNECTOR |
|
257 | 257 | |
|
258 | 258 | --SPACE WIRE |
|
259 | 259 | |
|
260 | 260 | leon3_soc_1 : leon3_soc |
|
261 | 261 | GENERIC MAP ( |
|
262 | 262 | fabtech => apa3e, |
|
263 | 263 | memtech => apa3e, |
|
264 | 264 | padtech => inferred, |
|
265 | 265 | clktech => inferred, |
|
266 | 266 | disas => 0, |
|
267 | 267 | dbguart => 0, |
|
268 | 268 | pclow => 2, |
|
269 | 269 | clk_freq => 25000, |
|
270 | 270 | NB_CPU => 1, |
|
271 | 271 | ENABLE_FPU => 1, |
|
272 | 272 | FPU_NETLIST => 0, |
|
273 | 273 | ENABLE_DSU => 1, |
|
274 | 274 | ENABLE_AHB_UART => 1, |
|
275 | 275 | ENABLE_APB_UART => 1, |
|
276 | 276 | ENABLE_IRQMP => 1, |
|
277 | 277 | ENABLE_GPT => 1, |
|
278 | 278 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
279 | 279 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
280 | 280 | NB_APB_SLAVE => NB_APB_SLAVE) |
|
281 | 281 | PORT MAP ( |
|
282 | 282 | clk => clk_25, |
|
283 | 283 | reset => reset, |
|
284 | 284 | errorn => errorn, |
|
285 | 285 | ahbrxd => TXD1, |
|
286 | 286 | ahbtxd => RXD1, |
|
287 | 287 | urxd1 => TXD2, |
|
288 | 288 | utxd1 => RXD2, |
|
289 | 289 | address => SRAM_A, |
|
290 | 290 | data => SRAM_DQ, |
|
291 | 291 | nSRAM_BE0 => SRAM_nBE(0), |
|
292 | 292 | nSRAM_BE1 => SRAM_nBE(1), |
|
293 | 293 | nSRAM_BE2 => SRAM_nBE(2), |
|
294 | 294 | nSRAM_BE3 => SRAM_nBE(3), |
|
295 | 295 | nSRAM_WE => SRAM_nWE, |
|
296 | 296 | nSRAM_CE => SRAM_CE, |
|
297 | 297 | nSRAM_OE => SRAM_nOE, |
|
298 | 298 | |
|
299 | 299 | apbi_ext => apbi_ext, |
|
300 | 300 | apbo_ext => apbo_ext, |
|
301 | 301 | ahbi_s_ext => ahbi_s_ext, |
|
302 | 302 | ahbo_s_ext => ahbo_s_ext, |
|
303 | 303 | ahbi_m_ext => ahbi_m_ext, |
|
304 | 304 | ahbo_m_ext => ahbo_m_ext); |
|
305 | 305 | |
|
306 | 306 | ------------------------------------------------------------------------------- |
|
307 | 307 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
308 | 308 | ------------------------------------------------------------------------------- |
|
309 | 309 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
310 | 310 | GENERIC MAP ( |
|
311 | 311 | pindex => 6, |
|
312 | 312 | paddr => 6, |
|
313 | 313 | pmask => 16#fff#, |
|
314 | 314 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
315 | 315 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
316 | 316 | PORT MAP ( |
|
317 | 317 | clk25MHz => clk_25, |
|
318 | 318 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
319 | 319 | resetn => reset, |
|
320 | 320 | grspw_tick => swno.tickout, |
|
321 | 321 | apbi => apbi_ext, |
|
322 | 322 | apbo => apbo_ext(6), |
|
323 | 323 | coarse_time => coarse_time, |
|
324 | 324 | fine_time => fine_time); |
|
325 | 325 | |
|
326 | 326 | ----------------------------------------------------------------------- |
|
327 | 327 | --- SpaceWire -------------------------------------------------------- |
|
328 | 328 | ----------------------------------------------------------------------- |
|
329 | 329 | |
|
330 | 330 | SPW_EN <= '1'; |
|
331 | 331 | |
|
332 | 332 | spw_clk <= clk_50_s; |
|
333 | 333 | spw_rxtxclk <= spw_clk; |
|
334 | 334 | spw_rxclkn <= NOT spw_rxtxclk; |
|
335 | 335 | |
|
336 | 336 | -- PADS for SPW1 |
|
337 | 337 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
338 | 338 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
339 | 339 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
340 | 340 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
341 | 341 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
342 | 342 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
343 | 343 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
344 | 344 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
345 | 345 | -- PADS FOR SPW2 |
|
346 | 346 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
347 | 347 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
348 | 348 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
349 | 349 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
350 | 350 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
351 | 351 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
352 | 352 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
353 | 353 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
354 | 354 | |
|
355 | 355 | -- GRSPW PHY |
|
356 | 356 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
357 | 357 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
358 | 358 | spw_phy0 : grspw_phy |
|
359 | 359 | GENERIC MAP( |
|
360 | 360 | tech => apa3e, |
|
361 | 361 | rxclkbuftype => 1, |
|
362 | 362 | scantest => 0) |
|
363 | 363 | PORT MAP( |
|
364 | 364 | rxrst => swno.rxrst, |
|
365 | 365 | di => dtmp(j), |
|
366 | 366 | si => stmp(j), |
|
367 | 367 | rxclko => spw_rxclk(j), |
|
368 | 368 | do => swni.d(j), |
|
369 | 369 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
370 | 370 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
371 | 371 | END GENERATE spw_inputloop; |
|
372 | 372 | |
|
373 | 373 | -- SPW core |
|
374 | 374 | sw0 : grspwm GENERIC MAP( |
|
375 | 375 | tech => apa3e, |
|
376 | 376 | hindex => 1, |
|
377 | 377 | pindex => 5, |
|
378 | 378 | paddr => 5, |
|
379 | 379 | pirq => 11, |
|
380 | 380 | sysfreq => 25000, -- CPU_FREQ |
|
381 | 381 | rmap => 1, |
|
382 | 382 | rmapcrc => 1, |
|
383 | 383 | fifosize1 => 16, |
|
384 | 384 | fifosize2 => 16, |
|
385 | 385 | rxclkbuftype => 1, |
|
386 | 386 | rxunaligned => 0, |
|
387 | 387 | rmapbufs => 4, |
|
388 | 388 | ft => 0, |
|
389 | 389 | netlist => 0, |
|
390 | 390 | ports => 2, |
|
391 | 391 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
392 | 392 | memtech => apa3e, |
|
393 | 393 | destkey => 2, |
|
394 | 394 | spwcore => 1 |
|
395 | 395 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
396 | 396 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
397 | 397 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
398 | 398 | ) |
|
399 | 399 | PORT MAP(reset, clk_25, spw_rxclk(0), |
|
400 | 400 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
401 | 401 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
402 | 402 | swni, swno); |
|
403 | 403 | |
|
404 | 404 | swni.tickin <= '0'; |
|
405 | 405 | swni.rmapen <= '1'; |
|
406 | 406 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
407 | 407 | swni.tickinraw <= '0'; |
|
408 | 408 | swni.timein <= (OTHERS => '0'); |
|
409 | 409 | swni.dcrstval <= (OTHERS => '0'); |
|
410 | 410 | swni.timerrstval <= (OTHERS => '0'); |
|
411 | 411 | |
|
412 | 412 | ------------------------------------------------------------------------------- |
|
413 | 413 | -- LFR ------------------------------------------------------------------------ |
|
414 | 414 | ------------------------------------------------------------------------------- |
|
415 | 415 | lpp_lfr_1 : lpp_lfr |
|
416 | 416 | GENERIC MAP ( |
|
417 | 417 | Mem_use => use_RAM, |
|
418 | 418 | nb_data_by_buffer_size => 32, |
|
419 | 419 | nb_word_by_buffer_size => 30, |
|
420 | 420 | nb_snapshot_param_size => 32, |
|
421 | 421 | delta_vector_size => 32, |
|
422 | 422 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
423 | 423 | pindex => 15, |
|
424 | 424 | paddr => 15, |
|
425 | 425 | pmask => 16#fff#, |
|
426 | 426 | pirq_ms => 6, |
|
427 | 427 | pirq_wfp => 14, |
|
428 | 428 | hindex => 2, |
|
429 |
top_lfr_version => X"00010 |
|
|
429 | top_lfr_version => X"00010E") -- aa.bb.cc version | |
|
430 | 430 | PORT MAP ( |
|
431 | 431 | clk => clk_25, |
|
432 | 432 | rstn => reset, |
|
433 | 433 | sample_B => sample_s(2 DOWNTO 0), |
|
434 | 434 | sample_E => sample_s(7 DOWNTO 3), |
|
435 | 435 | sample_val => sample_val, |
|
436 | 436 | apbi => apbi_ext, |
|
437 | 437 | apbo => apbo_ext(15), |
|
438 | 438 | ahbi => ahbi_m_ext, |
|
439 | 439 | ahbo => ahbo_m_ext(2), |
|
440 | 440 | coarse_time => coarse_time, |
|
441 | 441 | fine_time => fine_time, |
|
442 | 442 | data_shaping_BW => bias_fail_sw_sig, |
|
443 | 443 | observation_reg => observation_reg); |
|
444 | 444 | |
|
445 | 445 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE |
|
446 | 446 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
|
447 | 447 | END GENERATE all_sample; |
|
448 | 448 | |
|
449 | 449 | |
|
450 | 450 | |
|
451 | 451 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
452 | 452 | GENERIC MAP( |
|
453 | 453 | ChannelCount => 8, |
|
454 | 454 | SampleNbBits => 14, |
|
455 | 455 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
456 | 456 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
457 | 457 | PORT MAP ( |
|
458 | 458 | -- CONV |
|
459 | 459 | cnv_clk => clk_24, |
|
460 | 460 | cnv_rstn => reset, |
|
461 | 461 | cnv => ADC_nCS_sig, |
|
462 | 462 | -- DATA |
|
463 | 463 | clk => clk_25, |
|
464 | 464 | rstn => reset, |
|
465 | 465 | sck => ADC_CLK_sig, |
|
466 | 466 | sdo => ADC_SDO_sig, |
|
467 | 467 | -- SAMPLE |
|
468 | 468 | sample => sample, |
|
469 | 469 | sample_val => sample_val); |
|
470 | 470 | |
|
471 | 471 | --IO10 <= ADC_SDO_sig(5); |
|
472 | 472 | --IO9 <= ADC_SDO_sig(4); |
|
473 | 473 | --IO8 <= ADC_SDO_sig(3); |
|
474 | 474 | |
|
475 | 475 | ADC_nCS <= ADC_nCS_sig; |
|
476 | 476 | ADC_CLK <= ADC_CLK_sig; |
|
477 | 477 | ADC_SDO_sig <= ADC_SDO; |
|
478 | 478 | |
|
479 | 479 | ---------------------------------------------------------------------- |
|
480 | 480 | --- GPIO ----------------------------------------------------------- |
|
481 | 481 | ---------------------------------------------------------------------- |
|
482 | 482 | |
|
483 | 483 | grgpio0 : grgpio |
|
484 | 484 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
485 | 485 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
486 | 486 | |
|
487 | 487 | --pio_pad_0 : iopad |
|
488 | 488 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
489 | 489 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
490 | 490 | --pio_pad_1 : iopad |
|
491 | 491 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
492 | 492 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
493 | 493 | --pio_pad_2 : iopad |
|
494 | 494 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
495 | 495 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
496 | 496 | --pio_pad_3 : iopad |
|
497 | 497 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
498 | 498 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
499 | 499 | --pio_pad_4 : iopad |
|
500 | 500 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
501 | 501 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
502 | 502 | --pio_pad_5 : iopad |
|
503 | 503 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
504 | 504 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
505 | 505 | --pio_pad_6 : iopad |
|
506 | 506 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
507 | 507 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
508 | 508 | --pio_pad_7 : iopad |
|
509 | 509 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
510 | 510 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
511 | 511 | |
|
512 | 512 | PROCESS (clk_25, reset) |
|
513 | 513 | BEGIN -- PROCESS |
|
514 | 514 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
515 | 515 | IO0 <= '0'; |
|
516 | 516 | IO1 <= '0'; |
|
517 | 517 | IO2 <= '0'; |
|
518 | 518 | IO3 <= '0'; |
|
519 | 519 | IO4 <= '0'; |
|
520 | 520 | IO5 <= '0'; |
|
521 | 521 | IO6 <= '0'; |
|
522 | 522 | IO7 <= '0'; |
|
523 | 523 | IO8 <= '0'; |
|
524 | 524 | IO9 <= '0'; |
|
525 | 525 | IO10 <= '0'; |
|
526 | 526 | IO11 <= '0'; |
|
527 | 527 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
528 | 528 | CASE gpioo.dout(1 DOWNTO 0) IS |
|
529 | 529 | WHEN "00" => |
|
530 | 530 | IO0 <= observation_reg(0 ); |
|
531 | 531 | IO1 <= observation_reg(1 ); |
|
532 | 532 | IO2 <= observation_reg(2 ); |
|
533 | 533 | IO3 <= observation_reg(3 ); |
|
534 | 534 | IO4 <= observation_reg(4 ); |
|
535 | 535 | IO5 <= observation_reg(5 ); |
|
536 | 536 | IO6 <= observation_reg(6 ); |
|
537 | 537 | IO7 <= observation_reg(7 ); |
|
538 | 538 | IO8 <= observation_reg(8 ); |
|
539 | 539 | IO9 <= observation_reg(9 ); |
|
540 | 540 | IO10 <= observation_reg(10); |
|
541 | 541 | IO11 <= observation_reg(11); |
|
542 | 542 | WHEN "01" => |
|
543 | 543 | IO0 <= observation_reg(0 + 12); |
|
544 | 544 | IO1 <= observation_reg(1 + 12); |
|
545 | 545 | IO2 <= observation_reg(2 + 12); |
|
546 | 546 | IO3 <= observation_reg(3 + 12); |
|
547 | 547 | IO4 <= observation_reg(4 + 12); |
|
548 | 548 | IO5 <= observation_reg(5 + 12); |
|
549 | 549 | IO6 <= observation_reg(6 + 12); |
|
550 | 550 | IO7 <= observation_reg(7 + 12); |
|
551 | 551 | IO8 <= observation_reg(8 + 12); |
|
552 | 552 | IO9 <= observation_reg(9 + 12); |
|
553 | 553 | IO10 <= observation_reg(10 + 12); |
|
554 | 554 | IO11 <= observation_reg(11 + 12); |
|
555 | 555 | WHEN "10" => |
|
556 | 556 | IO0 <= observation_reg(0 + 12 + 12); |
|
557 | 557 | IO1 <= observation_reg(1 + 12 + 12); |
|
558 | 558 | IO2 <= observation_reg(2 + 12 + 12); |
|
559 | 559 | IO3 <= observation_reg(3 + 12 + 12); |
|
560 | 560 | IO4 <= observation_reg(4 + 12 + 12); |
|
561 | 561 | IO5 <= observation_reg(5 + 12 + 12); |
|
562 | 562 | IO6 <= observation_reg(6 + 12 + 12); |
|
563 | 563 | IO7 <= observation_reg(7 + 12 + 12); |
|
564 | 564 | IO8 <= '0'; |
|
565 | 565 | IO9 <= '0'; |
|
566 | 566 | IO10 <= '0'; |
|
567 | 567 | IO11 <= '0'; |
|
568 | 568 | WHEN "11" => |
|
569 | 569 | IO0 <= '0'; |
|
570 | 570 | IO1 <= '0'; |
|
571 | 571 | IO2 <= '0'; |
|
572 | 572 | IO3 <= '0'; |
|
573 | 573 | IO4 <= '0'; |
|
574 | 574 | IO5 <= '0'; |
|
575 | 575 | IO6 <= '0'; |
|
576 | 576 | IO7 <= '0'; |
|
577 | 577 | IO8 <= '0'; |
|
578 | 578 | IO9 <= '0'; |
|
579 | 579 | IO10 <= '0'; |
|
580 | 580 | IO11 <= '0'; |
|
581 | 581 | WHEN OTHERS => NULL; |
|
582 | 582 | END CASE; |
|
583 | 583 | |
|
584 | 584 | END IF; |
|
585 | 585 | END PROCESS; |
|
586 | 586 | |
|
587 | 587 | END beh; |
@@ -1,770 +1,716 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | USE ieee.numeric_std.ALL; |
|
4 | 4 | |
|
5 | 5 | LIBRARY lpp; |
|
6 | 6 | USE lpp.lpp_ad_conv.ALL; |
|
7 | 7 | USE lpp.iir_filter.ALL; |
|
8 | 8 | USE lpp.FILTERcfg.ALL; |
|
9 | 9 | USE lpp.lpp_memory.ALL; |
|
10 | 10 | USE lpp.lpp_waveform_pkg.ALL; |
|
11 | 11 | USE lpp.lpp_dma_pkg.ALL; |
|
12 | 12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
13 | 13 | USE lpp.lpp_lfr_pkg.ALL; |
|
14 | 14 | USE lpp.general_purpose.ALL; |
|
15 | 15 | |
|
16 | 16 | LIBRARY techmap; |
|
17 | 17 | USE techmap.gencomp.ALL; |
|
18 | 18 | |
|
19 | 19 | LIBRARY grlib; |
|
20 | 20 | USE grlib.amba.ALL; |
|
21 | 21 | USE grlib.stdlib.ALL; |
|
22 | 22 | USE grlib.devices.ALL; |
|
23 | 23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
24 | 24 | |
|
25 | 25 | ENTITY lpp_lfr IS |
|
26 | 26 | GENERIC ( |
|
27 | 27 | Mem_use : INTEGER := use_RAM; |
|
28 | 28 | nb_data_by_buffer_size : INTEGER := 11; |
|
29 | 29 | nb_word_by_buffer_size : INTEGER := 11; |
|
30 | 30 | nb_snapshot_param_size : INTEGER := 11; |
|
31 | 31 | delta_vector_size : INTEGER := 20; |
|
32 | 32 | delta_vector_size_f0_2 : INTEGER := 7; |
|
33 | 33 | |
|
34 | 34 | pindex : INTEGER := 4; |
|
35 | 35 | paddr : INTEGER := 4; |
|
36 | 36 | pmask : INTEGER := 16#fff#; |
|
37 | 37 | pirq_ms : INTEGER := 0; |
|
38 | 38 | pirq_wfp : INTEGER := 1; |
|
39 | 39 | |
|
40 | 40 | hindex : INTEGER := 2; |
|
41 | 41 | |
|
42 | 42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') |
|
43 | 43 | |
|
44 | 44 | ); |
|
45 | 45 | PORT ( |
|
46 | 46 | clk : IN STD_LOGIC; |
|
47 | 47 | rstn : IN STD_LOGIC; |
|
48 | 48 | -- SAMPLE |
|
49 | 49 | sample_B : IN Samples(2 DOWNTO 0); |
|
50 | 50 | sample_E : IN Samples(4 DOWNTO 0); |
|
51 | 51 | sample_val : IN STD_LOGIC; |
|
52 | 52 | -- APB |
|
53 | 53 | apbi : IN apb_slv_in_type; |
|
54 | 54 | apbo : OUT apb_slv_out_type; |
|
55 | 55 | -- AHB |
|
56 | 56 | ahbi : IN AHB_Mst_In_Type; |
|
57 | 57 | ahbo : OUT AHB_Mst_Out_Type; |
|
58 | 58 | -- TIME |
|
59 | 59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
60 | 60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
61 | 61 | -- |
|
62 | 62 | data_shaping_BW : OUT STD_LOGIC; |
|
63 | 63 | -- |
|
64 | 64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
65 | 65 | |
|
66 | 66 | --debug |
|
67 | 67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
68 | 68 | --debug_f0_data_valid : OUT STD_LOGIC; |
|
69 | 69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
70 | 70 | --debug_f1_data_valid : OUT STD_LOGIC; |
|
71 | 71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
72 | 72 | --debug_f2_data_valid : OUT STD_LOGIC; |
|
73 | 73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
74 | 74 | --debug_f3_data_valid : OUT STD_LOGIC; |
|
75 | 75 | |
|
76 | 76 | ---- debug FIFO_IN |
|
77 | 77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | 78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
79 | 79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
80 | 80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
81 | 81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | 82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
83 | 83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | 84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
85 | 85 | |
|
86 | 86 | ----debug FIFO OUT |
|
87 | 87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
88 | 88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
89 | 89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | 90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
91 | 91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 | 92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
93 | 93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
94 | 94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
95 | 95 | |
|
96 | 96 | ----debug DMA IN |
|
97 | 97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
98 | 98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
99 | 99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
100 | 100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
101 | 101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
102 | 102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
103 | 103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
104 | 104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
105 | 105 | ); |
|
106 | 106 | END lpp_lfr; |
|
107 | 107 | |
|
108 | 108 | ARCHITECTURE beh OF lpp_lfr IS |
|
109 | 109 | --SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
110 | 110 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
111 | 111 | -- |
|
112 | 112 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
113 | 113 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
114 | 114 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
115 | 115 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
116 | 116 | -- |
|
117 | 117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
118 | 118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
119 | 119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
120 | 120 | -- |
|
121 | 121 | SIGNAL sample_f0_val : STD_LOGIC; |
|
122 | 122 | SIGNAL sample_f1_val : STD_LOGIC; |
|
123 | 123 | SIGNAL sample_f2_val : STD_LOGIC; |
|
124 | 124 | SIGNAL sample_f3_val : STD_LOGIC; |
|
125 | 125 | -- |
|
126 | 126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
127 | 127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
128 | 128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
129 | 129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
130 | 130 | -- |
|
131 | 131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
132 | 132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
133 | 133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
134 | 134 | |
|
135 | 135 | -- SM |
|
136 |
SIGNAL ready_matrix_f0 |
|
|
136 | SIGNAL ready_matrix_f0 : STD_LOGIC; | |
|
137 | 137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
138 | 138 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
139 | 139 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
140 | 140 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
141 | 141 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
143 |
SIGNAL status_ready_matrix_f0 |
|
|
142 | -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
143 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; | |
|
144 | 144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
145 | 145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
146 | 146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
147 | 147 | -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
148 | 148 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
149 | 149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
150 | 150 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
151 |
SIGNAL addr_matrix_f0 |
|
|
151 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
152 | 152 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
153 | 153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
154 | 154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
155 | 155 | |
|
156 | 156 | -- WFP |
|
157 | 157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
158 | 158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
159 | 159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
160 | 160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
161 | 161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
162 | 162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
163 | 163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
164 | 164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
165 | 165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
166 | 166 | |
|
167 | 167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
168 | 168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
169 | 169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
170 | 170 | SIGNAL enable_f0 : STD_LOGIC; |
|
171 | 171 | SIGNAL enable_f1 : STD_LOGIC; |
|
172 | 172 | SIGNAL enable_f2 : STD_LOGIC; |
|
173 | 173 | SIGNAL enable_f3 : STD_LOGIC; |
|
174 | 174 | SIGNAL burst_f0 : STD_LOGIC; |
|
175 | 175 | SIGNAL burst_f1 : STD_LOGIC; |
|
176 | 176 | SIGNAL burst_f2 : STD_LOGIC; |
|
177 | 177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
178 | 178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
179 | 179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
180 | 180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
181 | 181 | |
|
182 | 182 | SIGNAL run : STD_LOGIC; |
|
183 | 183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
184 | 184 | |
|
185 | 185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | 186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
187 | 187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
188 | 188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
189 | 189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
|
190 | 190 | --f1 |
|
191 | 191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
192 | 192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
193 | 193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
194 | 194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
195 | 195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
|
196 | 196 | --f2 |
|
197 | 197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
198 | 198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
199 | 199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
200 | 200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
201 | 201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
|
202 | 202 | --f3 |
|
203 | 203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
204 | 204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
205 | 205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
206 | 206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
207 | 207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
|
208 | 208 | |
|
209 | 209 | ----------------------------------------------------------------------------- |
|
210 | 210 | -- |
|
211 | 211 | ----------------------------------------------------------------------------- |
|
212 | 212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
213 | 213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
|
214 | 214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
|
215 | 215 | --f1 |
|
216 | 216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
217 | 217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
|
218 | 218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
|
219 | 219 | --f2 |
|
220 | 220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
221 | 221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
|
222 | 222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
|
223 | 223 | --f3 |
|
224 | 224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
225 | 225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
|
226 | 226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
|
227 | 227 | |
|
228 | 228 | ----------------------------------------------------------------------------- |
|
229 | 229 | -- DMA RR |
|
230 | 230 | ----------------------------------------------------------------------------- |
|
231 | 231 | SIGNAL dma_sel_valid : STD_LOGIC; |
|
232 | 232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
233 | 233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
234 | 234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
235 | 235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
236 | 236 | |
|
237 | 237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
238 | 238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
239 | 239 | |
|
240 | 240 | ----------------------------------------------------------------------------- |
|
241 | 241 | -- DMA_REG |
|
242 | 242 | ----------------------------------------------------------------------------- |
|
243 | 243 | SIGNAL ongoing_reg : STD_LOGIC; |
|
244 | 244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
245 | 245 | SIGNAL dma_send_reg : STD_LOGIC; |
|
246 | 246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
247 | 247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
248 | 248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
249 | 249 | |
|
250 | 250 | |
|
251 | 251 | ----------------------------------------------------------------------------- |
|
252 | 252 | -- DMA |
|
253 | 253 | ----------------------------------------------------------------------------- |
|
254 | 254 | SIGNAL dma_send : STD_LOGIC; |
|
255 | 255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
256 | 256 | SIGNAL dma_done : STD_LOGIC; |
|
257 | 257 | SIGNAL dma_ren : STD_LOGIC; |
|
258 | 258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
259 | 259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
260 | 260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
261 | 261 | |
|
262 | 262 | ----------------------------------------------------------------------------- |
|
263 | -- DEBUG | |
|
264 | ----------------------------------------------------------------------------- | |
|
265 | -- | |
|
266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
270 | ||
|
271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
279 | ||
|
280 | ----------------------------------------------------------------------------- | |
|
281 | 263 | -- MS |
|
282 | 264 | ----------------------------------------------------------------------------- |
|
283 | 265 | |
|
284 | 266 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
285 | 267 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
286 | 268 | SIGNAL data_ms_valid : STD_LOGIC; |
|
287 | 269 | SIGNAL data_ms_valid_burst : STD_LOGIC; |
|
288 | 270 | SIGNAL data_ms_ren : STD_LOGIC; |
|
289 | 271 | SIGNAL data_ms_done : STD_LOGIC; |
|
290 | 272 | |
|
291 | 273 | SIGNAL run_ms : STD_LOGIC; |
|
292 | 274 | SIGNAL ms_softandhard_rstn : STD_LOGIC; |
|
293 | 275 | |
|
294 |
SIGNAL matrix_time_f0 |
|
|
276 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
295 | 277 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
296 | 278 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
297 | 279 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
298 | 280 | |
|
299 | 281 | |
|
300 | 282 | SIGNAL error_buffer_full : STD_LOGIC; |
|
301 | 283 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
302 | 284 | |
|
303 | 285 | BEGIN |
|
304 | 286 | |
|
305 | 287 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
306 | 288 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
307 | 289 | |
|
308 | 290 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
|
309 | 291 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
310 | 292 | --END GENERATE all_channel; |
|
311 | 293 | |
|
312 | 294 | ----------------------------------------------------------------------------- |
|
313 | 295 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
314 | 296 | GENERIC MAP ( |
|
315 | 297 | Mem_use => Mem_use) |
|
316 | 298 | PORT MAP ( |
|
317 | 299 | sample => sample_s, |
|
318 | 300 | sample_val => sample_val, |
|
319 | 301 | clk => clk, |
|
320 | 302 | rstn => rstn, |
|
321 | 303 | data_shaping_SP0 => data_shaping_SP0, |
|
322 | 304 | data_shaping_SP1 => data_shaping_SP1, |
|
323 | 305 | data_shaping_R0 => data_shaping_R0, |
|
324 | 306 | data_shaping_R1 => data_shaping_R1, |
|
325 | 307 | sample_f0_val => sample_f0_val, |
|
326 | 308 | sample_f1_val => sample_f1_val, |
|
327 | 309 | sample_f2_val => sample_f2_val, |
|
328 | 310 | sample_f3_val => sample_f3_val, |
|
329 | 311 | sample_f0_wdata => sample_f0_data, |
|
330 | 312 | sample_f1_wdata => sample_f1_data, |
|
331 | 313 | sample_f2_wdata => sample_f2_data, |
|
332 | 314 | sample_f3_wdata => sample_f3_data); |
|
333 | 315 | |
|
334 | 316 | ----------------------------------------------------------------------------- |
|
335 | 317 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
336 | 318 | GENERIC MAP ( |
|
337 | 319 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
338 | 320 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
339 | 321 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
340 | 322 | delta_vector_size => delta_vector_size, |
|
341 | 323 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
342 | 324 | pindex => pindex, |
|
343 | 325 | paddr => paddr, |
|
344 | 326 | pmask => pmask, |
|
345 | 327 | pirq_ms => pirq_ms, |
|
346 | 328 | pirq_wfp => pirq_wfp, |
|
347 | 329 | top_lfr_version => top_lfr_version) |
|
348 | 330 | PORT MAP ( |
|
349 | 331 | HCLK => clk, |
|
350 | 332 | HRESETn => rstn, |
|
351 | 333 | apbi => apbi, |
|
352 | 334 | apbo => apbo, |
|
353 | 335 | |
|
354 | 336 | run_ms => run_ms, |
|
355 | 337 | |
|
356 |
ready_matrix_f0 |
|
|
338 | ready_matrix_f0 => ready_matrix_f0, | |
|
357 | 339 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
358 | 340 | ready_matrix_f1 => ready_matrix_f1, |
|
359 | 341 | ready_matrix_f2 => ready_matrix_f2, |
|
360 | 342 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
361 | 343 | error_bad_component_error => error_bad_component_error, |
|
362 | 344 | error_buffer_full => error_buffer_full, -- TODO |
|
363 | 345 | error_input_fifo_write => error_input_fifo_write, -- TODO |
|
364 | debug_reg => debug_reg, | |
|
365 |
status_ready_matrix_f0 |
|
|
346 | -- debug_reg => debug_reg, | |
|
347 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
|
366 | 348 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
367 | 349 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
368 | 350 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
369 | 351 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
370 | 352 | -- status_error_bad_component_error => status_error_bad_component_error, |
|
371 | 353 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
372 | 354 | config_active_interruption_onError => config_active_interruption_onError, |
|
373 | 355 | |
|
374 |
matrix_time_f0 |
|
|
356 | matrix_time_f0 => matrix_time_f0, | |
|
375 | 357 | -- matrix_time_f0_1 => matrix_time_f0_1, |
|
376 | 358 | matrix_time_f1 => matrix_time_f1, |
|
377 | 359 | matrix_time_f2 => matrix_time_f2, |
|
378 | 360 | |
|
379 |
addr_matrix_f0 |
|
|
361 | addr_matrix_f0 => addr_matrix_f0, | |
|
380 | 362 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
|
381 | 363 | addr_matrix_f1 => addr_matrix_f1, |
|
382 | 364 | addr_matrix_f2 => addr_matrix_f2, |
|
383 | 365 | ------------------------------------------------------------------------- |
|
384 | 366 | status_full => status_full, |
|
385 | 367 | status_full_ack => status_full_ack, |
|
386 | 368 | status_full_err => status_full_err, |
|
387 | 369 | status_new_err => status_new_err, |
|
388 | 370 | data_shaping_BW => data_shaping_BW, |
|
389 | 371 | data_shaping_SP0 => data_shaping_SP0, |
|
390 | 372 | data_shaping_SP1 => data_shaping_SP1, |
|
391 | 373 | data_shaping_R0 => data_shaping_R0, |
|
392 | 374 | data_shaping_R1 => data_shaping_R1, |
|
393 | 375 | delta_snapshot => delta_snapshot, |
|
394 | 376 | delta_f0 => delta_f0, |
|
395 | 377 | delta_f0_2 => delta_f0_2, |
|
396 | 378 | delta_f1 => delta_f1, |
|
397 | 379 | delta_f2 => delta_f2, |
|
398 | 380 | nb_data_by_buffer => nb_data_by_buffer, |
|
399 | 381 | nb_word_by_buffer => nb_word_by_buffer, |
|
400 | 382 | nb_snapshot_param => nb_snapshot_param, |
|
401 | 383 | enable_f0 => enable_f0, |
|
402 | 384 | enable_f1 => enable_f1, |
|
403 | 385 | enable_f2 => enable_f2, |
|
404 | 386 | enable_f3 => enable_f3, |
|
405 | 387 | burst_f0 => burst_f0, |
|
406 | 388 | burst_f1 => burst_f1, |
|
407 | 389 | burst_f2 => burst_f2, |
|
408 | 390 | run => run, |
|
409 | 391 | addr_data_f0 => addr_data_f0, |
|
410 | 392 | addr_data_f1 => addr_data_f1, |
|
411 | 393 | addr_data_f2 => addr_data_f2, |
|
412 | 394 | addr_data_f3 => addr_data_f3, |
|
413 |
start_date => start_date |
|
|
414 | --------------------------------------------------------------------------- | |
|
415 | debug_reg0 => debug_reg0, | |
|
416 | debug_reg1 => debug_reg1, | |
|
417 | debug_reg2 => debug_reg2, | |
|
418 | debug_reg3 => debug_reg3, | |
|
419 | debug_reg4 => debug_reg4, | |
|
420 | debug_reg5 => debug_reg5, | |
|
421 | debug_reg6 => debug_reg6, | |
|
422 | debug_reg7 => debug_reg7); | |
|
395 | start_date => start_date); | |
|
423 | 396 | |
|
424 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); | |
|
425 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); | |
|
426 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); | |
|
427 | 397 | ----------------------------------------------------------------------------- |
|
428 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug | |
|
429 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug | |
|
430 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug | |
|
431 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug | |
|
432 | ||
|
433 | ||
|
434 | 398 | ----------------------------------------------------------------------------- |
|
435 | 399 | lpp_waveform_1 : lpp_waveform |
|
436 | 400 | GENERIC MAP ( |
|
437 | 401 | tech => inferred, |
|
438 | 402 | data_size => 6*16, |
|
439 | 403 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
440 | 404 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
441 | 405 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
442 | 406 | delta_vector_size => delta_vector_size, |
|
443 | 407 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
444 | 408 | ) |
|
445 | 409 | PORT MAP ( |
|
446 | 410 | clk => clk, |
|
447 | 411 | rstn => rstn, |
|
448 | 412 | |
|
449 | 413 | reg_run => run, |
|
450 | 414 | reg_start_date => start_date, |
|
451 | 415 | reg_delta_snapshot => delta_snapshot, |
|
452 | 416 | reg_delta_f0 => delta_f0, |
|
453 | 417 | reg_delta_f0_2 => delta_f0_2, |
|
454 | 418 | reg_delta_f1 => delta_f1, |
|
455 | 419 | reg_delta_f2 => delta_f2, |
|
456 | 420 | |
|
457 | 421 | enable_f0 => enable_f0, |
|
458 | 422 | enable_f1 => enable_f1, |
|
459 | 423 | enable_f2 => enable_f2, |
|
460 | 424 | enable_f3 => enable_f3, |
|
461 | 425 | burst_f0 => burst_f0, |
|
462 | 426 | burst_f1 => burst_f1, |
|
463 | 427 | burst_f2 => burst_f2, |
|
464 | 428 | |
|
465 | 429 | nb_data_by_buffer => nb_data_by_buffer, |
|
466 | 430 | nb_word_by_buffer => nb_word_by_buffer, |
|
467 | 431 | nb_snapshot_param => nb_snapshot_param, |
|
468 | 432 | status_full => status_full, |
|
469 | 433 | status_full_ack => status_full_ack, |
|
470 | 434 | status_full_err => status_full_err, |
|
471 | 435 | status_new_err => status_new_err, |
|
472 | 436 | |
|
473 | 437 | coarse_time => coarse_time, |
|
474 | 438 | fine_time => fine_time, |
|
475 | 439 | |
|
476 | 440 | --f0 |
|
477 | 441 | addr_data_f0 => addr_data_f0, |
|
478 | 442 | data_f0_in_valid => sample_f0_val, |
|
479 |
data_f0_in => sample_f0_data, |
|
|
443 | data_f0_in => sample_f0_data, | |
|
480 | 444 |
|
|
481 | 445 | addr_data_f1 => addr_data_f1, |
|
482 | 446 | data_f1_in_valid => sample_f1_val, |
|
483 |
data_f1_in => sample_f1_data, |
|
|
447 | data_f1_in => sample_f1_data, | |
|
484 | 448 |
|
|
485 | 449 | addr_data_f2 => addr_data_f2, |
|
486 | 450 | data_f2_in_valid => sample_f2_val, |
|
487 |
data_f2_in => sample_f2_data, |
|
|
451 | data_f2_in => sample_f2_data, | |
|
488 | 452 |
|
|
489 | 453 | addr_data_f3 => addr_data_f3, |
|
490 | 454 | data_f3_in_valid => sample_f3_val, |
|
491 |
data_f3_in => sample_f3_data, |
|
|
455 | data_f3_in => sample_f3_data, | |
|
492 | 456 |
|
|
493 | 457 | --f0 |
|
494 | 458 | data_f0_addr_out => data_f0_addr_out_s, |
|
495 | 459 | data_f0_data_out => data_f0_data_out, |
|
496 | 460 | data_f0_data_out_valid => data_f0_data_out_valid_s, |
|
497 | 461 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
|
498 | 462 | data_f0_data_out_ren => data_f0_data_out_ren, |
|
499 | 463 | --f1 |
|
500 | 464 | data_f1_addr_out => data_f1_addr_out_s, |
|
501 | 465 | data_f1_data_out => data_f1_data_out, |
|
502 | 466 | data_f1_data_out_valid => data_f1_data_out_valid_s, |
|
503 | 467 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, |
|
504 | 468 | data_f1_data_out_ren => data_f1_data_out_ren, |
|
505 | 469 | --f2 |
|
506 | 470 | data_f2_addr_out => data_f2_addr_out_s, |
|
507 | 471 | data_f2_data_out => data_f2_data_out, |
|
508 | 472 | data_f2_data_out_valid => data_f2_data_out_valid_s, |
|
509 | 473 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, |
|
510 | 474 | data_f2_data_out_ren => data_f2_data_out_ren, |
|
511 | 475 | --f3 |
|
512 | 476 | data_f3_addr_out => data_f3_addr_out_s, |
|
513 | 477 | data_f3_data_out => data_f3_data_out, |
|
514 | 478 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
515 | 479 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
516 | 480 | data_f3_data_out_ren => data_f3_data_out_ren , |
|
517 | 481 | |
|
518 | 482 | ------------------------------------------------------------------------- |
|
519 | 483 | observation_reg => OPEN |
|
520 | 484 | |
|
521 | 485 | ); |
|
522 | 486 | |
|
523 | 487 | |
|
524 | 488 | ----------------------------------------------------------------------------- |
|
525 | 489 | -- TEMP |
|
526 | 490 | ----------------------------------------------------------------------------- |
|
527 | 491 | |
|
528 | 492 | PROCESS (clk, rstn) |
|
529 | 493 | BEGIN -- PROCESS |
|
530 | 494 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
531 | 495 | data_f0_data_out_valid <= '0'; |
|
532 | 496 | data_f0_data_out_valid_burst <= '0'; |
|
533 | 497 | data_f1_data_out_valid <= '0'; |
|
534 | 498 | data_f1_data_out_valid_burst <= '0'; |
|
535 | 499 | data_f2_data_out_valid <= '0'; |
|
536 | 500 | data_f2_data_out_valid_burst <= '0'; |
|
537 | 501 | data_f3_data_out_valid <= '0'; |
|
538 | 502 | data_f3_data_out_valid_burst <= '0'; |
|
539 | 503 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
540 | 504 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
541 | 505 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
|
542 | 506 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
543 | 507 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
|
544 | 508 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
545 | 509 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
|
546 | 510 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
|
547 | 511 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
|
548 | 512 | END IF; |
|
549 | 513 | END PROCESS; |
|
550 | 514 | |
|
551 | 515 | data_f0_addr_out <= data_f0_addr_out_s; |
|
552 | 516 | data_f1_addr_out <= data_f1_addr_out_s; |
|
553 | 517 | data_f2_addr_out <= data_f2_addr_out_s; |
|
554 | 518 | data_f3_addr_out <= data_f3_addr_out_s; |
|
555 | 519 | |
|
556 | 520 | ----------------------------------------------------------------------------- |
|
557 | 521 | -- RoundRobin Selection For DMA |
|
558 | 522 | ----------------------------------------------------------------------------- |
|
559 | 523 | |
|
560 | 524 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
|
561 | 525 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
|
562 | 526 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
|
563 | 527 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
|
564 | 528 | |
|
565 | 529 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
566 | 530 | PORT MAP ( |
|
567 | 531 | clk => clk, |
|
568 | 532 | rstn => rstn, |
|
569 | 533 | in_valid => dma_rr_valid, |
|
570 | 534 | out_grant => dma_rr_grant_s); |
|
571 | 535 | |
|
572 | 536 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; |
|
573 | 537 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; |
|
574 | 538 | dma_rr_valid_ms(2) <= '0'; |
|
575 | 539 | dma_rr_valid_ms(3) <= '0'; |
|
576 | 540 | |
|
577 | 541 | RR_Arbiter_4_2 : RR_Arbiter_4 |
|
578 | 542 | PORT MAP ( |
|
579 | 543 | clk => clk, |
|
580 | 544 | rstn => rstn, |
|
581 | 545 | in_valid => dma_rr_valid_ms, |
|
582 | 546 | out_grant => dma_rr_grant_ms); |
|
583 | 547 | |
|
584 | 548 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; |
|
585 | 549 | |
|
586 | 550 | |
|
587 | 551 | ----------------------------------------------------------------------------- |
|
588 | 552 | -- in : dma_rr_grant |
|
589 | 553 | -- send |
|
590 | 554 | -- out : dma_sel |
|
591 | 555 | -- dma_valid_burst |
|
592 | 556 | -- dma_sel_valid |
|
593 | 557 | ----------------------------------------------------------------------------- |
|
594 | 558 | PROCESS (clk, rstn) |
|
595 | 559 | BEGIN -- PROCESS |
|
596 | 560 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
597 | 561 | dma_sel <= (OTHERS => '0'); |
|
598 | 562 | dma_send <= '0'; |
|
599 | 563 | dma_valid_burst <= '0'; |
|
600 | 564 | data_ms_done <= '0'; |
|
601 | 565 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
602 | 566 | IF run = '1' THEN |
|
603 | 567 | data_ms_done <= '0'; |
|
604 | 568 | IF dma_sel = "00000" OR dma_done = '1' THEN |
|
605 | 569 | dma_sel <= dma_rr_grant; |
|
606 | 570 | IF dma_rr_grant(0) = '1' THEN |
|
607 | 571 | dma_send <= '1'; |
|
608 | 572 | dma_valid_burst <= data_f0_data_out_valid_burst; |
|
609 | 573 | dma_sel_valid <= data_f0_data_out_valid; |
|
610 | 574 | ELSIF dma_rr_grant(1) = '1' THEN |
|
611 | 575 | dma_send <= '1'; |
|
612 | 576 | dma_valid_burst <= data_f1_data_out_valid_burst; |
|
613 | 577 | dma_sel_valid <= data_f1_data_out_valid; |
|
614 | 578 | ELSIF dma_rr_grant(2) = '1' THEN |
|
615 | 579 | dma_send <= '1'; |
|
616 | 580 | dma_valid_burst <= data_f2_data_out_valid_burst; |
|
617 | 581 | dma_sel_valid <= data_f2_data_out_valid; |
|
618 | 582 | ELSIF dma_rr_grant(3) = '1' THEN |
|
619 | 583 | dma_send <= '1'; |
|
620 | 584 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
621 | 585 | dma_sel_valid <= data_f3_data_out_valid; |
|
622 | 586 | ELSIF dma_rr_grant(4) = '1' THEN |
|
623 | 587 | dma_send <= '1'; |
|
624 | 588 | dma_valid_burst <= data_ms_valid_burst; |
|
625 | 589 | dma_sel_valid <= data_ms_valid; |
|
626 | 590 | END IF; |
|
627 | 591 | |
|
628 | 592 | IF dma_sel(4) = '1' THEN |
|
629 | 593 | data_ms_done <= '1'; |
|
630 | 594 | END IF; |
|
631 | 595 | ELSE |
|
632 | 596 | dma_sel <= dma_sel; |
|
633 | 597 | dma_send <= '0'; |
|
634 | 598 | END IF; |
|
635 | 599 | ELSE |
|
636 | 600 | data_ms_done <= '0'; |
|
637 | 601 | dma_sel <= (OTHERS => '0'); |
|
638 | 602 | dma_send <= '0'; |
|
639 | 603 | dma_valid_burst <= '0'; |
|
640 | 604 | END IF; |
|
641 | 605 | END IF; |
|
642 | 606 | END PROCESS; |
|
643 | 607 | |
|
644 | 608 | |
|
645 | 609 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
646 | 610 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
647 | 611 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
648 | 612 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE |
|
649 | 613 | data_ms_addr; |
|
650 | 614 | |
|
651 | 615 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE |
|
652 | 616 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
653 | 617 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
654 | 618 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE |
|
655 | 619 | data_ms_data; |
|
656 | 620 | |
|
657 | 621 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
658 | 622 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
659 | 623 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
660 | 624 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
661 | 625 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; |
|
662 | 626 | |
|
663 | 627 | dma_data_2 <= dma_data; |
|
664 | 628 | |
|
665 | 629 | |
|
666 | ||
|
667 | ||
|
668 | ||
|
669 | ----------------------------------------------------------------------------- | |
|
670 | -- DEBUG -- DMA IN | |
|
671 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; | |
|
672 | --debug_f0_data_dma_in <= dma_data; | |
|
673 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; | |
|
674 | --debug_f1_data_dma_in <= dma_data; | |
|
675 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; | |
|
676 | --debug_f2_data_dma_in <= dma_data; | |
|
677 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; | |
|
678 | --debug_f3_data_dma_in <= dma_data; | |
|
679 | ----------------------------------------------------------------------------- | |
|
680 | ||
|
681 | 630 | ----------------------------------------------------------------------------- |
|
682 | 631 | -- DMA |
|
683 | 632 | ----------------------------------------------------------------------------- |
|
684 | 633 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
685 | 634 | GENERIC MAP ( |
|
686 | 635 | tech => inferred, |
|
687 | 636 | hindex => hindex) |
|
688 | 637 | PORT MAP ( |
|
689 | 638 | HCLK => clk, |
|
690 | 639 | HRESETn => rstn, |
|
691 | 640 | run => run, |
|
692 | 641 | AHB_Master_In => ahbi, |
|
693 | 642 | AHB_Master_Out => ahbo, |
|
694 | 643 | |
|
695 | 644 | send => dma_send, |
|
696 | 645 | valid_burst => dma_valid_burst, |
|
697 | 646 | done => dma_done, |
|
698 | 647 | ren => dma_ren, |
|
699 | 648 | address => dma_address, |
|
700 | 649 | data => dma_data_2); |
|
701 | 650 | |
|
702 | 651 | ----------------------------------------------------------------------------- |
|
703 | 652 | -- Matrix Spectral |
|
704 | 653 | ----------------------------------------------------------------------------- |
|
705 | 654 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
706 | 655 | NOT(sample_f0_val) & NOT(sample_f0_val); |
|
707 | 656 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
708 | 657 | NOT(sample_f1_val) & NOT(sample_f1_val); |
|
709 | 658 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & |
|
710 | 659 | NOT(sample_f3_val) & NOT(sample_f3_val); |
|
711 | 660 | |
|
712 | 661 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
713 | 662 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
714 | 663 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
715 | 664 | |
|
716 | 665 | ------------------------------------------------------------------------------- |
|
717 | 666 | |
|
718 | 667 | ms_softandhard_rstn <= rstn AND run_ms AND run; |
|
719 | 668 | |
|
720 | 669 | ----------------------------------------------------------------------------- |
|
721 | 670 | lpp_lfr_ms_1 : lpp_lfr_ms |
|
722 | 671 | GENERIC MAP ( |
|
723 | 672 | Mem_use => Mem_use) |
|
724 | 673 | PORT MAP ( |
|
725 | 674 | clk => clk, |
|
726 | 675 | rstn => ms_softandhard_rstn, --rstn, |
|
727 | 676 | |
|
728 | 677 | coarse_time => coarse_time, |
|
729 | 678 | fine_time => fine_time, |
|
730 | 679 | |
|
731 | 680 | sample_f0_wen => sample_f0_wen, |
|
732 | 681 | sample_f0_wdata => sample_f0_wdata, |
|
733 | 682 | sample_f1_wen => sample_f1_wen, |
|
734 | 683 | sample_f1_wdata => sample_f1_wdata, |
|
735 |
sample_f2_wen => sample_f3_wen, -- TODO |
|
|
736 |
sample_f2_wdata => sample_f3_wdata,-- TODO |
|
|
684 | sample_f2_wen => sample_f3_wen, -- TODO | |
|
685 | sample_f2_wdata => sample_f3_wdata,-- TODO | |
|
737 | 686 | |
|
738 | 687 | dma_addr => data_ms_addr, -- |
|
739 | 688 | dma_data => data_ms_data, -- |
|
740 | 689 | dma_valid => data_ms_valid, -- |
|
741 | 690 | dma_valid_burst => data_ms_valid_burst, -- |
|
742 | 691 | dma_ren => data_ms_ren, -- |
|
743 | 692 | dma_done => data_ms_done, -- |
|
744 | 693 | |
|
745 |
ready_matrix_f0 => ready_matrix_f0 |
|
|
694 | ready_matrix_f0 => ready_matrix_f0, | |
|
746 | 695 | ready_matrix_f1 => ready_matrix_f1, |
|
747 | 696 | ready_matrix_f2 => ready_matrix_f2, |
|
748 | --error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
749 | 697 | error_bad_component_error => error_bad_component_error, |
|
750 |
error_buffer_full => error_buffer_full, |
|
|
751 |
|
|
|
698 | error_buffer_full => error_buffer_full, | |
|
699 | error_input_fifo_write => error_input_fifo_write, | |
|
752 | 700 |
|
|
753 | 701 | debug_reg => observation_reg, |
|
754 | 702 | |
|
755 |
status_ready_matrix_f0 => status_ready_matrix_f0 |
|
|
703 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
|
756 | 704 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
757 | 705 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
758 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO | |
|
759 | -- status_error_bad_component_error => status_error_bad_component_error,-- TODO | |
|
760 | 706 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
761 | 707 | config_active_interruption_onError => config_active_interruption_onError, |
|
762 |
addr_matrix_f0 => addr_matrix_f0 |
|
|
708 | addr_matrix_f0 => addr_matrix_f0, | |
|
763 | 709 | addr_matrix_f1 => addr_matrix_f1, |
|
764 | 710 | addr_matrix_f2 => addr_matrix_f2, |
|
765 | 711 | |
|
766 |
matrix_time_f0 => matrix_time_f0 |
|
|
712 | matrix_time_f0 => matrix_time_f0, | |
|
767 | 713 | matrix_time_f1 => matrix_time_f1, |
|
768 | 714 | matrix_time_f2 => matrix_time_f2); |
|
769 | 715 | |
|
770 | END beh; No newline at end of file | |
|
716 | END beh; |
This diff has been collapsed as it changes many lines, (706 lines changed) Show them Hide them | |||
@@ -1,569 +1,683 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | LIBRARY ieee; |
|
24 | 24 | USE ieee.std_logic_1164.ALL; |
|
25 | 25 | USE ieee.numeric_std.ALL; |
|
26 | 26 | LIBRARY grlib; |
|
27 | 27 | USE grlib.amba.ALL; |
|
28 | 28 | USE grlib.stdlib.ALL; |
|
29 | 29 | USE grlib.devices.ALL; |
|
30 | 30 | LIBRARY lpp; |
|
31 | USE lpp.lpp_lfr_pkg.ALL; | |
|
31 | 32 | USE lpp.lpp_amba.ALL; |
|
32 | 33 | USE lpp.apb_devices_list.ALL; |
|
33 | 34 | USE lpp.lpp_memory.ALL; |
|
34 | 35 | LIBRARY techmap; |
|
35 | 36 | USE techmap.gencomp.ALL; |
|
36 | 37 | |
|
37 | 38 | ENTITY lpp_lfr_apbreg IS |
|
38 | 39 | GENERIC ( |
|
39 | 40 | nb_data_by_buffer_size : INTEGER := 11; |
|
40 | 41 | nb_word_by_buffer_size : INTEGER := 11; |
|
41 |
nb_snapshot_param_size |
|
|
42 |
delta_vector_size |
|
|
43 |
delta_vector_size_f0_2 |
|
|
42 | nb_snapshot_param_size : INTEGER := 11; | |
|
43 | delta_vector_size : INTEGER := 20; | |
|
44 | delta_vector_size_f0_2 : INTEGER := 3; | |
|
44 | 45 | |
|
45 | pindex : INTEGER := 4; | |
|
46 | paddr : INTEGER := 4; | |
|
47 | pmask : INTEGER := 16#fff#; | |
|
48 | pirq_ms : INTEGER := 0; | |
|
49 | pirq_wfp : INTEGER := 1; | |
|
50 |
top_lfr_version |
|
|
46 | pindex : INTEGER := 4; | |
|
47 | paddr : INTEGER := 4; | |
|
48 | pmask : INTEGER := 16#fff#; | |
|
49 | pirq_ms : INTEGER := 0; | |
|
50 | pirq_wfp : INTEGER := 1; | |
|
51 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); | |
|
51 | 52 | PORT ( |
|
52 | 53 | -- AMBA AHB system signals |
|
53 | 54 | HCLK : IN STD_ULOGIC; |
|
54 | 55 | HRESETn : IN STD_ULOGIC; |
|
55 | 56 | |
|
56 | 57 | -- AMBA APB Slave Interface |
|
57 | 58 | apbi : IN apb_slv_in_type; |
|
58 | 59 | apbo : OUT apb_slv_out_type; |
|
59 | 60 | |
|
60 | 61 | --------------------------------------------------------------------------- |
|
61 | 62 | -- Spectral Matrix Reg |
|
62 |
run_ms |
|
|
63 | run_ms : OUT STD_LOGIC; | |
|
63 | 64 | -- IN |
|
64 |
ready_matrix_f0 |
|
|
65 |
ready_matrix_f1 |
|
|
66 |
ready_matrix_f2 |
|
|
65 | ready_matrix_f0 : IN STD_LOGIC; | |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
|
67 | 68 | |
|
68 |
error_bad_component_error |
|
|
69 |
error_buffer_full |
|
|
70 |
error_input_fifo_write |
|
|
69 | error_bad_component_error : IN STD_LOGIC; | |
|
70 | error_buffer_full : IN STD_LOGIC; -- TODO | |
|
71 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO | |
|
71 | 72 | |
|
72 |
debug_reg |
|
|
73 | -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
73 | 74 | |
|
74 | 75 | -- OUT |
|
75 |
status_ready_matrix_f0 |
|
|
76 |
status_ready_matrix_f1 |
|
|
77 |
status_ready_matrix_f2 |
|
|
76 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
|
77 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
|
78 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
|
78 | 79 | |
|
79 | 80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
80 | 81 | config_active_interruption_onError : OUT STD_LOGIC; |
|
81 | ||
|
82 |
addr_matrix_f0 |
|
|
83 |
|
|
|
84 |
addr_matrix_f |
|
|
85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | ||
|
87 |
matrix_time_f |
|
|
88 |
|
|
|
89 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
91 | ||
|
82 | ||
|
83 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | ||
|
87 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
88 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
89 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | ||
|
92 | 91 | --------------------------------------------------------------------------- |
|
93 | 92 | --------------------------------------------------------------------------- |
|
94 | 93 | -- WaveForm picker Reg |
|
95 |
status_full |
|
|
96 |
status_full_ack |
|
|
97 |
status_full_err |
|
|
98 |
status_new_err |
|
|
99 | ||
|
94 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
95 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
96 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
97 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
98 | ||
|
100 | 99 | -- OUT |
|
101 | 100 | data_shaping_BW : OUT STD_LOGIC; |
|
102 | 101 | data_shaping_SP0 : OUT STD_LOGIC; |
|
103 | 102 | data_shaping_SP1 : OUT STD_LOGIC; |
|
104 | 103 | data_shaping_R0 : OUT STD_LOGIC; |
|
105 | 104 | data_shaping_R1 : OUT STD_LOGIC; |
|
106 | 105 | |
|
107 |
delta_snapshot |
|
|
108 |
delta_f0 |
|
|
109 |
delta_f0_2 |
|
|
110 |
delta_f1 |
|
|
111 |
delta_f2 |
|
|
106 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
107 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
108 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
109 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
110 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
112 | 111 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
113 | 112 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
114 |
nb_snapshot_param |
|
|
113 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
115 | 114 | |
|
116 | 115 | enable_f0 : OUT STD_LOGIC; |
|
117 | 116 | enable_f1 : OUT STD_LOGIC; |
|
118 | 117 | enable_f2 : OUT STD_LOGIC; |
|
119 | 118 | enable_f3 : OUT STD_LOGIC; |
|
120 | 119 | |
|
121 | 120 | burst_f0 : OUT STD_LOGIC; |
|
122 | 121 | burst_f1 : OUT STD_LOGIC; |
|
123 | 122 | burst_f2 : OUT STD_LOGIC; |
|
124 | 123 | |
|
125 | 124 | run : OUT STD_LOGIC; |
|
126 | 125 | |
|
127 | 126 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
128 | 127 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
129 | 128 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
130 | 129 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
131 |
start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) |
|
|
132 | --------------------------------------------------------------------------- | |
|
133 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
134 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
135 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
136 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
137 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
138 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
139 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
140 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
141 | ||
|
130 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) | |
|
142 | 131 | --------------------------------------------------------------------------- |
|
143 | 132 | ); |
|
144 | 133 | |
|
145 | 134 | END lpp_lfr_apbreg; |
|
146 | 135 | |
|
147 | 136 | ARCHITECTURE beh OF lpp_lfr_apbreg IS |
|
148 | 137 | |
|
149 | 138 | CONSTANT REVISION : INTEGER := 1; |
|
150 | 139 | |
|
151 | 140 | CONSTANT pconfig : apb_config_type := ( |
|
152 | 141 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), |
|
153 | 142 | 1 => apb_iobar(paddr, pmask)); |
|
154 | 143 | |
|
155 | 144 | TYPE lpp_SpectralMatrix_regs IS RECORD |
|
156 | 145 | config_active_interruption_onNewMatrix : STD_LOGIC; |
|
157 | 146 | config_active_interruption_onError : STD_LOGIC; |
|
158 | 147 | config_ms_run : STD_LOGIC; |
|
159 | 148 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
160 |
|
|
|
161 |
status_ready_matrix_f |
|
|
162 |
status_ready_matrix_f |
|
|
163 | -- status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
149 | status_ready_matrix_f1_0 : STD_LOGIC; | |
|
150 | status_ready_matrix_f2_0 : STD_LOGIC; | |
|
151 | status_ready_matrix_f0_1 : STD_LOGIC; | |
|
152 | status_ready_matrix_f1_1 : STD_LOGIC; | |
|
153 | status_ready_matrix_f2_1 : STD_LOGIC; | |
|
164 | 154 | status_error_bad_component_error : STD_LOGIC; |
|
165 |
status_error_buffer_full : STD_LOGIC; |
|
|
166 |
status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
|
155 | status_error_buffer_full : STD_LOGIC; | |
|
156 | status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
157 | ||
|
167 | 158 |
|
|
168 |
|
|
|
169 |
addr_matrix_f1 |
|
|
170 |
addr_matrix_f |
|
|
159 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
160 | addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
161 | addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
162 | addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
163 | addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
171 | 164 | |
|
172 |
|
|
|
173 |
|
|
|
174 |
|
|
|
175 |
|
|
|
176 | ||
|
177 |
|
|
|
178 | -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
179 | -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
180 | -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
165 | time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
166 | time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
167 | time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
168 | time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
169 | time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
170 | time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
181 | 171 | END RECORD; |
|
182 | 172 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
183 | 173 | |
|
184 | 174 | TYPE lpp_WaveformPicker_regs IS RECORD |
|
185 |
status_full |
|
|
186 |
status_full_err |
|
|
187 |
status_new_err |
|
|
188 |
data_shaping_BW |
|
|
189 |
data_shaping_SP0 |
|
|
190 |
data_shaping_SP1 |
|
|
191 |
data_shaping_R0 |
|
|
192 |
data_shaping_R1 |
|
|
193 |
delta_snapshot |
|
|
194 |
delta_f0 |
|
|
175 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
176 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
177 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
178 | data_shaping_BW : STD_LOGIC; | |
|
179 | data_shaping_SP0 : STD_LOGIC; | |
|
180 | data_shaping_SP1 : STD_LOGIC; | |
|
181 | data_shaping_R0 : STD_LOGIC; | |
|
182 | data_shaping_R1 : STD_LOGIC; | |
|
183 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
184 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
195 | 185 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
196 |
delta_f1 |
|
|
197 |
delta_f2 |
|
|
186 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
187 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
198 | 188 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
199 | 189 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
200 |
nb_snapshot_param |
|
|
201 |
enable_f0 |
|
|
202 |
enable_f1 |
|
|
203 |
enable_f2 |
|
|
204 |
enable_f3 |
|
|
205 |
burst_f0 |
|
|
206 |
burst_f1 |
|
|
207 |
burst_f2 |
|
|
208 |
run |
|
|
209 |
addr_data_f0 |
|
|
210 |
addr_data_f1 |
|
|
211 |
addr_data_f2 |
|
|
212 |
addr_data_f3 |
|
|
213 |
start_date |
|
|
190 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
191 | enable_f0 : STD_LOGIC; | |
|
192 | enable_f1 : STD_LOGIC; | |
|
193 | enable_f2 : STD_LOGIC; | |
|
194 | enable_f3 : STD_LOGIC; | |
|
195 | burst_f0 : STD_LOGIC; | |
|
196 | burst_f1 : STD_LOGIC; | |
|
197 | burst_f2 : STD_LOGIC; | |
|
198 | run : STD_LOGIC; | |
|
199 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
200 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
201 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
202 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
203 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
214 | 204 | END RECORD; |
|
215 | 205 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
|
216 | 206 | |
|
217 | 207 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
218 | 208 | |
|
219 | 209 | ----------------------------------------------------------------------------- |
|
220 | 210 | -- IRQ |
|
221 | 211 | ----------------------------------------------------------------------------- |
|
222 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
|
223 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
224 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
225 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
226 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
227 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
|
212 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; | |
|
213 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
214 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
215 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
216 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); | |
|
217 | SIGNAL ored_irq_wfp : STD_LOGIC; | |
|
218 | ||
|
219 | ----------------------------------------------------------------------------- | |
|
220 | -- | |
|
221 | ----------------------------------------------------------------------------- | |
|
222 | SIGNAL reg0_ready_matrix_f0 : STD_LOGIC; | |
|
223 | SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
224 | SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
225 | ||
|
226 | SIGNAL reg1_ready_matrix_f0 : STD_LOGIC; | |
|
227 | SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
228 | SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
229 | ||
|
230 | SIGNAL reg0_ready_matrix_f1 : STD_LOGIC; | |
|
231 | SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
232 | SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
233 | ||
|
234 | SIGNAL reg1_ready_matrix_f1 : STD_LOGIC; | |
|
235 | SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
236 | SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
237 | ||
|
238 | SIGNAL reg0_ready_matrix_f2 : STD_LOGIC; | |
|
239 | SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
240 | SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
241 | ||
|
242 | SIGNAL reg1_ready_matrix_f2 : STD_LOGIC; | |
|
243 | SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
244 | SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
228 | 245 |
|
|
229 | 246 | BEGIN -- beh |
|
230 | 247 | |
|
231 |
status_ready_matrix_f0 |
|
|
232 |
-- status_ready_matrix_f |
|
|
233 |
status_ready_matrix_f |
|
|
234 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
|
235 | -- status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
|
236 | -- status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
|
248 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; | |
|
249 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
|
250 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
|
237 | 251 | |
|
238 | 252 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; |
|
239 | 253 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; |
|
240 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |
|
241 | -- addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
|
242 |
addr_matrix_f |
|
|
243 |
addr_matrix_f |
|
|
254 | ||
|
255 | ||
|
256 | -- addr_matrix_f0 <= reg_sp.addr_matrix_f0; | |
|
257 | -- addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |
|
258 | -- addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |
|
244 | 259 | |
|
245 | 260 | |
|
246 | 261 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; |
|
247 | 262 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; |
|
248 | 263 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; |
|
249 | 264 | data_shaping_R0 <= reg_wp.data_shaping_R0; |
|
250 | 265 | data_shaping_R1 <= reg_wp.data_shaping_R1; |
|
251 | 266 | |
|
252 |
delta_snapshot |
|
|
253 |
delta_f0 |
|
|
254 |
delta_f0_2 |
|
|
255 |
delta_f1 |
|
|
256 |
delta_f2 |
|
|
267 | delta_snapshot <= reg_wp.delta_snapshot; | |
|
268 | delta_f0 <= reg_wp.delta_f0; | |
|
269 | delta_f0_2 <= reg_wp.delta_f0_2; | |
|
270 | delta_f1 <= reg_wp.delta_f1; | |
|
271 | delta_f2 <= reg_wp.delta_f2; | |
|
257 | 272 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; |
|
258 | 273 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; |
|
259 |
nb_snapshot_param |
|
|
274 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
|
260 | 275 | |
|
261 | 276 | enable_f0 <= reg_wp.enable_f0; |
|
262 | 277 | enable_f1 <= reg_wp.enable_f1; |
|
263 | 278 | enable_f2 <= reg_wp.enable_f2; |
|
264 | 279 | enable_f3 <= reg_wp.enable_f3; |
|
265 | 280 | |
|
266 | 281 | burst_f0 <= reg_wp.burst_f0; |
|
267 | 282 | burst_f1 <= reg_wp.burst_f1; |
|
268 | 283 | burst_f2 <= reg_wp.burst_f2; |
|
269 | 284 | |
|
270 | 285 | run <= reg_wp.run; |
|
271 | 286 | |
|
272 | 287 | addr_data_f0 <= reg_wp.addr_data_f0; |
|
273 | 288 | addr_data_f1 <= reg_wp.addr_data_f1; |
|
274 | 289 | addr_data_f2 <= reg_wp.addr_data_f2; |
|
275 | 290 | addr_data_f3 <= reg_wp.addr_data_f3; |
|
276 | 291 | |
|
277 | 292 | start_date <= reg_wp.start_date; |
|
278 | 293 | |
|
279 | 294 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
|
280 | 295 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
281 | 296 | BEGIN -- PROCESS lpp_dma_top |
|
282 | 297 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
283 | 298 | reg_sp.config_active_interruption_onNewMatrix <= '0'; |
|
284 | 299 | reg_sp.config_active_interruption_onError <= '0'; |
|
285 | 300 | reg_sp.config_ms_run <= '1'; |
|
286 | 301 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
|
287 |
|
|
|
288 |
reg_sp.status_ready_matrix_f |
|
|
289 |
reg_sp.status_ready_matrix_f |
|
|
290 |
|
|
|
302 | reg_sp.status_ready_matrix_f1_0 <= '0'; | |
|
303 | reg_sp.status_ready_matrix_f2_0 <= '0'; | |
|
304 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
|
305 | reg_sp.status_ready_matrix_f1_1 <= '0'; | |
|
306 | reg_sp.status_ready_matrix_f2_1 <= '0'; | |
|
291 | 307 | reg_sp.status_error_bad_component_error <= '0'; |
|
292 | 308 | reg_sp.status_error_buffer_full <= '0'; |
|
293 | 309 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); |
|
294 | ||
|
295 |
reg_sp.addr_matrix_f0_0 |
|
|
296 |
|
|
|
297 |
reg_sp.addr_matrix_f |
|
|
298 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |
|
310 | ||
|
311 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |
|
312 | reg_sp.addr_matrix_f1_0 <= (OTHERS => '0'); | |
|
313 | reg_sp.addr_matrix_f2_0 <= (OTHERS => '0'); | |
|
314 | ||
|
315 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
|
316 | reg_sp.addr_matrix_f1_1 <= (OTHERS => '0'); | |
|
317 | reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); | |
|
299 | 318 | |
|
300 |
reg_sp. |
|
|
301 |
|
|
|
302 |
reg_sp. |
|
|
303 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); | |
|
304 |
|
|
|
305 |
|
|
|
306 |
|
|
|
307 | --reg_sp.fine_time_f2 <= (OTHERS => '0'); | |
|
308 | ||
|
309 | prdata <= (OTHERS => '0'); | |
|
319 | reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok | |
|
320 | reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok | |
|
321 | reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok | |
|
322 | ||
|
323 | reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok | |
|
324 | reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok | |
|
325 | reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok | |
|
326 | ||
|
327 | prdata <= (OTHERS => '0'); | |
|
310 | 328 | |
|
311 | 329 | apbo.pirq <= (OTHERS => '0'); |
|
312 | 330 | |
|
313 | 331 | status_full_ack <= (OTHERS => '0'); |
|
314 | 332 | |
|
315 |
reg_wp.data_shaping_BW |
|
|
316 |
reg_wp.data_shaping_SP0 |
|
|
317 |
reg_wp.data_shaping_SP1 |
|
|
318 |
reg_wp.data_shaping_R0 |
|
|
319 |
reg_wp.data_shaping_R1 |
|
|
320 |
reg_wp.enable_f0 |
|
|
321 |
reg_wp.enable_f1 |
|
|
322 |
reg_wp.enable_f2 |
|
|
323 |
reg_wp.enable_f3 |
|
|
324 |
reg_wp.burst_f0 |
|
|
325 |
reg_wp.burst_f1 |
|
|
326 |
reg_wp.burst_f2 |
|
|
327 |
reg_wp.run |
|
|
328 |
reg_wp.addr_data_f0 |
|
|
329 |
reg_wp.addr_data_f1 |
|
|
330 |
reg_wp.addr_data_f2 |
|
|
331 |
reg_wp.addr_data_f3 |
|
|
332 |
reg_wp.status_full |
|
|
333 |
reg_wp.status_full_err |
|
|
334 |
reg_wp.status_new_err |
|
|
335 |
reg_wp.delta_snapshot |
|
|
336 |
reg_wp.delta_f0 |
|
|
337 |
reg_wp.delta_f0_2 |
|
|
338 |
reg_wp.delta_f1 |
|
|
339 |
reg_wp.delta_f2 |
|
|
333 | reg_wp.data_shaping_BW <= '0'; | |
|
334 | reg_wp.data_shaping_SP0 <= '0'; | |
|
335 | reg_wp.data_shaping_SP1 <= '0'; | |
|
336 | reg_wp.data_shaping_R0 <= '0'; | |
|
337 | reg_wp.data_shaping_R1 <= '0'; | |
|
338 | reg_wp.enable_f0 <= '0'; | |
|
339 | reg_wp.enable_f1 <= '0'; | |
|
340 | reg_wp.enable_f2 <= '0'; | |
|
341 | reg_wp.enable_f3 <= '0'; | |
|
342 | reg_wp.burst_f0 <= '0'; | |
|
343 | reg_wp.burst_f1 <= '0'; | |
|
344 | reg_wp.burst_f2 <= '0'; | |
|
345 | reg_wp.run <= '0'; | |
|
346 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
|
347 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
|
348 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
|
349 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
|
350 | reg_wp.status_full <= (OTHERS => '0'); | |
|
351 | reg_wp.status_full_err <= (OTHERS => '0'); | |
|
352 | reg_wp.status_new_err <= (OTHERS => '0'); | |
|
353 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |
|
354 | reg_wp.delta_f0 <= (OTHERS => '0'); | |
|
355 | reg_wp.delta_f0_2 <= (OTHERS => '0'); | |
|
356 | reg_wp.delta_f1 <= (OTHERS => '0'); | |
|
357 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
|
340 | 358 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); |
|
341 |
reg_wp.nb_snapshot_param |
|
|
342 |
reg_wp.start_date |
|
|
359 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
|
360 | reg_wp.start_date <= (OTHERS => '0'); | |
|
343 | 361 | |
|
344 | 362 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
345 | 363 | |
|
346 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); | |
|
347 | -- reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
|
348 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); | |
|
349 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); | |
|
350 | ||
|
351 | --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0); | |
|
352 | --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0); | |
|
353 | --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0); | |
|
354 | --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0); | |
|
355 | ||
|
364 | reg_sp.time_matrix_f0_0 <= reg0_matrix_time_f0; -- ok | |
|
365 | reg_sp.time_matrix_f1_0 <= reg0_matrix_time_f1; -- ok | |
|
366 | reg_sp.time_matrix_f2_0 <= reg0_matrix_time_f2; -- ok | |
|
367 | ||
|
368 | reg_sp.time_matrix_f0_1 <= reg1_matrix_time_f0; -- ok | |
|
369 | reg_sp.time_matrix_f1_1 <= reg1_matrix_time_f1; -- ok | |
|
370 | reg_sp.time_matrix_f2_1 <= reg1_matrix_time_f2; -- ok | |
|
371 | ||
|
356 | 372 | status_full_ack <= (OTHERS => '0'); |
|
357 | 373 | |
|
358 |
reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0 |
|
|
359 |
|
|
|
360 |
reg_sp.status_ready_matrix_f |
|
|
361 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
|
374 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0; | |
|
375 | reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1; | |
|
376 | reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2; | |
|
362 | 377 | |
|
363 | -- reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
|
364 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
365 | ||
|
366 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; | |
|
367 |
reg_sp.status_error_ |
|
|
368 | reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1); | |
|
369 |
reg_sp.status_error_ |
|
|
378 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0; | |
|
379 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; | |
|
380 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; | |
|
381 | ||
|
382 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
|
383 | ||
|
384 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; | |
|
385 | reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); | |
|
386 | reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1); | |
|
387 | reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2); | |
|
370 | 388 | |
|
371 | 389 | |
|
372 | ||
|
373 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
|
374 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
|
375 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
|
376 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
|
390 | ||
|
391 | all_status : FOR I IN 3 DOWNTO 0 LOOP | |
|
377 | 392 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; |
|
378 |
reg_wp.status_full_err(I) <= status_full_err(I) |
|
|
379 |
reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run |
|
|
393 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
|
394 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run; | |
|
380 | 395 | END LOOP all_status; |
|
381 | 396 | |
|
382 | 397 | paddr := "000000"; |
|
383 | 398 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
384 | 399 | prdata <= (OTHERS => '0'); |
|
385 | 400 | IF apbi.psel(pindex) = '1' THEN |
|
386 | 401 | -- APB DMA READ -- |
|
387 | 402 | CASE paddr(7 DOWNTO 2) IS |
|
388 | -- | |
|
403 | --0 | |
|
389 | 404 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; |
|
390 | 405 | prdata(1) <= reg_sp.config_active_interruption_onError; |
|
391 | 406 | prdata(2) <= reg_sp.config_ms_run; |
|
407 | --1 | |
|
392 | 408 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
393 |
|
|
|
394 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |
|
395 |
prdata(3) <= reg_sp.status_ready_matrix_f |
|
|
396 |
|
|
|
397 |
prdata(5) <= reg_sp.status_ |
|
|
398 |
prdata(6) <= reg_sp.status_error_b |
|
|
399 |
prdata(7) <= reg_sp.status_error_ |
|
|
400 |
prdata(8) <= reg_sp.status_error_input_fifo_write( |
|
|
401 |
prdata(9) <= reg_sp.status_error_input_fifo_write( |
|
|
402 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
|
403 | -- WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
404 |
WHEN "000 |
|
|
405 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |
|
406 | ||
|
407 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; | |
|
408 |
|
|
|
409 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; | |
|
410 |
WHEN "00 |
|
|
411 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; | |
|
412 | -- WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; | |
|
413 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; | |
|
414 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; | |
|
415 | ||
|
416 | WHEN "001111" => prdata <= debug_reg; | |
|
417 | --------------------------------------------------------------------- | |
|
418 |
WHEN "0 |
|
|
409 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
410 | prdata(2) <= reg_sp.status_ready_matrix_f1_0; | |
|
411 | prdata(3) <= reg_sp.status_ready_matrix_f1_1; | |
|
412 | prdata(4) <= reg_sp.status_ready_matrix_f2_0; | |
|
413 | prdata(5) <= reg_sp.status_ready_matrix_f2_1; | |
|
414 | prdata(6) <= reg_sp.status_error_bad_component_error; | |
|
415 | prdata(7) <= reg_sp.status_error_buffer_full; | |
|
416 | prdata(8) <= reg_sp.status_error_input_fifo_write(0); | |
|
417 | prdata(9) <= reg_sp.status_error_input_fifo_write(1); | |
|
418 | prdata(10) <= reg_sp.status_error_input_fifo_write(2); | |
|
419 | --2 | |
|
420 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |
|
421 | --3 | |
|
422 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
423 | --4 | |
|
424 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0; | |
|
425 | --5 | |
|
426 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1; | |
|
427 | --6 | |
|
428 | WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0; | |
|
429 | --7 | |
|
430 | WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1; | |
|
431 | --8 | |
|
432 | WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16); | |
|
433 | --9 | |
|
434 | WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0); | |
|
435 | --10 | |
|
436 | WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16); | |
|
437 | --11 | |
|
438 | WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0); | |
|
439 | --12 | |
|
440 | WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16); | |
|
441 | --13 | |
|
442 | WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0); | |
|
443 | --14 | |
|
444 | WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16); | |
|
445 | --15 | |
|
446 | WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0); | |
|
447 | --16 | |
|
448 | WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16); | |
|
449 | --17 | |
|
450 | WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0); | |
|
451 | --18 | |
|
452 | WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); | |
|
453 | --19 | |
|
454 | WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); | |
|
455 | --------------------------------------------------------------------- | |
|
456 | --20 | |
|
457 | WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW; | |
|
419 | 458 | prdata(1) <= reg_wp.data_shaping_SP0; |
|
420 | 459 | prdata(2) <= reg_wp.data_shaping_SP1; |
|
421 | 460 | prdata(3) <= reg_wp.data_shaping_R0; |
|
422 | 461 | prdata(4) <= reg_wp.data_shaping_R1; |
|
423 | WHEN "010001" => prdata(0) <= reg_wp.enable_f0; | |
|
462 | --21 | |
|
463 | WHEN "010101" => prdata(0) <= reg_wp.enable_f0; | |
|
424 | 464 | prdata(1) <= reg_wp.enable_f1; |
|
425 | 465 | prdata(2) <= reg_wp.enable_f2; |
|
426 | 466 | prdata(3) <= reg_wp.enable_f3; |
|
427 | 467 | prdata(4) <= reg_wp.burst_f0; |
|
428 | 468 | prdata(5) <= reg_wp.burst_f1; |
|
429 | 469 | prdata(6) <= reg_wp.burst_f2; |
|
430 | 470 | prdata(7) <= reg_wp.run; |
|
431 | WHEN "010010" => prdata <= reg_wp.addr_data_f0; | |
|
432 |
WHEN "010 |
|
|
433 | WHEN "010100" => prdata <= reg_wp.addr_data_f2; | |
|
434 |
WHEN "0101 |
|
|
435 | WHEN "010110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
|
471 | --22 | |
|
472 | WHEN "010110" => prdata <= reg_wp.addr_data_f0; | |
|
473 | --23 | |
|
474 | WHEN "010111" => prdata <= reg_wp.addr_data_f1; | |
|
475 | --24 | |
|
476 | WHEN "011000" => prdata <= reg_wp.addr_data_f2; | |
|
477 | --25 | |
|
478 | WHEN "011001" => prdata <= reg_wp.addr_data_f3; | |
|
479 | --26 | |
|
480 | WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |
|
436 | 481 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
|
437 | 482 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; |
|
438 | WHEN "010111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
|
439 |
WHEN "0110 |
|
|
440 | WHEN "011001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
|
441 |
WHEN "011 |
|
|
442 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
|
443 |
WHEN "01110 |
|
|
444 | WHEN "011101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
|
445 |
WHEN "011110" => prdata( |
|
|
446 | WHEN "011111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
447 | ---------------------------------------------------- | |
|
448 | WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); | |
|
449 |
WHEN "10000 |
|
|
450 | WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); | |
|
451 |
WHEN "1000 |
|
|
452 | WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); | |
|
453 |
WHEN "100 |
|
|
454 | WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); | |
|
455 |
WHEN "100 |
|
|
456 | ---------------------------------------------------- | |
|
457 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
|
483 | --27 | |
|
484 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
|
485 | --28 | |
|
486 | WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
|
487 | --29 | |
|
488 | WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
|
489 | --30 | |
|
490 | WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
|
491 | --31 | |
|
492 | WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
|
493 | --32 | |
|
494 | WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
|
495 | --33 | |
|
496 | WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
|
497 | --34 | |
|
498 | WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
|
499 | --35 | |
|
500 | WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
501 | ---------------------------------------------------- | |
|
502 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
|
458 | 503 | WHEN OTHERS => NULL; |
|
459 | 504 | |
|
460 | 505 | END CASE; |
|
461 | 506 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
462 | 507 | -- APB DMA WRITE -- |
|
463 | 508 | CASE paddr(7 DOWNTO 2) IS |
|
464 | 509 | -- |
|
465 | 510 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
466 | 511 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
467 | 512 | reg_sp.config_ms_run <= apbi.pwdata(2); |
|
468 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
|
469 |
|
|
|
470 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |
|
471 |
reg_sp.status_ready_matrix_f |
|
|
472 |
|
|
|
473 |
reg_sp.status_ |
|
|
474 |
reg_sp.status_error_b |
|
|
475 |
reg_sp.status_error_ |
|
|
476 |
reg_sp.status_error_input_fifo_write( |
|
|
477 |
reg_sp.status_error_input_fifo_write( |
|
|
478 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
479 | -- WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
480 |
WHEN "000 |
|
|
481 |
WHEN "000 |
|
|
482 | -- | |
|
483 |
WHEN "0 |
|
|
513 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
|
514 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
|
515 | reg_sp.status_ready_matrix_f1_0 <= apbi.pwdata(2); | |
|
516 | reg_sp.status_ready_matrix_f1_1 <= apbi.pwdata(3); | |
|
517 | reg_sp.status_ready_matrix_f2_0 <= apbi.pwdata(4); | |
|
518 | reg_sp.status_ready_matrix_f2_1 <= apbi.pwdata(5); | |
|
519 | reg_sp.status_error_bad_component_error <= apbi.pwdata(6); | |
|
520 | reg_sp.status_error_buffer_full <= apbi.pwdata(7); | |
|
521 | reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(8); | |
|
522 | reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(9); | |
|
523 | reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(10); | |
|
524 | --2 | |
|
525 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
526 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
527 | WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata; | |
|
528 | WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata; | |
|
529 | WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata; | |
|
530 | WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; | |
|
531 | --8 to 19 | |
|
532 | --20 | |
|
533 | WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
|
484 | 534 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
|
485 | 535 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); |
|
486 | 536 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
|
487 | 537 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); |
|
488 |
WHEN "010 |
|
|
538 | WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0); | |
|
489 | 539 | reg_wp.enable_f1 <= apbi.pwdata(1); |
|
490 | 540 | reg_wp.enable_f2 <= apbi.pwdata(2); |
|
491 | 541 | reg_wp.enable_f3 <= apbi.pwdata(3); |
|
492 | 542 | reg_wp.burst_f0 <= apbi.pwdata(4); |
|
493 | 543 | reg_wp.burst_f1 <= apbi.pwdata(5); |
|
494 | 544 | reg_wp.burst_f2 <= apbi.pwdata(6); |
|
495 | 545 | reg_wp.run <= apbi.pwdata(7); |
|
496 | WHEN "010010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
|
497 |
WHEN "010 |
|
|
498 |
WHEN "0101 |
|
|
499 |
WHEN "01 |
|
|
500 |
WHEN "0101 |
|
|
546 | --22 | |
|
547 | WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata; | |
|
548 | WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata; | |
|
549 | WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata; | |
|
550 | WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata; | |
|
551 | --26 | |
|
552 | WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |
|
501 | 553 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
|
502 | 554 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
|
503 | 555 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); |
|
504 | 556 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); |
|
505 | 557 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); |
|
506 | 558 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); |
|
507 |
WHEN "01 |
|
|
508 |
WHEN "011 |
|
|
509 |
WHEN "011 |
|
|
510 |
WHEN "011 |
|
|
511 |
WHEN "011 |
|
|
512 |
WHEN " |
|
|
513 |
WHEN " |
|
|
514 |
WHEN " |
|
|
515 |
WHEN " |
|
|
559 | WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
560 | WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
561 | WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
562 | WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
563 | WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
|
564 | WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
565 | WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
|
566 | WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
|
567 | WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
516 | 568 | -- |
|
517 | 569 | WHEN OTHERS => NULL; |
|
518 | 570 | END CASE; |
|
519 | 571 | END IF; |
|
520 | 572 | END IF; |
|
521 | 573 | |
|
522 |
apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 |
|
|
523 | -- ready_matrix_f0_1 OR | |
|
574 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR | |
|
524 | 575 | ready_matrix_f1 OR |
|
525 | 576 | ready_matrix_f2) |
|
526 | ) | |
|
527 | OR | |
|
528 | (reg_sp.config_active_interruption_onError AND ( | |
|
529 |
|
|
|
530 | error_bad_component_error | |
|
531 | OR error_buffer_full | |
|
532 |
|
|
|
533 |
|
|
|
534 | OR error_input_fifo_write(2)) | |
|
535 | )); | |
|
577 | ) | |
|
578 | OR | |
|
579 | (reg_sp.config_active_interruption_onError AND ( | |
|
580 | error_bad_component_error | |
|
581 | OR error_buffer_full | |
|
582 | OR error_input_fifo_write(0) | |
|
583 | OR error_input_fifo_write(1) | |
|
584 | OR error_input_fifo_write(2)) | |
|
585 | )); | |
|
536 | 586 | |
|
537 | 587 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; |
|
538 | 588 | |
|
539 | 589 | END IF; |
|
540 | 590 | END PROCESS lpp_lfr_apbreg; |
|
541 | 591 | |
|
542 | 592 | apbo.pindex <= pindex; |
|
543 | 593 | apbo.pconfig <= pconfig; |
|
544 | 594 | apbo.prdata <= prdata; |
|
545 | 595 | |
|
546 | 596 | ----------------------------------------------------------------------------- |
|
547 | 597 | -- IRQ |
|
548 | 598 | ----------------------------------------------------------------------------- |
|
549 | 599 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; |
|
550 | ||
|
600 | ||
|
551 | 601 | PROCESS (HCLK, HRESETn) |
|
552 | 602 | BEGIN -- PROCESS |
|
553 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
554 |
irq_wfp_reg |
|
|
555 |
ELSIF HCLK' |
|
|
556 |
irq_wfp_reg <= irq_wfp_reg_s; |
|
|
603 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
604 | irq_wfp_reg <= (OTHERS => '0'); | |
|
605 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
606 | irq_wfp_reg <= irq_wfp_reg_s; | |
|
557 | 607 | END IF; |
|
558 | 608 | END PROCESS; |
|
559 | 609 | |
|
560 | all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
|
610 | all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE | |
|
561 | 611 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); |
|
562 | 612 | END GENERATE all_irq_wfp; |
|
563 | 613 | |
|
564 | 614 | irq_wfp_ZERO <= (OTHERS => '0'); |
|
565 | 615 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; |
|
566 | 616 | |
|
567 | 617 | run_ms <= reg_sp.config_ms_run; |
|
618 | ||
|
619 | ----------------------------------------------------------------------------- | |
|
620 | -- | |
|
621 | ----------------------------------------------------------------------------- | |
|
622 | lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer | |
|
623 | PORT MAP ( | |
|
624 | clk => HCLK, | |
|
625 | rstn => HRESETn, | |
|
626 | ||
|
627 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, | |
|
628 | reg0_ready_matrix => reg0_ready_matrix_f0, | |
|
629 | reg0_addr_matrix => reg0_addr_matrix_f0, | |
|
630 | reg0_matrix_time => reg0_matrix_time_f0, | |
|
631 | ||
|
632 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1, | |
|
633 | reg1_ready_matrix => reg1_ready_matrix_f0, | |
|
634 | reg1_addr_matrix => reg1_addr_matrix_f0, | |
|
635 | reg1_matrix_time => reg1_matrix_time_f0, | |
|
636 | ||
|
637 | ready_matrix => ready_matrix_f0, | |
|
638 | status_ready_matrix => status_ready_matrix_f0, | |
|
639 | addr_matrix => addr_matrix_f0, | |
|
640 | matrix_time => matrix_time_f0); | |
|
641 | ||
|
642 | lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer | |
|
643 | PORT MAP ( | |
|
644 | clk => HCLK, | |
|
645 | rstn => HRESETn, | |
|
646 | ||
|
647 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, | |
|
648 | reg0_ready_matrix => reg0_ready_matrix_f1, | |
|
649 | reg0_addr_matrix => reg0_addr_matrix_f1, | |
|
650 | reg0_matrix_time => reg0_matrix_time_f1, | |
|
651 | ||
|
652 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1, | |
|
653 | reg1_ready_matrix => reg1_ready_matrix_f1, | |
|
654 | reg1_addr_matrix => reg1_addr_matrix_f1, | |
|
655 | reg1_matrix_time => reg1_matrix_time_f1, | |
|
656 | ||
|
657 | ready_matrix => ready_matrix_f1, | |
|
658 | status_ready_matrix => status_ready_matrix_f1, | |
|
659 | addr_matrix => addr_matrix_f1, | |
|
660 | matrix_time => matrix_time_f1); | |
|
568 | 661 | |
|
569 | END beh; | |
|
662 | lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer | |
|
663 | PORT MAP ( | |
|
664 | clk => HCLK, | |
|
665 | rstn => HRESETn, | |
|
666 | ||
|
667 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, | |
|
668 | reg0_ready_matrix => reg0_ready_matrix_f2, | |
|
669 | reg0_addr_matrix => reg0_addr_matrix_f2, | |
|
670 | reg0_matrix_time => reg0_matrix_time_f2, | |
|
671 | ||
|
672 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1, | |
|
673 | reg1_ready_matrix => reg1_ready_matrix_f2, | |
|
674 | reg1_addr_matrix => reg1_addr_matrix_f2, | |
|
675 | reg1_matrix_time => reg1_matrix_time_f2, | |
|
676 | ||
|
677 | ready_matrix => ready_matrix_f2, | |
|
678 | status_ready_matrix => status_ready_matrix_f2, | |
|
679 | addr_matrix => addr_matrix_f2, | |
|
680 | matrix_time => matrix_time_f2); | |
|
681 | ||
|
682 | ||
|
683 | END beh; No newline at end of file |
@@ -1,395 +1,406 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | |
|
4 | 4 | LIBRARY grlib; |
|
5 | 5 | USE grlib.amba.ALL; |
|
6 | 6 | |
|
7 | 7 | LIBRARY lpp; |
|
8 | 8 | USE lpp.lpp_ad_conv.ALL; |
|
9 | 9 | USE lpp.iir_filter.ALL; |
|
10 | 10 | USE lpp.FILTERcfg.ALL; |
|
11 | 11 | USE lpp.lpp_memory.ALL; |
|
12 | 12 | LIBRARY techmap; |
|
13 | 13 | USE techmap.gencomp.ALL; |
|
14 | 14 | |
|
15 | 15 | PACKAGE lpp_lfr_pkg IS |
|
16 | 16 | ----------------------------------------------------------------------------- |
|
17 | 17 | -- TEMP |
|
18 | 18 | ----------------------------------------------------------------------------- |
|
19 | 19 | COMPONENT lpp_lfr_ms_test |
|
20 | 20 | GENERIC ( |
|
21 | 21 | Mem_use : INTEGER); |
|
22 | 22 | PORT ( |
|
23 | 23 | clk : IN STD_LOGIC; |
|
24 | 24 | rstn : IN STD_LOGIC; |
|
25 | 25 | |
|
26 | 26 | -- TIME |
|
27 | 27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
28 | 28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
29 | 29 | -- |
|
30 | 30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
31 | 31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
32 | 32 | -- |
|
33 | 33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
34 | 34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
35 | 35 | -- |
|
36 | 36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
37 | 37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
38 | 38 | |
|
39 | 39 | |
|
40 | 40 | |
|
41 | 41 | --------------------------------------------------------------------------- |
|
42 | 42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
43 | 43 | |
|
44 | 44 | -- |
|
45 | 45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
46 | 46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
47 | 47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
48 | 48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
49 | 49 | |
|
50 | 50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
51 | 51 | |
|
52 | 52 | -- IN |
|
53 | 53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
54 | 54 | |
|
55 | 55 | ----------------------------------------------------------------------------- |
|
56 | 56 | |
|
57 | 57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
58 | 58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
59 | 59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
60 | 60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
61 | 61 | |
|
62 | 62 | SM_correlation_start : OUT STD_LOGIC; |
|
63 | 63 | SM_correlation_auto : OUT STD_LOGIC; |
|
64 | 64 | SM_correlation_done : IN STD_LOGIC |
|
65 | 65 | ); |
|
66 | 66 | END COMPONENT; |
|
67 | 67 | |
|
68 | 68 | |
|
69 | 69 | ----------------------------------------------------------------------------- |
|
70 | 70 | COMPONENT lpp_lfr_ms |
|
71 | 71 | GENERIC ( |
|
72 | 72 | Mem_use : INTEGER |
|
73 | 73 | ); |
|
74 | 74 | PORT ( |
|
75 | 75 | clk : IN STD_LOGIC; |
|
76 | 76 | rstn : IN STD_LOGIC; |
|
77 | 77 | |
|
78 | 78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
79 | 79 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
80 | 80 | |
|
81 | 81 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
82 | 82 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
83 | 83 | |
|
84 | 84 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
85 | 85 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
86 | 86 | |
|
87 | 87 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
88 | 88 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
89 | 89 | |
|
90 | 90 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | 91 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 | 92 | dma_valid : OUT STD_LOGIC; |
|
93 | 93 | dma_valid_burst : OUT STD_LOGIC; |
|
94 | 94 | dma_ren : IN STD_LOGIC; |
|
95 | 95 | dma_done : IN STD_LOGIC; |
|
96 | 96 | |
|
97 | 97 | ready_matrix_f0 : OUT STD_LOGIC; |
|
98 | 98 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
99 | 99 | ready_matrix_f1 : OUT STD_LOGIC; |
|
100 | 100 | ready_matrix_f2 : OUT STD_LOGIC; |
|
101 | 101 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
102 | 102 | error_bad_component_error : OUT STD_LOGIC; |
|
103 | 103 | error_buffer_full : OUT STD_LOGIC; |
|
104 | 104 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
105 | 105 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
106 | 106 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
107 | 107 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
108 | 108 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
109 | 109 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
110 | 110 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
111 | 111 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
112 | 112 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
113 | 113 | config_active_interruption_onError : IN STD_LOGIC; |
|
114 | 114 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
115 | 115 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
116 | 116 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
117 | 117 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
118 | 118 | |
|
119 | 119 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
120 | 120 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
121 | 121 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
122 | 122 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
123 | 123 | END COMPONENT; |
|
124 | 124 | |
|
125 | 125 | COMPONENT lpp_lfr_ms_fsmdma |
|
126 | 126 | PORT ( |
|
127 | 127 | HCLK : IN STD_ULOGIC; |
|
128 | 128 | HRESETn : IN STD_ULOGIC; |
|
129 | 129 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
130 | 130 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
131 | 131 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
132 | 132 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | 133 | fifo_empty : IN STD_LOGIC; |
|
134 | 134 | fifo_ren : OUT STD_LOGIC; |
|
135 | 135 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
136 | 136 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
137 | 137 | --fifo_empty : IN STD_LOGIC; |
|
138 | 138 | --fifo_ren : OUT STD_LOGIC; |
|
139 | 139 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | 140 | --header_val : IN STD_LOGIC; |
|
141 | 141 | --header_ack : OUT STD_LOGIC; |
|
142 | 142 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
143 | 143 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
144 | 144 | dma_valid : OUT STD_LOGIC; |
|
145 | 145 | dma_valid_burst : OUT STD_LOGIC; |
|
146 | 146 | dma_ren : IN STD_LOGIC; |
|
147 | 147 | dma_done : IN STD_LOGIC; |
|
148 | 148 | ready_matrix_f0 : OUT STD_LOGIC; |
|
149 | 149 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
150 | 150 | ready_matrix_f1 : OUT STD_LOGIC; |
|
151 | 151 | ready_matrix_f2 : OUT STD_LOGIC; |
|
152 | 152 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
153 | 153 | error_bad_component_error : OUT STD_LOGIC; |
|
154 | 154 | error_buffer_full : OUT STD_LOGIC; |
|
155 | 155 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
156 | 156 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
157 | 157 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
158 | 158 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
159 | 159 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
160 | 160 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
161 | 161 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
162 | 162 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
163 | 163 | config_active_interruption_onError : IN STD_LOGIC; |
|
164 | 164 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
165 | 165 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
166 | 166 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
167 | 167 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
168 | 168 | |
|
169 | 169 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
170 | 170 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
171 | 171 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
172 | 172 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
173 | 173 | ); |
|
174 | 174 | END COMPONENT; |
|
175 | 175 | |
|
176 | 176 | COMPONENT lpp_lfr_ms_FFT |
|
177 | 177 | PORT ( |
|
178 | 178 | clk : IN STD_LOGIC; |
|
179 | 179 | rstn : IN STD_LOGIC; |
|
180 | 180 | sample_valid : IN STD_LOGIC; |
|
181 | 181 | fft_read : IN STD_LOGIC; |
|
182 | 182 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
183 | 183 | sample_load : OUT STD_LOGIC; |
|
184 | 184 | fft_pong : OUT STD_LOGIC; |
|
185 | 185 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
186 | 186 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
187 | 187 | fft_data_valid : OUT STD_LOGIC; |
|
188 | 188 | fft_ready : OUT STD_LOGIC); |
|
189 | 189 | END COMPONENT; |
|
190 | 190 | |
|
191 | 191 | COMPONENT lpp_lfr_filter |
|
192 | 192 | GENERIC ( |
|
193 | 193 | Mem_use : INTEGER); |
|
194 | 194 | PORT ( |
|
195 | 195 | sample : IN Samples(7 DOWNTO 0); |
|
196 | 196 | sample_val : IN STD_LOGIC; |
|
197 | 197 | clk : IN STD_LOGIC; |
|
198 | 198 | rstn : IN STD_LOGIC; |
|
199 | 199 | data_shaping_SP0 : IN STD_LOGIC; |
|
200 | 200 | data_shaping_SP1 : IN STD_LOGIC; |
|
201 | 201 | data_shaping_R0 : IN STD_LOGIC; |
|
202 | 202 | data_shaping_R1 : IN STD_LOGIC; |
|
203 | 203 | sample_f0_val : OUT STD_LOGIC; |
|
204 | 204 | sample_f1_val : OUT STD_LOGIC; |
|
205 | 205 | sample_f2_val : OUT STD_LOGIC; |
|
206 | 206 | sample_f3_val : OUT STD_LOGIC; |
|
207 | 207 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
208 | 208 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
209 | 209 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
210 | 210 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); |
|
211 | 211 | END COMPONENT; |
|
212 | 212 | |
|
213 | 213 | COMPONENT lpp_lfr |
|
214 | 214 | GENERIC ( |
|
215 | 215 | Mem_use : INTEGER; |
|
216 | 216 | nb_data_by_buffer_size : INTEGER; |
|
217 | 217 | nb_word_by_buffer_size : INTEGER; |
|
218 | 218 | nb_snapshot_param_size : INTEGER; |
|
219 | 219 | delta_vector_size : INTEGER; |
|
220 | 220 | delta_vector_size_f0_2 : INTEGER; |
|
221 | 221 | pindex : INTEGER; |
|
222 | 222 | paddr : INTEGER; |
|
223 | 223 | pmask : INTEGER; |
|
224 | 224 | pirq_ms : INTEGER; |
|
225 | 225 | pirq_wfp : INTEGER; |
|
226 | 226 | hindex : INTEGER; |
|
227 | 227 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
|
228 | 228 | ); |
|
229 | 229 | PORT ( |
|
230 | 230 | clk : IN STD_LOGIC; |
|
231 | 231 | rstn : IN STD_LOGIC; |
|
232 | 232 | sample_B : IN Samples(2 DOWNTO 0); |
|
233 | 233 | sample_E : IN Samples(4 DOWNTO 0); |
|
234 | 234 | sample_val : IN STD_LOGIC; |
|
235 | 235 | apbi : IN apb_slv_in_type; |
|
236 | 236 | apbo : OUT apb_slv_out_type; |
|
237 | 237 | ahbi : IN AHB_Mst_In_Type; |
|
238 | 238 | ahbo : OUT AHB_Mst_Out_Type; |
|
239 | 239 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
240 | 240 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
241 | 241 | data_shaping_BW : OUT STD_LOGIC; |
|
242 | 242 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
243 | 243 | ); |
|
244 | 244 | END COMPONENT; |
|
245 | 245 | |
|
246 | 246 | ----------------------------------------------------------------------------- |
|
247 | 247 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) |
|
248 | 248 | ----------------------------------------------------------------------------- |
|
249 | 249 | COMPONENT lpp_lfr_WFP_nMS |
|
250 | 250 | GENERIC ( |
|
251 | 251 | Mem_use : INTEGER; |
|
252 | 252 | nb_data_by_buffer_size : INTEGER; |
|
253 | 253 | nb_word_by_buffer_size : INTEGER; |
|
254 | 254 | nb_snapshot_param_size : INTEGER; |
|
255 | 255 | delta_vector_size : INTEGER; |
|
256 | 256 | delta_vector_size_f0_2 : INTEGER; |
|
257 | 257 | pindex : INTEGER; |
|
258 | 258 | paddr : INTEGER; |
|
259 | 259 | pmask : INTEGER; |
|
260 | 260 | pirq_ms : INTEGER; |
|
261 | 261 | pirq_wfp : INTEGER; |
|
262 | 262 | hindex : INTEGER; |
|
263 | 263 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
264 | 264 | PORT ( |
|
265 | 265 | clk : IN STD_LOGIC; |
|
266 | 266 | rstn : IN STD_LOGIC; |
|
267 | 267 | sample_B : IN Samples(2 DOWNTO 0); |
|
268 | 268 | sample_E : IN Samples(4 DOWNTO 0); |
|
269 | 269 | sample_val : IN STD_LOGIC; |
|
270 | 270 | apbi : IN apb_slv_in_type; |
|
271 | 271 | apbo : OUT apb_slv_out_type; |
|
272 | 272 | ahbi : IN AHB_Mst_In_Type; |
|
273 | 273 | ahbo : OUT AHB_Mst_Out_Type; |
|
274 | 274 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
275 | 275 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
276 | 276 | data_shaping_BW : OUT STD_LOGIC; |
|
277 | 277 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
278 | 278 | END COMPONENT; |
|
279 | 279 | ----------------------------------------------------------------------------- |
|
280 | 280 | COMPONENT lpp_lfr_apbreg |
|
281 | 281 | GENERIC ( |
|
282 | 282 | nb_data_by_buffer_size : INTEGER; |
|
283 | 283 | nb_word_by_buffer_size : INTEGER; |
|
284 | 284 | nb_snapshot_param_size : INTEGER; |
|
285 | 285 | delta_vector_size : INTEGER; |
|
286 | 286 | delta_vector_size_f0_2 : INTEGER; |
|
287 | 287 | pindex : INTEGER; |
|
288 | 288 | paddr : INTEGER; |
|
289 | 289 | pmask : INTEGER; |
|
290 | 290 | pirq_ms : INTEGER; |
|
291 | 291 | pirq_wfp : INTEGER; |
|
292 | 292 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
293 | 293 | PORT ( |
|
294 | 294 | HCLK : IN STD_ULOGIC; |
|
295 | 295 | HRESETn : IN STD_ULOGIC; |
|
296 | 296 | apbi : IN apb_slv_in_type; |
|
297 | 297 | apbo : OUT apb_slv_out_type; |
|
298 | 298 | run_ms : OUT STD_LOGIC; |
|
299 |
ready_matrix_f0 |
|
|
299 | ready_matrix_f0 : IN STD_LOGIC; | |
|
300 | 300 | ready_matrix_f1 : IN STD_LOGIC; |
|
301 | 301 | ready_matrix_f2 : IN STD_LOGIC; |
|
302 | 302 | error_bad_component_error : IN STD_LOGIC; |
|
303 | 303 | error_buffer_full : in STD_LOGIC; |
|
304 | 304 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
305 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
306 |
status_ready_matrix_f0 |
|
|
305 | --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
306 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
|
307 | 307 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
308 | 308 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
309 | 309 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
310 | 310 | config_active_interruption_onError : OUT STD_LOGIC; |
|
311 |
addr_matrix_f0 |
|
|
311 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
312 | 312 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
313 | 313 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
314 | 314 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
315 |
matrix_time_f0 |
|
|
315 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
316 | 316 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
317 | 317 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
318 | 318 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
319 | 319 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
320 | 320 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
321 | 321 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
322 | 322 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
323 | 323 | data_shaping_BW : OUT STD_LOGIC; |
|
324 | 324 | data_shaping_SP0 : OUT STD_LOGIC; |
|
325 | 325 | data_shaping_SP1 : OUT STD_LOGIC; |
|
326 | 326 | data_shaping_R0 : OUT STD_LOGIC; |
|
327 | 327 | data_shaping_R1 : OUT STD_LOGIC; |
|
328 | 328 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
329 | 329 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
330 | 330 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
331 | 331 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
332 | 332 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
333 | 333 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
334 | 334 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
335 | 335 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
336 | 336 | enable_f0 : OUT STD_LOGIC; |
|
337 | 337 | enable_f1 : OUT STD_LOGIC; |
|
338 | 338 | enable_f2 : OUT STD_LOGIC; |
|
339 | 339 | enable_f3 : OUT STD_LOGIC; |
|
340 | 340 | burst_f0 : OUT STD_LOGIC; |
|
341 | 341 | burst_f1 : OUT STD_LOGIC; |
|
342 | 342 | burst_f2 : OUT STD_LOGIC; |
|
343 | 343 | run : OUT STD_LOGIC; |
|
344 | 344 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
345 | 345 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
346 | 346 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
347 | 347 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
348 |
start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) |
|
|
349 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
350 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
351 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
352 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
353 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
354 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
355 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
356 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
|
348 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) | |
|
349 | ); | |
|
357 | 350 | END COMPONENT; |
|
358 | 351 | |
|
359 | 352 | |
|
360 | 353 | |
|
361 | 354 | COMPONENT lpp_top_ms |
|
362 | 355 | GENERIC ( |
|
363 | 356 | Mem_use : INTEGER; |
|
364 | 357 | nb_burst_available_size : INTEGER; |
|
365 | 358 | nb_snapshot_param_size : INTEGER; |
|
366 | 359 | delta_snapshot_size : INTEGER; |
|
367 | 360 | delta_f2_f0_size : INTEGER; |
|
368 | 361 | delta_f2_f1_size : INTEGER; |
|
369 | 362 | pindex : INTEGER; |
|
370 | 363 | paddr : INTEGER; |
|
371 | 364 | pmask : INTEGER; |
|
372 | 365 | pirq_ms : INTEGER; |
|
373 | 366 | pirq_wfp : INTEGER; |
|
374 | 367 | hindex_wfp : INTEGER; |
|
375 | 368 | hindex_ms : INTEGER); |
|
376 | 369 | PORT ( |
|
377 | 370 | clk : IN STD_LOGIC; |
|
378 | 371 | rstn : IN STD_LOGIC; |
|
379 | 372 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
380 | 373 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
381 | 374 | sample_val : IN STD_LOGIC; |
|
382 | 375 | apbi : IN apb_slv_in_type; |
|
383 | 376 | apbo : OUT apb_slv_out_type; |
|
384 | 377 | ahbi_ms : IN AHB_Mst_In_Type; |
|
385 | 378 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
386 | 379 | data_shaping_BW : OUT STD_LOGIC; |
|
387 | 380 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
388 | 381 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
389 | 382 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
390 | 383 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
391 | 384 | |
|
392 | 385 | ); |
|
393 | 386 | END COMPONENT; |
|
387 | ||
|
388 | COMPONENT lpp_apbreg_ms_pointer | |
|
389 | PORT ( | |
|
390 | clk : IN STD_LOGIC; | |
|
391 | rstn : IN STD_LOGIC; | |
|
392 | reg0_status_ready_matrix : IN STD_LOGIC; | |
|
393 | reg0_ready_matrix : OUT STD_LOGIC; | |
|
394 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
395 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
396 | reg1_status_ready_matrix : IN STD_LOGIC; | |
|
397 | reg1_ready_matrix : OUT STD_LOGIC; | |
|
398 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
399 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
400 | ready_matrix : IN STD_LOGIC; | |
|
401 | status_ready_matrix : OUT STD_LOGIC; | |
|
402 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
403 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
|
404 | END COMPONENT; | |
|
394 | 405 | |
|
395 | 406 | END lpp_lfr_pkg; |
General Comments 0
You need to be logged in to leave comments.
Login now