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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
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29 | 29 | USE techmap.gencomp.ALL; |
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30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.sim.ALL; |
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32 | 32 | USE gaisler.memctrl.ALL; |
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33 | 33 | USE gaisler.leon3.ALL; |
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34 | 34 | USE gaisler.uart.ALL; |
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35 | 35 | USE gaisler.misc.ALL; |
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36 | 36 | USE gaisler.spacewire.ALL; |
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37 | 37 | LIBRARY esa; |
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38 | 38 | USE esa.memoryctrl.ALL; |
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39 | 39 | LIBRARY lpp; |
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40 | 40 | USE lpp.lpp_memory.ALL; |
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41 | 41 | USE lpp.lpp_ad_conv.ALL; |
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42 | 42 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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43 | 43 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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44 | 44 | USE lpp.iir_filter.ALL; |
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45 | 45 | USE lpp.general_purpose.ALL; |
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46 | 46 | USE lpp.lpp_lfr_management.ALL; |
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47 | 47 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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48 | 48 | USE lpp.lpp_bootloader_pkg.ALL; |
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49 | 49 | |
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50 | 50 | --library proasic3l; |
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51 | 51 | --use proasic3l.all; |
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52 | 52 | |
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53 | 53 | ENTITY LFR_EQM IS |
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54 | 54 | GENERIC ( |
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55 | 55 | Mem_use : INTEGER := use_RAM; |
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56 | 56 | USE_BOOTLOADER : INTEGER := 0; |
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57 | 57 | USE_ADCDRIVER : INTEGER := 0; |
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58 | 58 | tech : INTEGER := apa3e; |
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59 | tech_leon : INTEGER := apa3e | |
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59 | tech_leon : INTEGER := apa3e; | |
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60 | DEBUG_FORCE_DATA_DMA : INTEGER := 1; | |
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61 | USE_DEBUG_VECTOR : INTEGER := 1 | |
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60 | 62 | ); |
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61 | 63 | |
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62 | 64 | PORT ( |
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63 | 65 | clk50MHz : IN STD_ULOGIC; |
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64 | 66 | clk49_152MHz : IN STD_ULOGIC; |
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65 | 67 | reset : IN STD_ULOGIC; |
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66 | 68 | |
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69 | TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); | |
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70 | ||
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67 | 71 |
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68 | TAG1 : IN STD_ULOGIC; -- DSU rx data | |
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69 | TAG3 : OUT STD_ULOGIC; -- DSU tx data | |
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72 | --TAG1 : IN STD_ULOGIC; -- DSU rx data | |
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73 | --TAG3 : OUT STD_ULOGIC; -- DSU tx data | |
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70 | 74 | -- UART APB --------------------------------------------------------------- |
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71 | TAG2 : IN STD_ULOGIC; -- UART1 rx data | |
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72 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data | |
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75 | --TAG2 : IN STD_ULOGIC; -- UART1 rx data | |
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76 | --TAG4 : OUT STD_ULOGIC; -- UART1 tx data | |
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73 | 77 | -- RAM -------------------------------------------------------------------- |
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74 | 78 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); |
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75 | 79 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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76 | 80 | |
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77 | 81 | nSRAM_MBE : INOUT STD_LOGIC; -- new |
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78 | 82 | nSRAM_E1 : OUT STD_LOGIC; -- new |
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79 | 83 | nSRAM_E2 : OUT STD_LOGIC; -- new |
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80 | 84 | -- nSRAM_SCRUB : OUT STD_LOGIC; -- new |
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81 | 85 | nSRAM_W : OUT STD_LOGIC; -- new |
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82 | 86 | nSRAM_G : OUT STD_LOGIC; -- new |
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83 | 87 | nSRAM_BUSY : IN STD_LOGIC; -- new |
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84 | 88 | -- SPW -------------------------------------------------------------------- |
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85 | 89 | spw1_en : OUT STD_LOGIC; -- new |
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86 | 90 | spw1_din : IN STD_LOGIC; |
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87 | 91 | spw1_sin : IN STD_LOGIC; |
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88 | 92 | spw1_dout : OUT STD_LOGIC; |
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89 | 93 | spw1_sout : OUT STD_LOGIC; |
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90 | 94 | spw2_en : OUT STD_LOGIC; -- new |
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91 | 95 | spw2_din : IN STD_LOGIC; |
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92 | 96 | spw2_sin : IN STD_LOGIC; |
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93 | 97 | spw2_dout : OUT STD_LOGIC; |
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94 | 98 | spw2_sout : OUT STD_LOGIC; |
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95 | 99 | -- ADC -------------------------------------------------------------------- |
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96 | 100 | bias_fail_sw : OUT STD_LOGIC; |
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97 | 101 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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98 | 102 | ADC_smpclk : OUT STD_LOGIC; |
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99 | 103 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
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100 | 104 | -- DAC -------------------------------------------------------------------- |
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101 | 105 | DAC_SDO : OUT STD_LOGIC; |
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102 | 106 | DAC_SCK : OUT STD_LOGIC; |
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103 | 107 | DAC_SYNC : OUT STD_LOGIC; |
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104 | 108 | DAC_CAL_EN : OUT STD_LOGIC; |
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105 | 109 | -- HK --------------------------------------------------------------------- |
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106 | 110 | HK_smpclk : OUT STD_LOGIC; |
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107 | 111 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
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108 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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112 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--; | |
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109 | 113 | --------------------------------------------------------------------------- |
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110 | TAG8 : OUT STD_LOGIC | |
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114 | -- TAG8 : OUT STD_LOGIC | |
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111 | 115 | ); |
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112 | 116 | |
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113 | 117 | END LFR_EQM; |
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114 | 118 | |
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115 | 119 | |
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116 | 120 | ARCHITECTURE beh OF LFR_EQM IS |
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117 | 121 | |
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118 | 122 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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119 | 123 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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120 | 124 | ----------------------------------------------------------------------------- |
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121 | 125 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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122 | 126 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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123 | 127 | |
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124 | 128 | -- CONSTANTS |
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125 | 129 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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126 | 130 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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127 | 131 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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128 | 132 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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129 | 133 | |
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130 | 134 | SIGNAL apbi_ext : apb_slv_in_type; |
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131 | 135 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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132 | 136 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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133 | 137 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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134 | 138 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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135 | 139 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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136 | 140 | |
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137 | 141 | -- Spacewire signals |
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138 | 142 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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139 | 143 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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140 | 144 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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141 | 145 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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142 | 146 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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143 | 147 | SIGNAL spw_clk : STD_LOGIC; |
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144 | 148 | SIGNAL swni : grspw_in_type; |
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145 | 149 | SIGNAL swno : grspw_out_type; |
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146 | 150 | |
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147 | 151 | --GPIO |
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148 | 152 | SIGNAL gpioi : gpio_in_type; |
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149 | 153 | SIGNAL gpioo : gpio_out_type; |
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150 | 154 | |
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151 | 155 | -- AD Converter ADS7886 |
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152 | 156 | SIGNAL sample : Samples14v(8 DOWNTO 0); |
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153 | 157 | SIGNAL sample_s : Samples(8 DOWNTO 0); |
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154 | 158 | SIGNAL sample_val : STD_LOGIC; |
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155 | 159 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); |
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156 | 160 | |
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157 | 161 | ----------------------------------------------------------------------------- |
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158 | 162 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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159 | 163 | |
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160 | 164 | ----------------------------------------------------------------------------- |
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161 | 165 | SIGNAL rstn_25 : STD_LOGIC; |
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162 | 166 | SIGNAL rstn_24 : STD_LOGIC; |
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163 | 167 | |
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164 | 168 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
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165 | 169 | SIGNAL LFR_rstn : STD_LOGIC; |
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166 | 170 | |
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167 | 171 | SIGNAL ADC_smpclk_s : STD_LOGIC; |
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168 | 172 | |
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169 | 173 | SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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170 | 174 | |
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171 | 175 | SIGNAL clk50MHz_int : STD_LOGIC := '0'; |
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172 | 176 | SIGNAL clk_25_int : STD_LOGIC := '0'; |
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173 | 177 | |
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174 | 178 | component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; |
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175 | 179 | |
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176 | 180 | SIGNAL rstn_50 : STD_LOGIC; |
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177 | 181 | SIGNAL clk_lock : STD_LOGIC; |
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178 | 182 | SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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179 | 183 | SIGNAL nSRAM_BUSY_reg : STD_LOGIC; |
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184 | ||
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185 | SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
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186 | SIGNAL ahbrxd: STD_LOGIC; | |
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187 | SIGNAL ahbtxd: STD_LOGIC; | |
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188 | SIGNAL urxd1 : STD_LOGIC; | |
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189 | SIGNAL utxd1 : STD_LOGIC; | |
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180 | 190 | BEGIN -- beh |
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181 | 191 | |
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182 | 192 | ----------------------------------------------------------------------------- |
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183 | 193 | -- CLK_LOCK |
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184 | 194 | ----------------------------------------------------------------------------- |
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185 | 195 | rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); |
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186 | 196 | |
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187 | 197 | PROCESS (clk50MHz_int, rstn_50) |
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188 | 198 | BEGIN -- PROCESS |
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189 | 199 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) |
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190 | 200 | clk_lock <= '0'; |
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191 | 201 | clk_busy_counter <= (OTHERS => '0'); |
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192 | 202 | nSRAM_BUSY_reg <= '0'; |
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193 | 203 | ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge |
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194 | 204 | nSRAM_BUSY_reg <= nSRAM_BUSY; |
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195 | 205 | IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN |
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196 | 206 | IF clk_busy_counter = "1111" THEN |
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197 | 207 | clk_lock <= '1'; |
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198 | 208 | ELSE |
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199 | 209 | clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); |
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200 | 210 | END IF; |
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201 | 211 | END IF; |
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202 | 212 | END IF; |
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203 | 213 | END PROCESS; |
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204 | 214 | |
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205 | 215 | ----------------------------------------------------------------------------- |
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206 | 216 | -- CLK |
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207 | 217 | ----------------------------------------------------------------------------- |
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208 | 218 | rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); |
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209 | 219 | rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); |
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210 | 220 | |
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211 | 221 | --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); |
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212 | 222 | clk50MHz_int <= clk50MHz; |
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213 | 223 | |
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214 | 224 | PROCESS(clk50MHz_int) |
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215 | 225 | BEGIN |
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216 | 226 | IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN |
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217 | 227 | --clk_25_int <= NOT clk_25_int; |
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218 | 228 | clk_25 <= NOT clk_25; |
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219 | 229 | END IF; |
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220 | 230 | END PROCESS; |
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221 | 231 | --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); |
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222 | 232 | |
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223 | 233 | PROCESS(clk49_152MHz) |
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224 | 234 | BEGIN |
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225 | 235 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
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226 | 236 | clk_24 <= NOT clk_24; |
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227 | 237 | END IF; |
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228 | 238 | END PROCESS; |
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229 | 239 | |
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230 | 240 | ----------------------------------------------------------------------------- |
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231 | 241 | -- |
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232 | 242 | leon3_soc_1 : leon3_soc |
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233 | 243 | GENERIC MAP ( |
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234 | 244 | fabtech => tech_leon, |
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235 | 245 | memtech => tech_leon, |
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236 | 246 | padtech => inferred, |
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237 | 247 | clktech => inferred, |
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238 | 248 | disas => 0, |
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239 | 249 | dbguart => 0, |
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240 | 250 | pclow => 2, |
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241 | 251 | clk_freq => 25000, |
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242 | 252 | IS_RADHARD => 0, |
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243 | 253 | NB_CPU => 1, |
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244 | 254 | ENABLE_FPU => 1, |
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245 | 255 | FPU_NETLIST => 0, |
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246 | 256 | ENABLE_DSU => 1, |
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247 | 257 | ENABLE_AHB_UART => 1, |
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248 | 258 | ENABLE_APB_UART => 1, |
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249 | 259 | ENABLE_IRQMP => 1, |
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250 | 260 | ENABLE_GPT => 1, |
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251 | 261 | NB_AHB_MASTER => NB_AHB_MASTER, |
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252 | 262 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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253 | 263 | NB_APB_SLAVE => NB_APB_SLAVE, |
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254 | 264 | ADDRESS_SIZE => 19, |
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255 | 265 | USES_IAP_MEMCTRLR => 1, |
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256 | 266 | BYPASS_EDAC_MEMCTRLR => '0', |
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257 | 267 | SRBANKSZ => 8) |
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258 | 268 | PORT MAP ( |
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259 | 269 | clk => clk_25, |
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260 | 270 | reset => rstn_25, |
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261 | 271 | errorn => OPEN, |
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262 | 272 | |
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263 | ahbrxd => TAG1, | |
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264 | ahbtxd => TAG3, | |
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265 | urxd1 => TAG2, | |
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266 | utxd1 => TAG4, | |
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273 | ahbrxd => ahbrxd, -- INPUT | |
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274 | ahbtxd => ahbtxd, -- OUTPUT | |
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275 | urxd1 => urxd1, -- INPUT | |
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276 | utxd1 => utxd1, -- OUTPUT | |
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267 | 277 | |
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268 | 278 | address => address, |
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269 | 279 | data => data, |
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270 | 280 | nSRAM_BE0 => OPEN, |
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271 | 281 | nSRAM_BE1 => OPEN, |
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272 | 282 | nSRAM_BE2 => OPEN, |
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273 | 283 | nSRAM_BE3 => OPEN, |
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274 | 284 | nSRAM_WE => nSRAM_W, |
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275 | 285 | nSRAM_CE => nSRAM_CE, |
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276 | 286 | nSRAM_OE => nSRAM_G, |
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277 | 287 | nSRAM_READY => nSRAM_BUSY, |
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278 | 288 | SRAM_MBE => nSRAM_MBE, |
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279 | 289 | |
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280 | 290 | apbi_ext => apbi_ext, |
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281 | 291 | apbo_ext => apbo_ext, |
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282 | 292 | ahbi_s_ext => ahbi_s_ext, |
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283 | 293 | ahbo_s_ext => ahbo_s_ext, |
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284 | 294 | ahbi_m_ext => ahbi_m_ext, |
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285 | 295 | ahbo_m_ext => ahbo_m_ext); |
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286 | 296 | |
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287 | 297 | |
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288 | 298 | nSRAM_E1 <= nSRAM_CE(0); |
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289 | 299 | nSRAM_E2 <= nSRAM_CE(1); |
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290 | 300 | |
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291 | 301 | ------------------------------------------------------------------------------- |
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292 | 302 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
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293 | 303 | ------------------------------------------------------------------------------- |
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294 | 304 | apb_lfr_management_1 : apb_lfr_management |
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295 | 305 | GENERIC MAP ( |
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296 | 306 | tech => tech, |
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297 | 307 | pindex => 6, |
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298 | 308 | paddr => 6, |
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299 | 309 | pmask => 16#fff#, |
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300 | 310 | --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
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301 | 311 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
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302 | 312 | PORT MAP ( |
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303 | 313 | clk25MHz => clk_25, |
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304 | 314 | resetn_25MHz => rstn_25, -- TODO |
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305 | 315 | --clk24_576MHz => clk_24, -- 49.152MHz/2 |
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306 | 316 | --resetn_24_576MHz => rstn_24, -- TODO |
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307 | 317 | |
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308 | 318 | grspw_tick => swno.tickout, |
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309 | 319 | apbi => apbi_ext, |
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310 | 320 | apbo => apbo_ext(6), |
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311 | 321 | |
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312 | 322 | HK_sample => sample_s(8), |
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313 | 323 | HK_val => sample_val, |
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314 | 324 | HK_sel => HK_SEL, |
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315 | 325 | |
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316 | 326 | DAC_SDO => DAC_SDO, |
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317 | 327 | DAC_SCK => DAC_SCK, |
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318 | 328 | DAC_SYNC => DAC_SYNC, |
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319 | 329 | DAC_CAL_EN => DAC_CAL_EN, |
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320 | 330 | |
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321 | 331 | coarse_time => coarse_time, |
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322 | 332 | fine_time => fine_time, |
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323 | 333 | LFR_soft_rstn => LFR_soft_rstn |
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324 | 334 | ); |
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325 | 335 | |
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326 | 336 | ----------------------------------------------------------------------- |
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327 | 337 | --- SpaceWire -------------------------------------------------------- |
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328 | 338 | ----------------------------------------------------------------------- |
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329 | 339 | |
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330 | 340 | ------------------------------------------------------------------------------ |
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331 | 341 | -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ |
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332 | 342 | ------------------------------------------------------------------------------ |
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333 | 343 | spw1_en <= '1'; |
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334 | 344 | spw2_en <= '1'; |
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335 | 345 | ------------------------------------------------------------------------------ |
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336 | 346 | -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ |
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337 | 347 | ------------------------------------------------------------------------------ |
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338 | 348 | |
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339 | 349 | --spw_clk <= clk50MHz; |
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340 | 350 | --spw_rxtxclk <= spw_clk; |
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341 | 351 | --spw_rxclkn <= NOT spw_rxtxclk; |
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342 | 352 | |
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343 | 353 | -- PADS for SPW1 |
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344 | 354 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
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345 | 355 | PORT MAP (spw1_din, dtmp(0)); |
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346 | 356 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
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347 | 357 | PORT MAP (spw1_sin, stmp(0)); |
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348 | 358 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
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349 | 359 | PORT MAP (spw1_dout, swno.d(0)); |
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350 | 360 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
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351 | 361 | PORT MAP (spw1_sout, swno.s(0)); |
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352 | 362 | -- PADS FOR SPW2 |
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353 | 363 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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354 | 364 | PORT MAP (spw2_din, dtmp(1)); |
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355 | 365 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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356 | 366 | PORT MAP (spw2_sin, stmp(1)); |
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357 | 367 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
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358 | 368 | PORT MAP (spw2_dout, swno.d(1)); |
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359 | 369 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
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360 | 370 | PORT MAP (spw2_sout, swno.s(1)); |
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361 | 371 | |
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362 | 372 | -- GRSPW PHY |
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363 | 373 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
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364 | 374 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
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365 | 375 | spw_phy0 : grspw_phy |
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366 | 376 | GENERIC MAP( |
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367 | 377 | tech => tech_leon, |
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368 | 378 | rxclkbuftype => 1, |
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369 | 379 | scantest => 0) |
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370 | 380 | PORT MAP( |
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371 | 381 | rxrst => swno.rxrst, |
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372 | 382 | di => dtmp(j), |
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373 | 383 | si => stmp(j), |
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374 | 384 | rxclko => spw_rxclk(j), |
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375 | 385 | do => swni.d(j), |
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376 | 386 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
377 | 387 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
378 | 388 | END GENERATE spw_inputloop; |
|
379 | 389 | |
|
380 | 390 | -- SPW core |
|
381 | 391 | sw0 : grspwm GENERIC MAP( |
|
382 | 392 | tech => tech_leon, |
|
383 | 393 | hindex => 1, |
|
384 | 394 | pindex => 5, |
|
385 | 395 | paddr => 5, |
|
386 | 396 | pirq => 11, |
|
387 | 397 | sysfreq => 25000, -- CPU_FREQ |
|
388 | 398 | rmap => 1, |
|
389 | 399 | rmapcrc => 1, |
|
390 | 400 | fifosize1 => 16, |
|
391 | 401 | fifosize2 => 16, |
|
392 | 402 | rxclkbuftype => 1, |
|
393 | 403 | rxunaligned => 0, |
|
394 | 404 | rmapbufs => 4, |
|
395 | 405 | ft => 0, |
|
396 | 406 | netlist => 0, |
|
397 | 407 | ports => 2, |
|
398 | 408 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
399 | 409 | memtech => tech_leon, |
|
400 | 410 | destkey => 2, |
|
401 | 411 | spwcore => 1 |
|
402 | 412 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
403 | 413 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
404 | 414 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
405 | 415 | ) |
|
406 | 416 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
|
407 | 417 | spw_rxclk(1), |
|
408 | 418 | clk50MHz_int, |
|
409 | 419 | clk50MHz_int, |
|
410 | 420 | -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, |
|
411 | 421 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
412 | 422 | swni, swno); |
|
413 | 423 | |
|
414 | 424 | swni.tickin <= '0'; |
|
415 | 425 | swni.rmapen <= '1'; |
|
416 | 426 | swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz |
|
417 | 427 | swni.tickinraw <= '0'; |
|
418 | 428 | swni.timein <= (OTHERS => '0'); |
|
419 | 429 | swni.dcrstval <= (OTHERS => '0'); |
|
420 | 430 | swni.timerrstval <= (OTHERS => '0'); |
|
421 | 431 | |
|
422 | 432 | ------------------------------------------------------------------------------- |
|
423 | 433 | -- LFR ------------------------------------------------------------------------ |
|
424 | 434 | ------------------------------------------------------------------------------- |
|
425 | 435 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
|
426 | 436 | |
|
427 | 437 | lpp_lfr_1 : lpp_lfr |
|
428 | 438 | GENERIC MAP ( |
|
429 | 439 | Mem_use => Mem_use, |
|
440 | tech => tech, | |
|
430 | 441 | nb_data_by_buffer_size => 32, |
|
431 | 442 | --nb_word_by_buffer_size => 30, |
|
432 | 443 | nb_snapshot_param_size => 32, |
|
433 | 444 | delta_vector_size => 32, |
|
434 | 445 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
435 | 446 | pindex => 15, |
|
436 | 447 | paddr => 15, |
|
437 | 448 | pmask => 16#fff#, |
|
438 | 449 | pirq_ms => 6, |
|
439 | 450 | pirq_wfp => 14, |
|
440 | 451 | hindex => 2, |
|
441 |
top_lfr_version => X"02014 |
|
|
452 | top_lfr_version => X"020148", -- aa.bb.cc version | |
|
442 | 453 | -- AA : BOARD NUMBER |
|
443 | 454 | -- 0 => MINI_LFR |
|
444 | 455 | -- 1 => EM |
|
445 | 456 | -- 2 => EQM (with A3PE3000) |
|
457 | DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA) | |
|
446 | 458 | PORT MAP ( |
|
447 | 459 | clk => clk_25, |
|
448 | 460 | rstn => LFR_rstn, |
|
449 | 461 | sample_B => sample_s(2 DOWNTO 0), |
|
450 | 462 | sample_E => sample_s(7 DOWNTO 3), |
|
451 | 463 | sample_val => sample_val, |
|
452 | 464 | apbi => apbi_ext, |
|
453 | 465 | apbo => apbo_ext(15), |
|
454 | 466 | ahbi => ahbi_m_ext, |
|
455 | 467 | ahbo => ahbo_m_ext(2), |
|
456 | 468 | coarse_time => coarse_time, |
|
457 | 469 | fine_time => fine_time, |
|
458 | 470 | data_shaping_BW => bias_fail_sw, |
|
459 |
debug_vector => |
|
|
471 | debug_vector => debug_vector, | |
|
460 | 472 | debug_vector_ms => OPEN); --, |
|
461 | 473 | --observation_vector_0 => OPEN, |
|
462 | 474 | --observation_vector_1 => OPEN, |
|
463 | 475 | --observation_reg => observation_reg); |
|
464 | 476 | |
|
465 | 477 | |
|
466 | 478 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
467 | 479 | sample_s(I) <= sample(I) & '0' & '0'; |
|
468 | 480 | END GENERATE all_sample; |
|
469 | 481 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); |
|
470 | 482 | |
|
471 | 483 | ----------------------------------------------------------------------------- |
|
472 | 484 | -- |
|
473 | 485 | ----------------------------------------------------------------------------- |
|
474 | 486 | USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE |
|
475 | 487 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter |
|
476 | 488 | GENERIC MAP ( |
|
477 | 489 | ChanelCount => 9, |
|
478 | 490 | ncycle_cnv_high => 13, |
|
479 | 491 | ncycle_cnv => 25, |
|
480 | 492 | FILTER_ENABLED => 16#FF#) |
|
481 | 493 | PORT MAP ( |
|
482 | 494 | cnv_clk => clk_24, |
|
483 | 495 | cnv_rstn => rstn_24, |
|
484 | 496 | cnv => ADC_smpclk_s, |
|
485 | 497 | clk => clk_25, |
|
486 | 498 | rstn => rstn_25, |
|
487 | 499 | ADC_data => ADC_data, |
|
488 | 500 | ADC_nOE => ADC_OEB_bar_CH_s, |
|
489 | 501 | sample => sample, |
|
490 | 502 | sample_val => sample_val); |
|
491 | 503 | |
|
492 | 504 | END GENERATE USE_ADCDRIVER_true; |
|
493 | 505 | |
|
494 | 506 | USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE |
|
495 | 507 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter |
|
496 | 508 | GENERIC MAP ( |
|
497 | 509 | ChanelCount => 9, |
|
498 | 510 | ncycle_cnv_high => 13, |
|
499 | 511 | ncycle_cnv => 25, |
|
500 | 512 | FILTER_ENABLED => 16#FF#) |
|
501 | 513 | PORT MAP ( |
|
502 | 514 | cnv_clk => clk_24, |
|
503 | 515 | cnv_rstn => rstn_24, |
|
504 | 516 | cnv => ADC_smpclk_s, |
|
505 | 517 | clk => clk_25, |
|
506 | 518 | rstn => rstn_25, |
|
507 | 519 | ADC_data => ADC_data, |
|
508 | 520 | ADC_nOE => OPEN, |
|
509 | 521 | sample => OPEN, |
|
510 | 522 | sample_val => sample_val); |
|
511 | 523 | |
|
512 | 524 | ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); |
|
513 | 525 | |
|
514 | 526 | all_sample: FOR I IN 8 DOWNTO 0 GENERATE |
|
515 | 527 | ramp_generator_1: ramp_generator |
|
516 | 528 | GENERIC MAP ( |
|
517 | 529 | DATA_SIZE => 14, |
|
518 | 530 | VALUE_UNSIGNED_INIT => 2**I, |
|
519 | 531 | VALUE_UNSIGNED_INCR => 0, |
|
520 | 532 | VALUE_UNSIGNED_MASK => 16#3FFF#) |
|
521 | 533 | PORT MAP ( |
|
522 | 534 | clk => clk_25, |
|
523 | 535 | rstn => rstn_25, |
|
524 | 536 | new_data => sample_val, |
|
525 | 537 | output_data => sample(I) ); |
|
526 | 538 | END GENERATE all_sample; |
|
527 | 539 | |
|
528 | 540 | |
|
529 | 541 | END GENERATE USE_ADCDRIVER_false; |
|
530 | 542 | |
|
531 | 543 | |
|
532 | 544 | |
|
533 | 545 | |
|
534 | 546 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); |
|
535 | 547 | |
|
536 | 548 | ADC_smpclk <= ADC_smpclk_s; |
|
537 | 549 | HK_smpclk <= ADC_smpclk_s; |
|
538 | 550 | |
|
539 | TAG8 <= nSRAM_BUSY; | |
|
540 | 551 | |
|
541 | 552 | ----------------------------------------------------------------------------- |
|
542 | 553 | -- HK |
|
543 | 554 | ----------------------------------------------------------------------------- |
|
544 | 555 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); |
|
545 | 556 | |
|
546 | 557 | ----------------------------------------------------------------------------- |
|
547 | 558 | -- |
|
548 | 559 | ----------------------------------------------------------------------------- |
|
549 | 560 | inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE |
|
550 | 561 | lpp_bootloader_1: lpp_bootloader |
|
551 | 562 | GENERIC MAP ( |
|
552 | 563 | pindex => 13, |
|
553 | 564 | paddr => 13, |
|
554 | 565 | pmask => 16#fff#, |
|
555 | 566 | hindex => 3, |
|
556 | 567 | haddr => 0, |
|
557 | 568 | hmask => 16#fff#) |
|
558 | 569 | PORT MAP ( |
|
559 | 570 | HCLK => clk_25, |
|
560 | 571 | HRESETn => rstn_25, |
|
561 | 572 | apbi => apbi_ext, |
|
562 | 573 | apbo => apbo_ext(13), |
|
563 | 574 | ahbsi => ahbi_s_ext, |
|
564 | 575 | ahbso => ahbo_s_ext(3)); |
|
565 | 576 | END GENERATE inst_bootloader; |
|
577 | ||
|
578 | ----------------------------------------------------------------------------- | |
|
579 | -- | |
|
580 | ----------------------------------------------------------------------------- | |
|
581 | USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE | |
|
582 | PROCESS (clk_25, rstn_25) | |
|
583 | BEGIN -- PROCESS | |
|
584 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
|
585 | TAG <= (OTHERS => '0'); | |
|
586 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |
|
587 | TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); | |
|
588 | END IF; | |
|
589 | END PROCESS; | |
|
590 | ||
|
591 | ||
|
592 | END GENERATE USE_DEBUG_VECTOR_IF; | |
|
593 | ||
|
594 | USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE | |
|
595 | ahbrxd <= TAG(1); | |
|
596 | TAG(3) <= ahbtxd; | |
|
597 | urxd1 <= TAG(2); | |
|
598 | TAG(4) <= utxd1; | |
|
599 | TAG(8) <= nSRAM_BUSY; | |
|
600 | END GENERATE USE_DEBUG_VECTOR_IF2; | |
|
601 | ||
|
566 | 602 | END beh; |
@@ -1,672 +1,679 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | |
|
23 | 23 | LIBRARY IEEE; |
|
24 | 24 | USE IEEE.STD_LOGIC_1164.ALL; |
|
25 | 25 | USE IEEE.NUMERIC_STD.ALL; |
|
26 | 26 | |
|
27 | 27 | LIBRARY techmap; |
|
28 | 28 | USE techmap.gencomp.ALL; |
|
29 | 29 | |
|
30 | 30 | LIBRARY lpp; |
|
31 | 31 | USE lpp.lpp_sim_pkg.ALL; |
|
32 | 32 | USE lpp.lpp_lfr_sim_pkg.ALL; |
|
33 | 33 | USE lpp.lpp_lfr_apbreg_pkg.ALL; |
|
34 | 34 | USE lpp.lpp_lfr_management_apbreg_pkg.ALL; |
|
35 | 35 | USE lpp.iir_filter.ALL; |
|
36 | 36 | USE lpp.FILTERcfg.ALL; |
|
37 | 37 | USE lpp.lpp_memory.ALL; |
|
38 | 38 | USE lpp.lpp_waveform_pkg.ALL; |
|
39 | 39 | USE lpp.lpp_dma_pkg.ALL; |
|
40 | 40 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
41 | 41 | USE lpp.lpp_lfr_pkg.ALL; |
|
42 | 42 | USE lpp.general_purpose.ALL; |
|
43 | 43 | --LIBRARY lpp; |
|
44 | 44 | USE lpp.lpp_ad_conv.ALL; |
|
45 | 45 | --USE lpp.lpp_lfr_management_apbreg_pkg.ALL; |
|
46 | 46 | --USE lpp.lpp_lfr_apbreg_pkg.ALL; |
|
47 | 47 | |
|
48 | 48 | --USE work.debug.ALL; |
|
49 | 49 | |
|
50 | 50 | LIBRARY gaisler; |
|
51 | 51 | USE gaisler.libdcom.ALL; |
|
52 | 52 | USE gaisler.sim.ALL; |
|
53 | 53 | USE gaisler.memctrl.ALL; |
|
54 | 54 | USE gaisler.leon3.ALL; |
|
55 | 55 | USE gaisler.uart.ALL; |
|
56 | 56 | USE gaisler.misc.ALL; |
|
57 | 57 | USE gaisler.spacewire.ALL; |
|
58 | 58 | |
|
59 | 59 | ENTITY TB IS |
|
60 | 60 | |
|
61 | 61 | END TB; |
|
62 | 62 | |
|
63 | 63 | ARCHITECTURE beh OF TB IS |
|
64 | -- CONSTANT sramfile : STRING := "prom.srec"; | |
|
65 | CONSTANT sramfile : STRING; | |
|
64 | 66 | |
|
65 | 67 | CONSTANT USE_ESA_MEMCTRL : INTEGER := 0; |
|
66 | 68 | |
|
67 | 69 | COMPONENT LFR_EQM |
|
68 | 70 | GENERIC ( |
|
69 | 71 | Mem_use : INTEGER; |
|
70 | 72 | USE_BOOTLOADER : INTEGER; |
|
71 | 73 | USE_ADCDRIVER : INTEGER; |
|
72 | 74 | tech : INTEGER; |
|
73 |
tech_leon : INTEGER |
|
|
75 | tech_leon : INTEGER; | |
|
76 | DEBUG_FORCE_DATA_DMA : INTEGER; | |
|
77 | USE_DEBUG_VECTOR : INTEGER ); | |
|
74 | 78 | PORT ( |
|
75 | 79 | clk50MHz : IN STD_ULOGIC; |
|
76 | 80 | clk49_152MHz : IN STD_ULOGIC; |
|
77 | 81 | reset : IN STD_ULOGIC; |
|
78 | TAG1 : IN STD_ULOGIC; | |
|
79 | TAG3 : OUT STD_ULOGIC; | |
|
80 | TAG2 : IN STD_ULOGIC; | |
|
81 | TAG4 : OUT STD_ULOGIC; | |
|
82 | --TAG1 : IN STD_ULOGIC; | |
|
83 | --TAG3 : OUT STD_ULOGIC; | |
|
84 | --TAG2 : IN STD_ULOGIC; | |
|
85 | --TAG4 : OUT STD_ULOGIC; | |
|
86 | TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); | |
|
82 | 87 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); |
|
83 | 88 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | 89 | nSRAM_MBE : INOUT STD_LOGIC; |
|
85 | 90 | nSRAM_E1 : OUT STD_LOGIC; |
|
86 | 91 | nSRAM_E2 : OUT STD_LOGIC; |
|
87 | 92 | nSRAM_W : OUT STD_LOGIC; |
|
88 | 93 | nSRAM_G : OUT STD_LOGIC; |
|
89 | 94 | nSRAM_BUSY : IN STD_LOGIC; |
|
90 | 95 | spw1_en : OUT STD_LOGIC; |
|
91 | 96 | spw1_din : IN STD_LOGIC; |
|
92 | 97 | spw1_sin : IN STD_LOGIC; |
|
93 | 98 | spw1_dout : OUT STD_LOGIC; |
|
94 | 99 | spw1_sout : OUT STD_LOGIC; |
|
95 | 100 | spw2_en : OUT STD_LOGIC; |
|
96 | 101 | spw2_din : IN STD_LOGIC; |
|
97 | 102 | spw2_sin : IN STD_LOGIC; |
|
98 | 103 | spw2_dout : OUT STD_LOGIC; |
|
99 | 104 | spw2_sout : OUT STD_LOGIC; |
|
100 | 105 | bias_fail_sw : OUT STD_LOGIC; |
|
101 | 106 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
102 | 107 | ADC_smpclk : OUT STD_LOGIC; |
|
103 | 108 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
104 | 109 | DAC_SDO : OUT STD_LOGIC; |
|
105 | 110 | DAC_SCK : OUT STD_LOGIC; |
|
106 | 111 | DAC_SYNC : OUT STD_LOGIC; |
|
107 | 112 | DAC_CAL_EN : OUT STD_LOGIC; |
|
108 | 113 | HK_smpclk : OUT STD_LOGIC; |
|
109 | 114 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
|
110 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
111 | TAG8 : OUT STD_LOGIC); | |
|
115 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)); | |
|
112 | 116 | END COMPONENT; |
|
113 | 117 | |
|
114 | 118 | SIGNAL clk50MHz : STD_ULOGIC := '0'; |
|
115 | 119 | SIGNAL clk49_152MHz : STD_ULOGIC := '0'; |
|
116 | 120 | SIGNAL reset : STD_ULOGIC; |
|
117 |
SIGNAL TAG |
|
|
118 | SIGNAL TAG3 : STD_ULOGIC; | |
|
119 | SIGNAL TAG2 : STD_ULOGIC := '1'; | |
|
120 | SIGNAL TAG4 : STD_ULOGIC; | |
|
121 | SIGNAL TAG : STD_LOGIC_VECTOR(9 DOWNTO 1); | |
|
122 | --SIGNAL TAG3 : STD_ULOGIC; | |
|
123 | --SIGNAL TAG2 : STD_ULOGIC := '1'; | |
|
124 | --SIGNAL TAG4 : STD_ULOGIC; | |
|
121 | 125 | SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0); |
|
122 | 126 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
123 | 127 | SIGNAL nSRAM_MBE : STD_LOGIC; |
|
124 | 128 | SIGNAL nSRAM_E1 : STD_LOGIC; |
|
125 | 129 | SIGNAL nSRAM_E2 : STD_LOGIC; |
|
126 | 130 | SIGNAL nSRAM_W : STD_LOGIC; |
|
127 | 131 | SIGNAL nSRAM_G : STD_LOGIC; |
|
128 | 132 | SIGNAL nSRAM_BUSY : STD_LOGIC; |
|
129 | 133 | SIGNAL spw1_en : STD_LOGIC; |
|
130 | 134 | SIGNAL spw1_din : STD_LOGIC := '1'; |
|
131 | 135 | SIGNAL spw1_sin : STD_LOGIC := '1'; |
|
132 | 136 | SIGNAL spw1_dout : STD_LOGIC; |
|
133 | 137 | SIGNAL spw1_sout : STD_LOGIC; |
|
134 | 138 | SIGNAL spw2_en : STD_LOGIC; |
|
135 | 139 | SIGNAL spw2_din : STD_LOGIC := '1'; |
|
136 | 140 | SIGNAL spw2_sin : STD_LOGIC := '1'; |
|
137 | 141 | SIGNAL spw2_dout : STD_LOGIC; |
|
138 | 142 | SIGNAL spw2_sout : STD_LOGIC; |
|
139 | 143 | SIGNAL bias_fail_sw : STD_LOGIC; |
|
140 | 144 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
141 | 145 | SIGNAL ADC_smpclk : STD_LOGIC; |
|
142 | 146 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
143 | 147 | SIGNAL DAC_SDO : STD_LOGIC; |
|
144 | 148 | SIGNAL DAC_SCK : STD_LOGIC; |
|
145 | 149 | SIGNAL DAC_SYNC : STD_LOGIC; |
|
146 | 150 | SIGNAL DAC_CAL_EN : STD_LOGIC; |
|
147 | 151 | SIGNAL HK_smpclk : STD_LOGIC; |
|
148 | 152 | SIGNAL ADC_OEB_bar_HK : STD_LOGIC; |
|
149 | 153 | SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
150 | SIGNAL TAG8 : STD_LOGIC; | |
|
154 | -- SIGNAL TAG8 : STD_LOGIC; | |
|
151 | 155 | |
|
152 | 156 | CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20; |
|
153 | 157 | CONSTANT SCRUB_PERIOD : INTEGER := 200/20; |
|
154 | 158 | CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20; |
|
155 | 159 | CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20; |
|
156 | 160 | SIGNAL counter_scrub_period : INTEGER; |
|
157 | 161 | |
|
158 | 162 | |
|
159 | 163 | --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800"; |
|
160 | 164 | --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006"; |
|
161 | 165 | --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F"; |
|
162 | 166 | |
|
163 | 167 | CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90"; |
|
164 | 168 | CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; |
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165 | 169 | CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E"; |
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166 | 170 | CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; |
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167 | 171 | CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; |
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168 | 172 | CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000"; |
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169 | 173 | |
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170 | 174 | SIGNAL message_simu : STRING(1 TO 15) := "---------------"; |
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171 | 175 | SIGNAL data_message : STRING(1 TO 15) := "---------------"; |
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172 | 176 | SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); |
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173 | 177 | SIGNAL TXD1 : STD_LOGIC; |
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174 | 178 | SIGNAL RXD1 : STD_LOGIC; |
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175 | 179 | |
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176 | 180 | ----------------------------------------------------------------------------- |
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177 | 181 | CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000"; |
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178 | 182 | CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000"; |
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179 | 183 | CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000"; |
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180 | 184 | CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000"; |
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181 | 185 | CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000"; |
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182 | 186 | CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000"; |
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183 | 187 | CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000"; |
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184 | 188 | CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000"; |
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185 | 189 | CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000"; |
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186 | 190 | CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000"; |
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187 | 191 | CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000"; |
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188 | 192 | CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000"; |
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189 | 193 | CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000"; |
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190 | 194 | CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000"; |
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191 | 195 | |
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192 | 196 | |
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193 | 197 | TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); |
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194 | 198 | SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0); |
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195 | 199 | |
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196 | 200 | TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; |
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197 | 201 | SIGNAL sample_counter : counter_vector( 2 DOWNTO 0); |
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198 | 202 | |
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199 | 203 | SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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200 | 204 | SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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201 | 205 | SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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202 | 206 | SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0); |
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203 | 207 | |
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204 | 208 | SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
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205 | 209 | SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
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206 | 210 | SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
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207 | 211 | |
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208 | 212 | |
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209 | 213 | SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0); |
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210 | 214 | ----------------------------------------------------------------------------- |
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211 | 215 | CONSTANT srambanks : INTEGER := 2; |
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212 | 216 | CONSTANT sramwidth : INTEGER := 32; |
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213 | 217 | CONSTANT sramdepth : INTEGER := 19; |
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214 | CONSTANT sramfile : STRING := "prom.srec"; | |
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215 | 218 | SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0); |
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216 | 219 | ----------------------------------------------------------------------------- |
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217 | 220 | |
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218 | 221 | BEGIN -- beh |
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219 | 222 | |
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220 | 223 | LFR_EQM_1 : LFR_EQM |
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221 | 224 | GENERIC MAP ( |
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222 | 225 | Mem_use => use_RAM, |
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223 | 226 | USE_BOOTLOADER => 0, |
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224 | 227 | USE_ADCDRIVER => 0, |
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225 | 228 | tech => apa3e, |
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226 |
tech_leon => |
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229 | tech_leon => apa3e, | |
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230 | DEBUG_FORCE_DATA_DMA => 1, | |
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231 | USE_DEBUG_VECTOR => 0) | |
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227 | 232 | PORT MAP ( |
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228 | 233 | clk50MHz => clk50MHz, --IN --ok |
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229 | 234 | clk49_152MHz => clk49_152MHz, --in --ok |
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230 | 235 | reset => reset, --IN --ok |
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231 | 236 | |
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232 | TAG1 => TAG1, --in | |
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233 |
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|
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234 |
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235 |
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237 | TAG => TAG, | |
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238 | --TAG1 => TAG1, --in | |
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239 | --TAG3 => TAG3, --out | |
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240 | --TAG2 => TAG2, --IN --ok | |
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241 | --TAG4 => TAG4, --out --ok | |
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236 | 242 | |
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237 | 243 | address => address, --out |
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238 | 244 | data => data, --inout |
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239 | 245 | nSRAM_MBE => nSRAM_MBE, --inout |
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240 | 246 | nSRAM_E1 => nSRAM_E1, --out |
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241 | 247 | nSRAM_E2 => nSRAM_E2, --out |
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242 | 248 | nSRAM_W => nSRAM_W, --out |
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243 | 249 | nSRAM_G => nSRAM_G, --out |
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244 | 250 | nSRAM_BUSY => nSRAM_BUSY, --in |
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245 | 251 | |
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246 | 252 | spw1_en => spw1_en, --out --ok |
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247 | 253 | spw1_din => spw1_din, --in --ok |
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248 | 254 | spw1_sin => spw1_sin, --in --ok |
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249 | 255 | spw1_dout => spw1_dout, --out --ok |
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250 | 256 | spw1_sout => spw1_sout, --out --ok |
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251 | 257 | |
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252 | 258 | spw2_en => spw2_en, --out --ok |
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253 | 259 | spw2_din => spw2_din, --in --ok |
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254 | 260 | spw2_sin => spw2_sin, --in --ok |
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255 | 261 | spw2_dout => spw2_dout, --out --ok |
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256 | 262 | spw2_sout => spw2_sout, --out --ok |
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257 | 263 | |
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258 | 264 | bias_fail_sw => bias_fail_sw, --OUT --ok |
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259 | 265 | |
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260 | 266 | ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok |
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261 | 267 | ADC_smpclk => ADC_smpclk, --out --ok |
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262 | 268 | ADC_data => ADC_data, --IN --ok |
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263 | 269 | |
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264 | 270 | DAC_SDO => DAC_SDO, --out --ok |
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265 | 271 | DAC_SCK => DAC_SCK, --out --ok |
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266 | 272 | DAC_SYNC => DAC_SYNC, --out --ok |
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267 | 273 | DAC_CAL_EN => DAC_CAL_EN, --out --ok |
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268 | 274 | |
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269 | 275 | HK_smpclk => HK_smpclk, --out --ok |
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270 | 276 | ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok |
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271 |
HK_SEL => HK_SEL |
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272 | TAG8 => TAG8); --out --ok | |
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277 | HK_SEL => HK_SEL); --out --ok | |
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273 | 278 | |
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274 | 279 | |
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275 | 280 | ----------------------------------------------------------------------------- |
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276 | 281 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
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277 | 282 | clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz |
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278 | 283 | ----------------------------------------------------------------------------- |
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279 | 284 | |
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280 | 285 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE |
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281 | 286 | TestModule_RHF1401_1 : TestModule_RHF1401 |
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282 | 287 | GENERIC MAP ( |
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283 | 288 | freq => 24*(I+1), |
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284 | 289 | amplitude => 8000/(I+1), |
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285 | 290 | impulsion => 0) |
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286 | 291 | PORT MAP ( |
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287 | 292 | ADC_smpclk => ADC_smpclk, |
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288 | 293 | ADC_OEB_bar => ADC_OEB_bar_CH(I), |
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289 | 294 | ADC_data => ADC_data); |
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290 | 295 | END GENERATE MODULE_RHF1401; |
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291 | 296 | |
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292 | 297 | ----------------------------------------------------------------------------- |
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293 | 298 | PROCESS (clk50MHz, reset) |
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294 | 299 | BEGIN -- PROCESS |
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295 | 300 | IF reset = '0' THEN -- asynchronous reset (active low) |
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296 | 301 | nSRAM_BUSY <= '1'; |
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297 | 302 | counter_scrub_period <= 0; |
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298 | 303 | ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge |
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299 | 304 | IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN |
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300 | 305 | counter_scrub_period <= 0; |
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301 | 306 | ELSE |
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302 | 307 | counter_scrub_period <= counter_scrub_period + 1; |
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303 | 308 | END IF; |
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304 | 309 | |
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305 | 310 | IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN |
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306 | 311 | nSRAM_BUSY <= '1'; |
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307 | 312 | ELSE |
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308 | 313 | nSRAM_BUSY <= '0'; |
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309 | 314 | END IF; |
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310 | 315 | END IF; |
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311 | 316 | END PROCESS; |
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312 | 317 | |
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313 | 318 | ----------------------------------------------------------------------------- |
|
314 | 319 | -- TB |
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315 | 320 | ----------------------------------------------------------------------------- |
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316 | TAG1 <= TXD1; | |
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317 | RXD1 <= TAG3; | |
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321 | TAG(1) <= TXD1; | |
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322 | TAG(2) <= '1'; | |
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323 | RXD1 <= TAG(3); | |
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318 | 324 | |
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319 | 325 | PROCESS |
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320 | 326 | CONSTANT txp : TIME := 320 ns; |
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321 | 327 | VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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322 | 328 | BEGIN -- PROCESS |
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323 | 329 | TXD1 <= '1'; |
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324 | 330 | reset <= '0'; |
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325 | 331 | WAIT FOR 500 ns; |
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326 | 332 | reset <= '1'; |
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327 | 333 | WAIT FOR 100 us; |
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328 | 334 | message_simu <= "0 - UART init "; |
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329 | 335 | UART_INIT(TXD1, txp); |
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330 | 336 | |
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331 | 337 | --------------------------------------------------------------------------- |
|
332 | 338 | -- LAUNCH leon 3 software |
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333 | 339 | --------------------------------------------------------------------------- |
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334 | 340 | message_simu <= "2- GO Leon3...."; |
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335 | 341 | |
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336 | 342 | -- bool dsu3plugin::configureTarget() --------------------------------------------------------------------------------------------------------------------------- |
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337 | 343 | --Force a debug break |
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338 | 344 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS); |
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339 | 345 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20); |
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340 | 346 | --Clear time tag counter |
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341 | 347 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8); |
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342 | 348 | --Clear ASR registers |
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343 | 349 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040); |
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344 | 350 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000"); |
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345 | 351 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000"); |
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346 | 352 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024); |
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347 | 353 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); |
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348 | 354 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); |
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349 | 355 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); |
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350 | 356 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); |
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351 | 357 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000"); |
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352 | 358 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000"); |
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353 | 359 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000"); |
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354 | 360 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000"); |
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355 | 361 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48); |
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356 | 362 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C); |
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357 | 363 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040); |
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358 | 364 | |
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359 | 365 | IF USE_ESA_MEMCTRL = 1 THEN |
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360 | 366 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS); |
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361 | 367 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60"); |
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362 | 368 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000"); |
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363 | 369 | END IF; |
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364 | 370 | |
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365 | 371 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); |
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366 | 372 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); |
|
367 | 373 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); |
|
368 | 374 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); |
|
369 | 375 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24); |
|
370 | 376 | |
|
371 | 377 | --memSet(DSUBASEADDRESS+0x300000,0,1567); |
|
372 | 378 | |
|
373 | 379 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000); |
|
374 | 380 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0"); |
|
375 | 381 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002"); |
|
376 | 382 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000"); |
|
377 | 383 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000"); |
|
378 | 384 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004"); |
|
379 | 385 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000"); |
|
380 | 386 | |
|
381 | 387 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020); |
|
382 | 388 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000"); |
|
383 | 389 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000"); |
|
384 | 390 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000"); |
|
385 | 391 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000"); |
|
386 | 392 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000"); |
|
387 | 393 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0"); |
|
388 | 394 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000"); |
|
389 | 395 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000"); |
|
390 | 396 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000"); |
|
391 | 397 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000"); |
|
392 | 398 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000"); |
|
393 | 399 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000"); |
|
394 | 400 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000"); |
|
395 | 401 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000"); |
|
396 | 402 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000"); |
|
397 | 403 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000"); |
|
398 | 404 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000"); |
|
399 | 405 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000"); |
|
400 | 406 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000"); |
|
401 | 407 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000"); |
|
402 | 408 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000"); |
|
403 | 409 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000"); |
|
404 | 410 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000"); |
|
405 | 411 | |
|
406 | 412 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS); |
|
407 | 413 | |
|
408 | 414 | --//Disable interrupts |
|
409 | 415 | --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0); |
|
410 | 416 | --if(APBIRQCTRLRBASEADD == (unsigned int)-1) |
|
411 | 417 | -- return false; |
|
412 | 418 | --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040); |
|
413 | 419 | --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080); |
|
414 | 420 | --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD); |
|
415 | 421 | |
|
416 | 422 | -- //Set up timer |
|
417 | 423 | --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0); |
|
418 | 424 | --if(APBTIMERBASEADD == (unsigned int)-1) |
|
419 | 425 | -- return false; |
|
420 | 426 | --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014); |
|
421 | 427 | --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04); |
|
422 | 428 | --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018); |
|
423 | 429 | |
|
424 | 430 | |
|
425 | 431 | --------------------------------------------------------------------------- |
|
426 | 432 | --bool dsu3plugin::setCacheEnable(bool enabled) |
|
427 | 433 | --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0); |
|
428 | 434 | --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000; |
|
429 | 435 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024); |
|
430 | 436 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000); |
|
431 | 437 | data_read <= data_read_v; |
|
432 | 438 | --if(enabled){ |
|
433 | 439 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000); |
|
434 | 440 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000); |
|
435 | 441 | --}else{ |
|
436 | 442 | --WriteRegs(uIntlist()<<((!0x0001000F)®),DSUBASEADDRESS+0x700000); |
|
437 | 443 | --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000); |
|
438 | 444 | --} |
|
439 | 445 | |
|
440 | 446 | |
|
441 | 447 | -- void dsu3plugin::run() --------------------------------------------------------------------------------------------------------------------------------------- |
|
442 | 448 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020); |
|
443 | 449 | |
|
444 | 450 | --------------------------------------------------------------------------- |
|
445 | 451 | --message_simu <= "1 - UART test "; |
|
446 | 452 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF"); |
|
447 | 453 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A"); |
|
448 | 454 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B"); |
|
449 | 455 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v); |
|
450 | 456 | --data_read <= data_read_v; |
|
451 | 457 | --data_message <= "GPIO_data_write"; |
|
452 | 458 | |
|
453 | 459 | -- UNSET the LFR reset |
|
454 | 460 | message_simu <= "2 - LFR UNRESET"; |
|
455 | 461 | UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT); |
|
456 | 462 | -- |
|
457 | 463 | message_simu <= "3 - LFR CONFIG "; |
|
458 | 464 | LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR, |
|
459 | 465 | ADDR_BUFFER_MS_F0_0, |
|
460 | 466 | ADDR_BUFFER_MS_F0_1, |
|
461 | 467 | ADDR_BUFFER_MS_F1_0, |
|
462 | 468 | ADDR_BUFFER_MS_F1_1, |
|
463 | 469 | ADDR_BUFFER_MS_F2_0, |
|
464 | 470 | ADDR_BUFFER_MS_F2_1); |
|
465 | 471 | |
|
466 | 472 | |
|
467 | 473 | LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp, |
|
468 | 474 | LFR_MODE_SBM1, |
|
469 | 475 | X"7FFFFFFF", -- START DATE |
|
470 | 476 | |
|
471 | 477 | "00000", --DATA_SHAPING ( 4 DOWNTO 0) |
|
472 | 478 | X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0) |
|
473 | 479 | X"0001280A", --DELTA_F0 (31 DOWNTO 0) |
|
474 | 480 | X"00000007", --DELTA_F0_2 (31 DOWNTO 0) |
|
475 | 481 | X"0001283F", --DELTA_F1 (31 DOWNTO 0) |
|
476 | 482 | X"000127FF", --DELTA_F2 (31 DOWNTO 0) |
|
477 | 483 | |
|
478 | 484 | ADDR_BASE_LFR, |
|
479 | 485 | ADDR_BUFFER_WFP_F0_0, |
|
480 | 486 | ADDR_BUFFER_WFP_F0_1, |
|
481 | 487 | ADDR_BUFFER_WFP_F1_0, |
|
482 | 488 | ADDR_BUFFER_WFP_F1_1, |
|
483 | 489 | ADDR_BUFFER_WFP_F2_0, |
|
484 | 490 | ADDR_BUFFER_WFP_F2_1, |
|
485 | 491 | ADDR_BUFFER_WFP_F3_0, |
|
486 | 492 | ADDR_BUFFER_WFP_F3_1); |
|
487 | 493 | |
|
488 | 494 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); |
|
489 | 495 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); |
|
490 | 496 | |
|
491 | 497 | |
|
492 | 498 | --------------------------------------------------------------------------- |
|
493 | 499 | -- CONFIG LFR 2 |
|
494 | 500 | --------------------------------------------------------------------------- |
|
495 | 501 | --message_simu <= "3 - LFR2 CONFIG"; |
|
496 | 502 | --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2, |
|
497 | 503 | -- X"40000000", |
|
498 | 504 | -- X"40001000", |
|
499 | 505 | -- X"40002000", |
|
500 | 506 | -- X"40003000", |
|
501 | 507 | -- X"40004000", |
|
502 | 508 | -- X"40005000"); |
|
503 | 509 | |
|
504 | 510 | |
|
505 | 511 | --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, |
|
506 | 512 | -- LFR_MODE_SBM1, |
|
507 | 513 | -- X"7FFFFFFF", -- START DATE |
|
508 | 514 | |
|
509 | 515 | -- "00000",--DATA_SHAPING ( 4 DOWNTO 0) |
|
510 | 516 | -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) |
|
511 | 517 | -- X"0001280A",--DELTA_F0 (31 DOWNTO 0) |
|
512 | 518 | -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0) |
|
513 | 519 | -- X"0001283F",--DELTA_F1 (31 DOWNTO 0) |
|
514 | 520 | -- X"000127FF",--DELTA_F2 (31 DOWNTO 0) |
|
515 | 521 | |
|
516 | 522 | -- ADDR_BASE_LFR_2, |
|
517 | 523 | -- X"40006000", |
|
518 | 524 | -- X"40007000", |
|
519 | 525 | -- X"40008000", |
|
520 | 526 | -- X"40009000", |
|
521 | 527 | -- X"4000A000", |
|
522 | 528 | -- X"4000B000", |
|
523 | 529 | -- X"4000C000", |
|
524 | 530 | -- X"4000D000"); |
|
525 | 531 | |
|
526 | 532 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F"); |
|
527 | 533 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); |
|
528 | 534 | |
|
529 | 535 | --------------------------------------------------------------------------- |
|
530 | 536 | --------------------------------------------------------------------------- |
|
537 | UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"58", X"FFFFFFFF"); | |
|
531 | 538 | |
|
532 | 539 | |
|
533 | 540 | message_simu <= "4 - GO GO GO !!"; |
|
534 | 541 | data_message <= "---------------"; |
|
535 | 542 | UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000"); |
|
536 | 543 | -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000"); |
|
537 | 544 | |
|
538 | 545 | |
|
539 | 546 | data_read_v := (OTHERS => '1'); |
|
540 | 547 | READ_STATUS : LOOP |
|
541 | 548 | data_message <= "---------------"; |
|
542 | 549 | WAIT FOR 2 ms; |
|
543 | 550 | data_message <= "READ_STATUS_SM_"; |
|
544 | 551 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); |
|
545 | 552 | --data_message <= "--------------r"; |
|
546 | 553 | --data_read <= data_read_v; |
|
547 | 554 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); |
|
548 | 555 | |
|
549 | 556 | data_message <= "READ_STATUS_WF_"; |
|
550 | 557 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); |
|
551 | 558 | --data_message <= "--------------r"; |
|
552 | 559 | --data_read <= data_read_v; |
|
553 | 560 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); |
|
554 | 561 | END LOOP READ_STATUS; |
|
555 | 562 | |
|
556 | 563 | WAIT; |
|
557 | 564 | END PROCESS; |
|
558 | 565 | |
|
559 | 566 | |
|
560 | 567 | ----------------------------------------------------------------------------- |
|
561 | 568 | PROCESS (nSRAM_W, reset) |
|
562 | 569 | BEGIN -- PROCESS |
|
563 | 570 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
564 | 571 | data_pre_f0 <= X"00020001"; |
|
565 | 572 | data_pre_f1 <= X"00020001"; |
|
566 | 573 | data_pre_f2 <= X"00020001"; |
|
567 | 574 | |
|
568 | 575 | addr_pre_f0 <= (OTHERS => '0'); |
|
569 | 576 | addr_pre_f1 <= (OTHERS => '0'); |
|
570 | 577 | addr_pre_f2 <= (OTHERS => '0'); |
|
571 | 578 | |
|
572 | 579 | error_wfp <= "000"; |
|
573 | 580 | error_wfp_addr <= "000"; |
|
574 | 581 | |
|
575 | 582 | sample_counter <= (0,0,0); |
|
576 | 583 | |
|
577 | 584 | ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge |
|
578 | 585 | error_wfp <= "000"; |
|
579 | 586 | error_wfp_addr <= "000"; |
|
580 | 587 | ------------------------------------------------------------------------- |
|
581 | 588 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR |
|
582 | 589 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN |
|
583 | 590 | |
|
584 | 591 | addr_pre_f0 <= address(13 DOWNTO 0); |
|
585 | 592 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN |
|
586 | 593 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
587 | 594 | error_wfp_addr(0) <= '1'; |
|
588 | 595 | END IF; |
|
589 | 596 | END IF; |
|
590 | 597 | |
|
591 | 598 | data_pre_f0 <= data; |
|
592 | 599 | CASE data_pre_f0 IS |
|
593 | 600 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF; |
|
594 | 601 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF; |
|
595 | 602 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF; |
|
596 | 603 | WHEN OTHERS => error_wfp(0) <= '1'; |
|
597 | 604 | END CASE; |
|
598 | 605 | |
|
599 | 606 | |
|
600 | 607 | END IF; |
|
601 | 608 | ------------------------------------------------------------------------- |
|
602 | 609 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR |
|
603 | 610 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN |
|
604 | 611 | |
|
605 | 612 | addr_pre_f1 <= address(13 DOWNTO 0); |
|
606 | 613 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN |
|
607 | 614 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
608 | 615 | error_wfp_addr(1) <= '1'; |
|
609 | 616 | END IF; |
|
610 | 617 | END IF; |
|
611 | 618 | |
|
612 | 619 | data_pre_f1 <= data; |
|
613 | 620 | CASE data_pre_f1 IS |
|
614 | 621 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF; |
|
615 | 622 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF; |
|
616 | 623 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF; |
|
617 | 624 | WHEN OTHERS => error_wfp(1) <= '1'; |
|
618 | 625 | END CASE; |
|
619 | 626 | |
|
620 | 627 | sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16); |
|
621 | 628 | sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0); |
|
622 | 629 | sample_counter(1) <= (sample_counter(1) + 1) MOD 3; |
|
623 | 630 | |
|
624 | 631 | END IF; |
|
625 | 632 | ------------------------------------------------------------------------- |
|
626 | 633 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR |
|
627 | 634 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN |
|
628 | 635 | |
|
629 | 636 | addr_pre_f2 <= address(13 DOWNTO 0); |
|
630 | 637 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN |
|
631 | 638 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
632 | 639 | error_wfp_addr(2) <= '1'; |
|
633 | 640 | END IF; |
|
634 | 641 | END IF; |
|
635 | 642 | |
|
636 | 643 | data_pre_f2 <= data; |
|
637 | 644 | CASE data_pre_f2 IS |
|
638 | 645 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF; |
|
639 | 646 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF; |
|
640 | 647 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF; |
|
641 | 648 | WHEN OTHERS => error_wfp(2) <= '1'; |
|
642 | 649 | END CASE; |
|
643 | 650 | |
|
644 | 651 | sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16); |
|
645 | 652 | sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0); |
|
646 | 653 | sample_counter(2) <= (sample_counter(2) + 1) MOD 3; |
|
647 | 654 | |
|
648 | 655 | END IF; |
|
649 | 656 | END IF; |
|
650 | 657 | END PROCESS; |
|
651 | 658 | ----------------------------------------------------------------------------- |
|
652 | 659 | ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1; |
|
653 | 660 | |
|
654 | 661 | sbanks : FOR k IN 0 TO srambanks-1 GENERATE |
|
655 | 662 | sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE |
|
656 | 663 | sr0 : sram |
|
657 | 664 | GENERIC MAP ( |
|
658 | 665 | index => i, |
|
659 | 666 | abits => sramdepth, |
|
660 | 667 | fname => sramfile) |
|
661 | 668 | PORT MAP ( |
|
662 | 669 | address, |
|
663 | 670 | data(31-i*8 DOWNTO 24-i*8), |
|
664 | 671 | ramsn(k), |
|
665 | 672 | nSRAM_W, |
|
666 | 673 | nSRAM_G |
|
667 | 674 | ); |
|
668 | 675 | END GENERATE; |
|
669 | 676 | END GENERATE; |
|
670 | 677 | |
|
671 | 678 | END beh; |
|
672 | 679 |
@@ -1,226 +1,226 | |||
|
1 | 1 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd |
|
2 | 2 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd |
|
3 | 3 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd |
|
4 | 4 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd |
|
5 | 5 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management.vhd |
|
6 | 6 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd |
|
7 | 7 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd |
|
8 | 8 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_sim_pkg.vhd |
|
9 | 9 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_lfr_sim_pkg.vhd |
|
10 | 10 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd |
|
11 | 11 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/lpp_bootloader_pkg.vhd |
|
12 | 12 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd |
|
13 | 13 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices_list.vhd |
|
14 | 14 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices.vhd |
|
15 | 15 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/memctrlr.vhd |
|
16 | 16 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd |
|
17 | 17 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-1ws.vhd |
|
18 | 18 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/data_type_pkg.vhd |
|
19 | 19 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_purpose.vhd |
|
20 | 20 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ADDRcntr.vhd |
|
21 | 21 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ALU.vhd |
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22 | 22 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Adder.vhd |
|
23 | 23 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_Divider2.vhd |
|
24 | 24 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_divider.vhd |
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25 | 25 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC.vhd |
|
26 | 26 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd |
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27 | 27 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX.vhd |
|
28 | 28 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX2.vhd |
|
29 | 29 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_REG.vhd |
|
30 | 30 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUX2.vhd |
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31 | 31 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUXN.vhd |
|
32 | 32 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Multiplier.vhd |
|
33 | 33 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/REG.vhd |
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34 | 34 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_FF.vhd |
|
35 | 35 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Shifter.vhd |
|
36 | 36 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/TwoComplementer.vhd |
|
37 | 37 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clock_Divider.vhd |
|
38 | 38 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_to_level.vhd |
|
39 | 39 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_detection.vhd |
|
40 | 40 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd |
|
41 | 41 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd |
|
42 | 42 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/RR_Arbiter_4.vhd |
|
43 | 43 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_counter.vhd |
|
44 | 44 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ramp_generator.vhd |
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45 | 45 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/apb_devices_list.vhd |
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46 | 46 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/lpp_amba.vhd |
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47 | 47 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp_pkg.vhd |
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48 | 48 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp.vhd |
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49 | 49 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/iir_filter.vhd |
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50 | 50 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd |
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51 | 51 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM.vhd |
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52 | 52 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd |
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53 | 53 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd |
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54 | 54 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd |
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55 | 55 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd |
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56 | 56 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd |
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57 | 57 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd |
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58 | 58 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd |
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59 | 59 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_pkg.vhd |
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60 | 60 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic.vhd |
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61 | 61 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_integrator.vhd |
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62 | 62 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_downsampler.vhd |
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63 | 63 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_comb.vhd |
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64 | 64 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr.vhd |
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65 | 65 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control.vhd |
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66 | 66 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd |
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67 | 67 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd |
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68 | 68 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_r2.vhd |
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69 | 69 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd |
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70 | 70 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd |
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71 | 71 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_memory.vhd |
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72 | 72 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO.vhd |
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73 | 73 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd |
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74 | 74 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd |
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75 | 75 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd |
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76 | 76 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd |
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77 | 77 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lppFIFOxN.vhd |
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78 | 78 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fft_components.vhd |
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79 | 79 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd |
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80 | 80 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actar.vhd |
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81 | 81 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actram.vhd |
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82 | 82 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd |
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83 | 83 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftDp.vhd |
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84 | 84 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftSm.vhd |
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85 | 85 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/primitives.vhd |
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86 | 86 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/twiddle.vhd |
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87 | 87 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd |
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88 | 88 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/FFT.vhd |
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89 | 89 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd |
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90 | 90 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lpp_cna.vhd |
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91 | 91 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_READER.vhd |
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92 | 92 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_WRITER.vhd |
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93 | 93 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/SPI_DAC_DRIVER.vhd |
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94 | 94 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/dynamic_freq_div.vhd |
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95 | 95 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lfr_cal_driver.vhd |
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96 | 96 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management.vhd |
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97 | 97 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management_apbreg_pkg.vhd |
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98 | 98 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/apb_lfr_management.vhd |
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99 | 99 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lfr_time_management.vhd |
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100 | 100 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_counter.vhd |
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101 | 101 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/coarse_time_counter.vhd |
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102 | 102 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_max_value_gen.vhd |
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103 | 103 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd |
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104 | 104 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd |
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105 | 105 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd |
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106 | 106 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd |
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107 | 107 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd |
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108 | 108 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd |
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109 | 109 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd |
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110 | 110 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd |
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111 | 111 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/bootrom.vhd |
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112 | 112 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd |
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113 | 113 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd |
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114 | 114 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd |
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115 | 115 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd |
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116 | 116 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_control.vhd |
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117 | 117 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd |
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118 | 118 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd |
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119 | 119 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/DEMUX.vhd |
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120 | 120 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/lpp_demux.vhd |
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121 | 121 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd |
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122 | 122 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd |
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123 | 123 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/lpp_matrix.vhd |
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124 | 124 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ALU_Driver.vhd |
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125 | 125 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd |
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126 | 126 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Dispatch.vhd |
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127 | 127 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/DriveInputs.vhd |
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128 | 128 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/GetResult.vhd |
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129 | 129 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd |
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130 | 130 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Matrix.vhd |
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131 | 131 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd |
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132 | 132 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd |
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133 | 133 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd |
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134 | 134 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd |
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135 | 135 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd |
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136 | 136 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd |
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137 | 137 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd |
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138 | 138 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd |
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139 | 139 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd |
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140 | 140 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem.vhd |
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141 | 141 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd |
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142 | 142 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd |
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143 | 143 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd |
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144 | 144 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd |
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145 | 145 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd |
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146 | 146 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform.vhd |
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147 | 147 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd |
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148 | 148 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd |
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149 | 149 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd |
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150 | 150 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd |
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151 | 151 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd |
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152 | 152 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd |
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153 | 153 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd |
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154 | 154 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd |
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155 | 155 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd |
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156 | 156 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd |
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157 | 157 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd |
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158 | 158 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd |
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159 | 159 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd |
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160 | 160 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd |
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161 | 161 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd |
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162 | 162 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd |
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163 | 163 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd |
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164 | 164 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd |
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165 | 165 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd |
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166 | 166 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd |
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167 | 167 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd |
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168 | 168 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd |
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169 | 169 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd |
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170 | 170 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd |
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171 | 171 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd |
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172 | 172 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd |
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173 | 173 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd |
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174 | 174 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd |
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175 | 175 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd |
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176 | 176 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd |
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177 | 177 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd |
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178 | 178 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd |
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179 | 179 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_sim/lpp_sim_pkg.vhd |
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180 | 180 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd |
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181 | 181 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/leon3_soc.vhd |
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182 | 182 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd |
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183 | 183 | vcom -quiet -93 -work work LFR-EQM.vhd |
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184 | 184 | vcom -quiet -93 -work work TB.vhd |
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185 | 185 | |
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186 | 186 | vsim work.tb |
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187 | 187 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_2/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 00000000000000000000000000000000 0 |
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188 | 188 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 11111111111111111111111111111111 0 |
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189 | 189 | #force -freeze sim:/tb/LFR_EQM_1/inst_bootloader/lpp_bootloader_1/reg.config_wait_on_boot 0 0 |
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190 | 190 | |
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191 | 191 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 |
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192 | 192 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 |
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193 | 193 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 |
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194 | 194 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 |
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195 | 195 | |
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196 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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197 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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198 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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199 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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196 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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197 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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198 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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199 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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200 | 200 | |
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201 | 201 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd |
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202 | 202 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd |
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203 | 203 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd |
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204 | 204 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/inf/x0/rfd |
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205 | 205 | |
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206 | 206 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/inf/x0/rfd |
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207 | 207 | |
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208 | 208 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 |
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209 | 209 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 |
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210 | 210 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 |
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211 | 211 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 |
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212 | 212 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 |
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213 | 213 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 |
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214 | 214 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(0)/u0/u0/VITALBehavior/MEM_512_9 |
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215 | 215 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(1)/u0/u0/VITALBehavior/MEM_512_9 |
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216 | 216 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(2)/u0/u0/VITALBehavior/MEM_512_9 |
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217 | 217 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(3)/u0/u0/VITALBehavior/MEM_512_9 |
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218 | 218 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(4)/u0/u0/VITALBehavior/MEM_512_9 |
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219 | 219 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(5)/u0/u0/VITALBehavior/MEM_512_9 |
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220 | 220 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(6)/u0/u0/VITALBehavior/MEM_512_9 |
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221 | 221 | |
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222 | 222 | log -r *; |
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223 | 223 | do wave.do ; |
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224 | 224 | run -all |
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225 | 225 | |
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226 | 226 |
@@ -1,116 +1,125 | |||
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1 | 1 | onerror {resume} |
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2 | 2 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc |
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3 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(4 downto 3)} HWDATA | |
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4 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(7 downto 6)} DMA_DATA | |
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3 | 5 | quietly WaveActivateNextPane {} 0 |
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4 | add wave -noupdate /tb/data_message | |
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5 | add wave -noupdate /tb/message_simu | |
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6 |
add wave -noupdate -expand -group |
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7 |
add wave -noupdate -expand -group |
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8 |
add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_ |
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9 |
add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_ |
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10 |
add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/ |
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11 | add wave -noupdate -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc | |
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12 | add wave -noupdate -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address | |
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13 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY | |
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14 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE | |
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15 | add wave -noupdate -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data | |
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16 |
add wave -noupdate -group A |
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17 | add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH | |
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18 |
add wave -noupdate -expand -group |
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19 |
add wave -noupdate -expand -group |
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20 |
add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample |
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21 |
add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_ |
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22 |
add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f |
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23 |
add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f |
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24 |
add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f |
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25 |
add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f |
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26 |
add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f |
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27 |
add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f |
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28 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
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29 |
add wave -noupdate -group |
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30 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |
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31 |
add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/d |
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32 |
add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/s |
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33 |
add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/a |
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34 |
add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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35 |
add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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36 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |
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37 |
add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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38 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |
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39 |
add wave -noupdate -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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40 | add wave -noupdate -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
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41 |
add wave -noupdate -group L |
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42 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk | |
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43 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/d |
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44 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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45 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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46 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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47 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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48 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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49 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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50 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/v |
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51 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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52 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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53 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/r |
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54 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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55 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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56 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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57 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctr |
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58 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/d |
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59 |
add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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60 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp | |
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61 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp | |
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62 | add wave -noupdate -expand -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 | |
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63 |
add wave -noupdate -expand -group |
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64 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/data_pre_f2 | |
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65 |
add wave -noupdate -expand -group TEST -radix hexadecimal /tb/a |
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66 |
add wave -noupdate -expand -group TEST -radix hexadecimal /tb/a |
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67 |
add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f |
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68 | add wave -noupdate /tb/error_wfp | |
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69 | add wave -noupdate /tb/error_wfp_addr | |
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70 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a | |
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71 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1 | |
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72 |
add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0( |
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73 |
add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ |
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74 |
add wave -noupdate -group sbanks_ |
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75 |
add wave -noupdate -group sbanks_ |
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76 |
add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ |
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77 |
add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ |
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78 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi | |
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79 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo | |
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80 |
add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/a |
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81 |
add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/a |
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82 |
add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahb |
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83 | add wave -noupdate -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo | |
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84 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
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85 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |
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86 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |
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87 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |
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88 |
add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/d |
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89 |
add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/s |
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90 |
add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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91 |
add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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92 |
add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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93 |
add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/d |
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94 |
add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ |
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95 |
add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/do |
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96 |
add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/r |
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97 | add wave -noupdate -childformat {{/tb/sample(2) -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} {/tb/sample(1) -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} {/tb/sample(0) -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}}} -expand -subitemconfig {/tb/sample(2) {-height 15 -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} /tb/sample(2)(5) {-height 15 -radix decimal} /tb/sample(2)(4) {-height 15 -radix decimal} /tb/sample(2)(3) {-height 15 -radix decimal} /tb/sample(2)(2) {-height 15 -radix decimal} /tb/sample(2)(1) {-height 15 -radix decimal} /tb/sample(2)(0) {-height 15 -radix decimal} /tb/sample(1) {-height 15 -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -expand} /tb/sample(1)(5) {-format Analog-Step -height 74 -min -4.0 -radix decimal} /tb/sample(1)(4) {-format Analog-Step -height 74 -min -8.0 -radix decimal} /tb/sample(1)(3) {-format Analog-Step -height 74 -max 70.0 -radix decimal} /tb/sample(1)(2) {-format Analog-Step -height 74 -max 512.0 -radix decimal} /tb/sample(1)(1) {-format Analog-Step -height 74 -max 256.0 -radix decimal} /tb/sample(1)(0) {-format Analog-Step -height 74 -max 16.0 -radix decimal} /tb/sample(0) {-height 15 -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}} /tb/sample(0)(5) {-height 15 -radix decimal} /tb/sample(0)(4) {-height 15 -radix decimal} /tb/sample(0)(3) {-height 15 -radix decimal} /tb/sample(0)(2) {-height 15 -radix decimal} /tb/sample(0)(1) {-height 15 -radix decimal} /tb/sample(0)(0) {-height 15 -radix decimal}} /tb/sample | |
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98 | add wave -noupdate /tb/sample_counter | |
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6 | add wave -noupdate -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -subitemconfig {/tb/sample(1)(5) {-height 15 -radix decimal} /tb/sample(1)(4) {-height 15 -radix decimal} /tb/sample(1)(3) {-height 15 -radix decimal} /tb/sample(1)(2) {-height 15 -radix decimal} /tb/sample(1)(1) {-height 15 -radix decimal} /tb/sample(1)(0) {-height 15 -radix decimal}} /tb/sample(1) | |
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7 | add wave -noupdate -height 74 -max 326.0 -min 256.0 /tb/sample_counter | |
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8 | add wave -noupdate -expand -group ALL /tb/data_message | |
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9 | add wave -noupdate -expand -group ALL /tb/message_simu | |
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10 | add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1 | |
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11 | add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2 | |
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12 | add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G | |
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13 | add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W | |
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14 | add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/data | |
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15 | add wave -noupdate -expand -group ALL -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc | |
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16 | add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address | |
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17 | add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY | |
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18 | add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE | |
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19 | add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data | |
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20 | add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk | |
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21 | add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH | |
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22 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample | |
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23 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val | |
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24 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val | |
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25 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata | |
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26 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val | |
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27 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata | |
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28 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val | |
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29 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata | |
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30 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val | |
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31 | add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata | |
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32 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
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33 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |
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34 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |
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35 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |
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36 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |
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37 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter | |
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38 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |
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39 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |
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40 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |
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41 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |
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42 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |
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43 | add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
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44 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
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45 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |
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46 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk | |
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47 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |
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48 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid | |
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49 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex | |
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50 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn | |
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51 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |
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52 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |
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53 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid | |
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54 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version | |
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55 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |
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56 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |
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57 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |
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58 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |
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59 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter | |
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60 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |
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61 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window | |
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62 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window | |
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63 | add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state | |
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64 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp | |
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65 | add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp | |
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66 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 | |
|
67 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/data_pre_f1 | |
|
68 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/data_pre_f2 | |
|
69 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f0 | |
|
70 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f1 | |
|
71 | add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f2 | |
|
72 | add wave -noupdate -expand -group ALL /tb/error_wfp | |
|
73 | add wave -noupdate -expand -group ALL /tb/error_wfp_addr | |
|
74 | add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a | |
|
75 | add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1 | |
|
76 | add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe | |
|
77 | add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we | |
|
78 | add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a | |
|
79 | add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1 | |
|
80 | add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe | |
|
81 | add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we | |
|
82 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi | |
|
83 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo | |
|
84 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi | |
|
85 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso | |
|
86 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}} -expand} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmi | |
|
87 | add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo | |
|
88 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
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89 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |
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90 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |
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91 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |
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92 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |
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93 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |
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94 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state | |
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95 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |
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96 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |
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97 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window | |
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98 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window | |
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99 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |
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100 | add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |
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101 | add wave -noupdate -expand /tb/LFR_EQM_1/debug_vector | |
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102 | add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state | |
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103 | add wave -noupdate -radix unsigned /tb/LFR_EQM_1/HWDATA | |
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104 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY | |
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105 | add wave -noupdate -radix unsigned /tb/LFR_EQM_1/DMA_DATA | |
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106 | add wave -noupdate -label DMA_REN /tb/LFR_EQM_1/debug_vector(8) | |
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107 | add wave -noupdate -label HREADY /tb/LFR_EQM_1/debug_vector(5) | |
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99 | 108 | TreeUpdate [SetDefaultTree] |
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100 |
WaveRestoreCursors {{Cursor 1} {1 |
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101 |
quietly wave cursor active |
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109 | WaveRestoreCursors {{Cursor 1} {13070951696 ps} 0} {{Cursor 2} {6213170000 ps} 0} {{Cursor 3} {102733931000 ps} 0} | |
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110 | quietly wave cursor active 2 | |
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102 | 111 | configure wave -namecolwidth 517 |
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103 | 112 | configure wave -valuecolwidth 347 |
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104 | 113 | configure wave -justifyvalue left |
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105 | 114 | configure wave -signalnamewidth 0 |
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106 | 115 | configure wave -snapdistance 10 |
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107 | 116 | configure wave -datasetprefix 0 |
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108 | 117 | configure wave -rowmargin 4 |
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109 | 118 | configure wave -childrowmargin 2 |
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110 | 119 | configure wave -gridoffset 0 |
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111 | 120 | configure wave -gridperiod 1 |
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112 | 121 | configure wave -griddelta 40 |
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113 | 122 | configure wave -timeline 0 |
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114 | 123 | configure wave -timelineunits ns |
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115 | 124 | update |
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116 |
WaveRestoreZoom { |
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125 | WaveRestoreZoom {6212445233 ps} {6219679457 ps} |
@@ -1,226 +1,240 | |||
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1 | 1 | LIBRARY ieee; |
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2 | 2 | USE ieee.std_logic_1164.ALL; |
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3 | 3 | USE ieee.numeric_std.ALL; |
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4 | 4 | |
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5 | 5 | LIBRARY lpp; |
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6 | 6 | USE lpp.apb_devices_list.ALL; |
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7 | 7 | USE lpp.lpp_ad_conv.ALL; |
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8 | 8 | USE lpp.iir_filter.ALL; |
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9 | 9 | USE lpp.FILTERcfg.ALL; |
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10 | 10 | USE lpp.lpp_memory.ALL; |
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11 | 11 | --USE lpp.lpp_waveform_pkg.ALL; |
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12 | 12 | USE lpp.lpp_dma_pkg.ALL; |
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13 | 13 | --USE lpp.lpp_top_lfr_pkg.ALL; |
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14 | 14 | --USE lpp.lpp_lfr_pkg.ALL; |
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15 | 15 | USE lpp.general_purpose.ALL; |
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16 | 16 | |
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17 | 17 | LIBRARY techmap; |
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18 | 18 | USE techmap.gencomp.ALL; |
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19 | 19 | |
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20 | 20 | LIBRARY grlib; |
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21 | 21 | USE grlib.amba.ALL; |
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22 | 22 | USE grlib.stdlib.ALL; |
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23 | 23 | USE grlib.devices.ALL; |
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24 | 24 | USE GRLIB.DMA2AHB_Package.ALL; |
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25 | 25 | |
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26 | 26 | ENTITY DMA_SubSystem IS |
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27 | 27 | |
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28 | 28 | GENERIC ( |
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29 | 29 | hindex : INTEGER := 2; |
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30 | 30 | CUSTOM_DMA : INTEGER := 1); |
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31 | 31 | |
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32 | 32 | PORT ( |
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33 | 33 | clk : IN STD_LOGIC; |
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34 | 34 | rstn : IN STD_LOGIC; |
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35 | 35 | run : IN STD_LOGIC; |
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36 | 36 | -- AHB |
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37 | 37 | ahbi : IN AHB_Mst_In_Type; |
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38 | 38 | ahbo : OUT AHB_Mst_Out_Type; |
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39 | 39 | --------------------------------------------------------------------------- |
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40 | 40 | fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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41 | 41 | fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
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42 | 42 | fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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43 | 43 | --------------------------------------------------------------------------- |
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44 | 44 | buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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45 | 45 | buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
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46 | 46 | buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); |
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47 | 47 | buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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48 | 48 | buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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49 | 49 | --------------------------------------------------------------------------- |
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50 |
grant_error : OUT STD_LOGIC |
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50 | grant_error : OUT STD_LOGIC; | |
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51 | --------------------------------------------------------------------------- | |
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52 | debug_vector : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) | |
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51 | 53 | |
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52 | 54 | ); |
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53 | 55 | |
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54 | 56 | END DMA_SubSystem; |
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55 | 57 | |
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56 | 58 | |
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57 | 59 | ARCHITECTURE beh OF DMA_SubSystem IS |
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58 | 60 | |
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59 | 61 | COMPONENT DMA_SubSystem_GestionBuffer |
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60 | 62 | GENERIC ( |
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61 | 63 | BUFFER_ADDR_SIZE : INTEGER; |
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62 | 64 | BUFFER_LENGTH_SIZE : INTEGER); |
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63 | 65 | PORT ( |
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64 | 66 | clk : IN STD_LOGIC; |
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65 | 67 | rstn : IN STD_LOGIC; |
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66 | 68 | run : IN STD_LOGIC; |
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67 | 69 | buffer_new : IN STD_LOGIC; |
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68 | 70 | buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); |
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69 | 71 | buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); |
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70 | 72 | buffer_full : OUT STD_LOGIC; |
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71 | 73 | buffer_full_err : OUT STD_LOGIC; |
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72 | 74 | burst_send : IN STD_LOGIC; |
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73 | 75 | burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0)); |
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74 | 76 | END COMPONENT; |
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75 | 77 | |
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76 | 78 | COMPONENT DMA_SubSystem_Arbiter |
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77 | 79 | PORT ( |
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78 | 80 | clk : IN STD_LOGIC; |
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79 | 81 | rstn : IN STD_LOGIC; |
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80 | 82 | run : IN STD_LOGIC; |
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81 | 83 | data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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82 | 84 | data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); |
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83 | 85 | END COMPONENT; |
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84 | 86 | |
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85 | 87 | COMPONENT DMA_SubSystem_MUX |
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86 | 88 | PORT ( |
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87 | 89 | clk : IN STD_LOGIC; |
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88 | 90 | rstn : IN STD_LOGIC; |
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89 | 91 | run : IN STD_LOGIC; |
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90 | 92 | fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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91 | 93 | fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
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92 | 94 | fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
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93 | 95 | fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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94 | 96 | fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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95 | 97 | dma_send : OUT STD_LOGIC; |
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96 | 98 | dma_valid_burst : OUT STD_LOGIC; |
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97 | 99 | dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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98 | 100 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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99 | 101 | dma_ren : IN STD_LOGIC; |
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100 | 102 | dma_done : IN STD_LOGIC; |
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101 | 103 | grant_error : OUT STD_LOGIC); |
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102 | 104 | END COMPONENT; |
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103 | 105 | |
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104 | 106 | ----------------------------------------------------------------------------- |
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105 | 107 | SIGNAL dma_send : STD_LOGIC; |
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106 | 108 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
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107 | 109 | SIGNAL dma_done : STD_LOGIC; |
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108 | 110 | SIGNAL dma_ren : STD_LOGIC; |
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109 | 111 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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110 | 112 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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111 | 113 | SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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112 | 114 |
SIGNAL fifo_grant : |
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113 | 115 |
SIGNAL fifo_address : |
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114 | 116 | |
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115 | ||
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117 | SIGNAL ahbo_s : AHB_Mst_Out_Type; | |
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118 | SIGNAL fifo_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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116 | 119 | BEGIN -- beh |
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117 | 120 | |
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121 | ||
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122 | debug_vector <= fifo_ren_s(0) & | |
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123 | dma_data(1 DOWNTO 0) & | |
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124 | ahbi.HREADY & | |
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125 | ahbo_s.HWDATA(1 DOWNTO 0) & | |
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126 | ahbi.HGRANT(hindex) & | |
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127 | ahbo_s.HTRANS(0) & | |
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128 | ahbo_s.HLOCK; | |
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129 | ||
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130 | ahbo <= ahbo_s; | |
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131 | fifo_ren <= fifo_ren_s; | |
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118 | 132 | ----------------------------------------------------------------------------- |
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119 | 133 | -- DMA |
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120 | 134 | ----------------------------------------------------------------------------- |
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121 | 135 | GR_DMA : IF CUSTOM_DMA = 0 GENERATE |
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122 | 136 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
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123 | 137 | GENERIC MAP ( |
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124 | 138 | tech => inferred, |
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125 | 139 | hindex => hindex) |
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126 | 140 | PORT MAP ( |
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127 | 141 | HCLK => clk, |
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128 | 142 | HRESETn => rstn, |
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129 | 143 | run => run, |
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130 | 144 | AHB_Master_In => ahbi, |
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131 | AHB_Master_Out => ahbo, | |
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145 | AHB_Master_Out => ahbo_s, | |
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132 | 146 | |
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133 | 147 | send => dma_send, |
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134 | 148 | valid_burst => dma_valid_burst, |
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135 | 149 | done => dma_done, |
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136 | 150 | ren => dma_ren, |
|
137 | 151 | address => dma_address, |
|
138 | 152 | data => dma_data); |
|
139 | 153 | END GENERATE GR_DMA; |
|
140 | 154 | |
|
141 | 155 | LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE |
|
142 | 156 | lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA |
|
143 | 157 | GENERIC MAP ( |
|
144 | 158 | hindex => hindex, |
|
145 | 159 | vendorid => VENDOR_LPP, |
|
146 | 160 | deviceid => 10, |
|
147 | 161 | version => 0) |
|
148 | 162 | PORT MAP ( |
|
149 | 163 | clk => clk, |
|
150 | 164 | rstn => rstn, |
|
151 | 165 | AHB_Master_In => ahbi, |
|
152 | AHB_Master_Out => ahbo, | |
|
166 | AHB_Master_Out => ahbo_s, | |
|
153 | 167 | |
|
154 | 168 | ren => dma_ren, |
|
155 | 169 | data => dma_data, |
|
156 | 170 | send => dma_send, |
|
157 | 171 | valid_burst => dma_valid_burst, |
|
158 | 172 | done => dma_done, |
|
159 | 173 | address => dma_address); |
|
160 | 174 | END GENERATE LPP_DMA_IP; |
|
161 | 175 | |
|
162 | 176 | |
|
163 | 177 | ----------------------------------------------------------------------------- |
|
164 | 178 | -- RoundRobin Selection Channel For DMA |
|
165 | 179 | ----------------------------------------------------------------------------- |
|
166 | 180 | DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter |
|
167 | 181 | PORT MAP ( |
|
168 | 182 | clk => clk, |
|
169 | 183 | rstn => rstn, |
|
170 | 184 | run => run, |
|
171 | 185 | data_burst_valid => fifo_burst_valid, |
|
172 | 186 | data_burst_valid_grant => fifo_grant); |
|
173 | 187 | |
|
174 | 188 | |
|
175 | 189 | ----------------------------------------------------------------------------- |
|
176 | 190 | -- Mux between the channel from Waveform Picker and Spectral Matrix |
|
177 | 191 | ----------------------------------------------------------------------------- |
|
178 | 192 | DMA_SubSystem_MUX_1: DMA_SubSystem_MUX |
|
179 | 193 | PORT MAP ( |
|
180 | 194 | clk => clk, |
|
181 | 195 | rstn => rstn, |
|
182 | 196 | run => run, |
|
183 | 197 | |
|
184 | 198 | fifo_grant => fifo_grant, |
|
185 | 199 | fifo_data => fifo_data, |
|
186 | 200 | fifo_address => fifo_address, |
|
187 | fifo_ren => fifo_ren, | |
|
201 | fifo_ren => fifo_ren_s, | |
|
188 | 202 | fifo_burst_done => burst_send, |
|
189 | 203 | |
|
190 | 204 | dma_send => dma_send, |
|
191 | 205 | dma_valid_burst => dma_valid_burst, |
|
192 | 206 | dma_address => dma_address, |
|
193 | 207 | dma_data => dma_data, |
|
194 | 208 | dma_ren => dma_ren, |
|
195 | 209 | dma_done => dma_done, |
|
196 | 210 | |
|
197 | 211 | grant_error => grant_error); |
|
198 | 212 | |
|
199 | 213 | |
|
200 | 214 | ----------------------------------------------------------------------------- |
|
201 | 215 | -- GEN ADDR |
|
202 | 216 | ----------------------------------------------------------------------------- |
|
203 | 217 | all_buffer : FOR I IN 4 DOWNTO 0 GENERATE |
|
204 | 218 | DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer |
|
205 | 219 | GENERIC MAP ( |
|
206 | 220 | BUFFER_ADDR_SIZE => 32, |
|
207 | 221 | BUFFER_LENGTH_SIZE => 26) |
|
208 | 222 | PORT MAP ( |
|
209 | 223 | clk => clk, |
|
210 | 224 | rstn => rstn, |
|
211 | 225 | run => run, |
|
212 | 226 | |
|
213 | 227 | buffer_new => buffer_new(I), |
|
214 | 228 | buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32), |
|
215 | 229 | buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26), |
|
216 | 230 | buffer_full => buffer_full(I), |
|
217 | 231 | buffer_full_err => buffer_full_err(I), |
|
218 | 232 | |
|
219 | 233 | burst_send => burst_send(I), |
|
220 | 234 | burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I) |
|
221 | 235 | ); |
|
222 | 236 | END GENERATE all_buffer; |
|
223 | 237 | |
|
224 | 238 | |
|
225 | 239 | |
|
226 | 240 | END beh; |
@@ -1,233 +1,255 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ------------------------------------------------------------------------------- |
|
23 | 23 | -- 1.0 - initial version |
|
24 | 24 | ------------------------------------------------------------------------------- |
|
25 | 25 | LIBRARY ieee; |
|
26 | 26 | USE ieee.std_logic_1164.ALL; |
|
27 | 27 | USE ieee.numeric_std.ALL; |
|
28 | 28 | LIBRARY grlib; |
|
29 | 29 | USE grlib.amba.ALL; |
|
30 | 30 | USE grlib.stdlib.ALL; |
|
31 | 31 | USE grlib.devices.ALL; |
|
32 | 32 | |
|
33 | 33 | LIBRARY lpp; |
|
34 | 34 | USE lpp.lpp_amba.ALL; |
|
35 | 35 | USE lpp.apb_devices_list.ALL; |
|
36 | 36 | USE lpp.lpp_memory.ALL; |
|
37 | 37 | USE lpp.lpp_dma_pkg.ALL; |
|
38 | 38 | USE lpp.general_purpose.ALL; |
|
39 | 39 | --USE lpp.lpp_waveform_pkg.ALL; |
|
40 | 40 | LIBRARY techmap; |
|
41 | 41 | USE techmap.gencomp.ALL; |
|
42 | 42 | |
|
43 | 43 | |
|
44 | 44 | ENTITY lpp_dma_SEND16B_FIFO2DMA IS |
|
45 | 45 | GENERIC ( |
|
46 | 46 | hindex : INTEGER := 2; |
|
47 | 47 | vendorid : IN INTEGER := 0; |
|
48 | 48 | deviceid : IN INTEGER := 0; |
|
49 | 49 | version : IN INTEGER := 0 |
|
50 | 50 | ); |
|
51 | 51 | PORT ( |
|
52 | 52 | clk : IN STD_LOGIC; |
|
53 | 53 | rstn : IN STD_LOGIC; |
|
54 | 54 | |
|
55 | 55 | -- AMBA AHB Master Interface |
|
56 | 56 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
57 | 57 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
58 | 58 | |
|
59 | 59 | -- FIFO Interface |
|
60 | 60 | ren : OUT STD_LOGIC; |
|
61 | 61 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
62 | 62 | |
|
63 | 63 | -- Controls |
|
64 | 64 | send : IN STD_LOGIC; |
|
65 | 65 | valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
66 | 66 | done : OUT STD_LOGIC; |
|
67 | 67 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
68 | 68 | ); |
|
69 | 69 | END; |
|
70 | 70 | |
|
71 | 71 | ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS |
|
72 | 72 | |
|
73 | 73 | CONSTANT HConfig : AHB_Config_Type := ( |
|
74 | 74 | 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0), |
|
75 | 75 | OTHERS => (OTHERS => '0')); |
|
76 | 76 | |
|
77 | TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA); | |
|
77 | TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA); | |
|
78 | 78 | SIGNAL state : AHB_DMA_FSM_STATE; |
|
79 | 79 | |
|
80 | 80 | SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
81 | 81 | SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
82 | 82 | |
|
83 | 83 | SIGNAL data_window : STD_LOGIC; |
|
84 | 84 | SIGNAL ctrl_window : STD_LOGIC; |
|
85 | 85 | |
|
86 | 86 | SIGNAL bus_request : STD_LOGIC; |
|
87 | 87 | SIGNAL bus_lock : STD_LOGIC; |
|
88 | 88 | |
|
89 | 89 | SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | 90 | |
|
91 | SIGNAL HREADY_pre : STD_LOGIC; | |
|
92 | SIGNAL HREADY_falling : STD_LOGIC; | |
|
93 | ||
|
94 | SIGNAL inhib_ren : STD_LOGIC; | |
|
95 | ||
|
91 | 96 | BEGIN |
|
92 | 97 | |
|
93 | 98 | ----------------------------------------------------------------------------- |
|
94 | 99 | AHB_Master_Out.HCONFIG <= HConfig; |
|
95 | 100 | AHB_Master_Out.HSIZE <= "010"; --WORDS 32b |
|
96 | 101 | AHB_Master_Out.HINDEX <= hindex; |
|
97 | 102 | AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS |
|
98 | 103 | AHB_Master_Out.HIRQ <= (OTHERS => '0'); |
|
99 | 104 | AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16 |
|
100 | 105 | AHB_Master_Out.HWRITE <= '1'; |
|
101 | 106 | |
|
102 | 107 | --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE; |
|
103 | 108 | |
|
104 | 109 | --AHB_Master_Out.HBUSREQ <= bus_request; |
|
105 | 110 | --AHB_Master_Out.HLOCK <= data_window; |
|
106 | 111 | |
|
107 | 112 | --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE |
|
108 | 113 | -- '1' WHEN ctrl_window = '1' ELSE |
|
109 | 114 | -- '0'; |
|
110 | 115 | |
|
111 | 116 | --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE |
|
112 | 117 | -- '1' WHEN ctrl_window = '1' ELSE '0'; |
|
113 | 118 | |
|
114 | 119 | ----------------------------------------------------------------------------- |
|
115 | 120 | AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00"; |
|
116 | 121 | AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg); |
|
117 | 122 | |
|
118 | 123 | ----------------------------------------------------------------------------- |
|
119 | 124 | --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY ); |
|
120 | 125 | --ren <= NOT beat; |
|
121 | 126 | ----------------------------------------------------------------------------- |
|
127 | ||
|
128 | HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1'; | |
|
129 | ||
|
130 | ||
|
122 | 131 |
|
|
123 | 132 | BEGIN -- PROCESS |
|
124 | 133 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
125 | 134 | state <= IDLE; |
|
126 | 135 | done <= '0'; |
|
127 | 136 | ren <= '1'; |
|
128 | 137 | address_counter_reg <= (OTHERS => '0'); |
|
129 | 138 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
|
130 | 139 | AHB_Master_Out.HBUSREQ <= '0'; |
|
131 | 140 | AHB_Master_Out.HLOCK <= '0'; |
|
132 | 141 | |
|
133 | 142 | data_reg <= (OTHERS => '0'); |
|
143 | ||
|
144 | HREADY_pre <= '0'; | |
|
145 | inhib_ren <= '0'; | |
|
134 | 146 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
147 | HREADY_pre <= AHB_Master_In.HREADY; | |
|
135 | 148 | |
|
136 | 149 |
|
|
137 | 150 | data_reg <= data; |
|
138 | 151 | END IF; |
|
139 | 152 | |
|
140 | 153 | done <= '0'; |
|
141 | 154 | ren <= '1'; |
|
155 | inhib_ren <= '0'; | |
|
142 | 156 | CASE state IS |
|
143 | 157 | WHEN IDLE => |
|
144 | 158 | AHB_Master_Out.HBUSREQ <= '0'; |
|
145 | 159 | AHB_Master_Out.HLOCK <= '0'; |
|
146 | 160 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
|
147 | 161 | address_counter_reg <= (OTHERS => '0'); |
|
148 | 162 | IF send = '1' THEN |
|
163 | state <= s_INIT_TRANS; | |
|
164 | END IF; | |
|
165 | ||
|
166 | WHEN s_INIT_TRANS => | |
|
149 | 167 |
|
|
150 | 168 |
|
|
151 | 169 |
|
|
152 | 170 |
|
|
153 | END IF; | |
|
154 | 171 | |
|
155 | 172 | WHEN s_ARBITER => |
|
156 | 173 | AHB_Master_Out.HBUSREQ <= '1'; |
|
157 | 174 | AHB_Master_Out.HLOCK <= '1'; |
|
158 | 175 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
|
159 | 176 | address_counter_reg <= (OTHERS => '0'); |
|
160 | 177 | |
|
161 | 178 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN |
|
162 | 179 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
|
163 | 180 | state <= s_CTRL; |
|
164 | 181 | END IF; |
|
165 | 182 | |
|
166 | 183 | WHEN s_CTRL => |
|
184 | inhib_ren <= '1'; | |
|
167 | 185 | AHB_Master_Out.HBUSREQ <= '1'; |
|
168 | 186 | AHB_Master_Out.HLOCK <= '1'; |
|
169 | 187 | AHB_Master_Out.HTRANS <= HTRANS_NONSEQ; |
|
170 | 188 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN |
|
171 | AHB_Master_Out.HTRANS <= HTRANS_SEQ; | |
|
189 | --AHB_Master_Out.HTRANS <= HTRANS_SEQ; | |
|
172 | 190 | state <= s_CTRL_DATA; |
|
173 | ren <= '0'; | |
|
191 | --ren <= '0'; | |
|
174 | 192 | END IF; |
|
175 | 193 | |
|
176 | 194 | WHEN s_CTRL_DATA => |
|
177 | 195 | AHB_Master_Out.HBUSREQ <= '1'; |
|
178 | 196 | AHB_Master_Out.HLOCK <= '1'; |
|
179 | 197 | AHB_Master_Out.HTRANS <= HTRANS_SEQ; |
|
180 | 198 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN |
|
181 | 199 | address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1); |
|
182 | 200 | END IF; |
|
183 | 201 | |
|
184 | 202 | IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN |
|
185 | 203 | AHB_Master_Out.HBUSREQ <= '0'; |
|
186 | 204 | AHB_Master_Out.HLOCK <= '1';--'0'; |
|
187 | 205 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
|
188 | 206 | state <= s_DATA; |
|
189 | 207 | END IF; |
|
190 | 208 | |
|
191 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN | |
|
192 | ren <= '0'; | |
|
193 | END IF; | |
|
209 | ren <= HREADY_falling; | |
|
210 | ||
|
211 | --IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN | |
|
212 | -- ren <= '0'; | |
|
213 | --END IF; | |
|
194 | 214 | |
|
195 | 215 | |
|
196 | 216 | WHEN s_DATA => |
|
217 | ren <= HREADY_falling; | |
|
218 | ||
|
197 | 219 |
|
|
198 | 220 | --AHB_Master_Out.HLOCK <= '0'; |
|
199 | 221 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
|
200 | 222 | IF AHB_Master_In.HREADY = '1' THEN |
|
201 | 223 | AHB_Master_Out.HLOCK <= '0'; |
|
202 | 224 | state <= IDLE; |
|
203 | 225 | done <= '1'; |
|
204 | 226 | END IF; |
|
205 | 227 | |
|
206 | 228 | WHEN OTHERS => NULL; |
|
207 | 229 | END CASE; |
|
208 | 230 | END IF; |
|
209 | 231 | END PROCESS; |
|
210 | 232 | |
|
211 | 233 | ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0'; |
|
212 | 234 | data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0'; |
|
213 | 235 | ----------------------------------------------------------------------------- |
|
214 | 236 | |
|
215 | 237 | |
|
216 | 238 | --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1'; |
|
217 | 239 | |
|
218 | 240 | ----------------------------------------------------------------------------- |
|
219 | 241 | --PROCESS (clk, rstn) |
|
220 | 242 | --BEGIN -- PROCESS |
|
221 | 243 | -- IF rstn = '0' THEN -- asynchronous reset (active low) |
|
222 | 244 | -- address_counter_reg <= (OTHERS => '0'); |
|
223 | 245 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
224 | 246 | -- address_counter_reg <= address_counter; |
|
225 | 247 | -- END IF; |
|
226 | 248 | --END PROCESS; |
|
227 | 249 | |
|
228 | 250 | --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE |
|
229 | 251 | -- address_counter_reg; |
|
230 | 252 | ----------------------------------------------------------------------------- |
|
231 | 253 | |
|
232 | 254 | |
|
233 | 255 | END Behavioral; |
@@ -1,309 +1,311 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | LIBRARY ieee; |
|
24 | 24 | USE ieee.std_logic_1164.ALL; |
|
25 | 25 | LIBRARY grlib; |
|
26 | 26 | USE grlib.amba.ALL; |
|
27 | 27 | USE std.textio.ALL; |
|
28 | 28 | LIBRARY grlib; |
|
29 | 29 | USE grlib.amba.ALL; |
|
30 | 30 | USE grlib.stdlib.ALL; |
|
31 | 31 | USE GRLIB.DMA2AHB_Package.ALL; |
|
32 | 32 | LIBRARY techmap; |
|
33 | 33 | USE techmap.gencomp.ALL; |
|
34 | 34 | --LIBRARY lpp; |
|
35 | 35 | --USE lpp.lpp_amba.ALL; |
|
36 | 36 | --USE lpp.apb_devices_list.ALL; |
|
37 | 37 | --USE lpp.lpp_memory.ALL; |
|
38 | 38 | |
|
39 | 39 | PACKAGE lpp_dma_pkg IS |
|
40 | 40 | |
|
41 | 41 | COMPONENT lpp_dma |
|
42 | 42 | GENERIC ( |
|
43 | 43 | tech : INTEGER; |
|
44 | 44 | hindex : INTEGER; |
|
45 | 45 | pindex : INTEGER; |
|
46 | 46 | paddr : INTEGER; |
|
47 | 47 | pmask : INTEGER; |
|
48 | 48 | pirq : INTEGER); |
|
49 | 49 | PORT ( |
|
50 | 50 | HCLK : IN STD_ULOGIC; |
|
51 | 51 | HRESETn : IN STD_ULOGIC; |
|
52 | 52 | apbi : IN apb_slv_in_type; |
|
53 | 53 | apbo : OUT apb_slv_out_type; |
|
54 | 54 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
55 | 55 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
56 | 56 | -- fifo interface |
|
57 | 57 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
58 | 58 | fifo_empty : IN STD_LOGIC; |
|
59 | 59 | fifo_ren : OUT STD_LOGIC; |
|
60 | 60 | -- header |
|
61 | 61 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
62 | 62 | header_val : IN STD_LOGIC; |
|
63 | 63 | header_ack : OUT STD_LOGIC); |
|
64 | 64 | END COMPONENT; |
|
65 | 65 | |
|
66 | 66 | COMPONENT fifo_test_dma |
|
67 | 67 | GENERIC ( |
|
68 | 68 | tech : INTEGER; |
|
69 | 69 | pindex : INTEGER; |
|
70 | 70 | paddr : INTEGER; |
|
71 | 71 | pmask : INTEGER); |
|
72 | 72 | PORT ( |
|
73 | 73 | HCLK : IN STD_ULOGIC; |
|
74 | 74 | HRESETn : IN STD_ULOGIC; |
|
75 | 75 | apbi : IN apb_slv_in_type; |
|
76 | 76 | apbo : OUT apb_slv_out_type; |
|
77 | 77 | -- fifo interface |
|
78 | 78 | fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | 79 | fifo_empty : OUT STD_LOGIC; |
|
80 | 80 | fifo_ren : IN STD_LOGIC; |
|
81 | 81 | -- header |
|
82 | 82 | header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | 83 | header_val : OUT STD_LOGIC; |
|
84 | 84 | header_ack : IN STD_LOGIC |
|
85 | 85 | ); |
|
86 | 86 | END COMPONENT; |
|
87 | 87 | |
|
88 | 88 | COMPONENT lpp_dma_apbreg |
|
89 | 89 | GENERIC ( |
|
90 | 90 | pindex : INTEGER; |
|
91 | 91 | paddr : INTEGER; |
|
92 | 92 | pmask : INTEGER; |
|
93 | 93 | pirq : INTEGER); |
|
94 | 94 | PORT ( |
|
95 | 95 | HCLK : IN STD_ULOGIC; |
|
96 | 96 | HRESETn : IN STD_ULOGIC; |
|
97 | 97 | apbi : IN apb_slv_in_type; |
|
98 | 98 | apbo : OUT apb_slv_out_type; |
|
99 | 99 | -- IN |
|
100 | 100 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
101 | 101 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
102 | 102 | ready_matrix_f1 : IN STD_LOGIC; |
|
103 | 103 | ready_matrix_f2 : IN STD_LOGIC; |
|
104 | 104 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
105 | 105 | error_bad_component_error : IN STD_LOGIC; |
|
106 | 106 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
107 | 107 | |
|
108 | 108 | -- OUT |
|
109 | 109 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
110 | 110 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
111 | 111 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
112 | 112 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
113 | 113 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
114 | 114 | status_error_bad_component_error : OUT STD_LOGIC; |
|
115 | 115 | |
|
116 | 116 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
117 | 117 | config_active_interruption_onError : OUT STD_LOGIC; |
|
118 | 118 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
119 | 119 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | 120 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
121 | 121 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
122 | 122 | ); |
|
123 | 123 | END COMPONENT; |
|
124 | 124 | |
|
125 | 125 | COMPONENT lpp_dma_send_1word |
|
126 | 126 | PORT ( |
|
127 | 127 | HCLK : IN STD_ULOGIC; |
|
128 | 128 | HRESETn : IN STD_ULOGIC; |
|
129 | 129 | DMAIn : OUT DMA_In_Type; |
|
130 | 130 | DMAOut : IN DMA_OUt_Type; |
|
131 | 131 | send : IN STD_LOGIC; |
|
132 | 132 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | 133 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
134 | 134 | ren : OUT STD_LOGIC; |
|
135 | 135 | send_ok : OUT STD_LOGIC; |
|
136 | 136 | send_ko : OUT STD_LOGIC); |
|
137 | 137 | END COMPONENT; |
|
138 | 138 | |
|
139 | 139 | COMPONENT lpp_dma_send_16word |
|
140 | 140 | PORT ( |
|
141 | 141 | HCLK : IN STD_ULOGIC; |
|
142 | 142 | HRESETn : IN STD_ULOGIC; |
|
143 | 143 | DMAIn : OUT DMA_In_Type; |
|
144 | 144 | DMAOut : IN DMA_OUt_Type; |
|
145 | 145 | send : IN STD_LOGIC; |
|
146 | 146 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
147 | 147 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
148 | 148 | ren : OUT STD_LOGIC; |
|
149 | 149 | send_ok : OUT STD_LOGIC; |
|
150 | 150 | send_ko : OUT STD_LOGIC); |
|
151 | 151 | END COMPONENT; |
|
152 | 152 | |
|
153 | 153 | COMPONENT fifo_latency_correction |
|
154 | 154 | PORT ( |
|
155 | 155 | HCLK : IN STD_ULOGIC; |
|
156 | 156 | HRESETn : IN STD_ULOGIC; |
|
157 | 157 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
158 | 158 | fifo_empty : IN STD_LOGIC; |
|
159 | 159 | fifo_ren : OUT STD_LOGIC; |
|
160 | 160 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
161 | 161 | dma_empty : OUT STD_LOGIC; |
|
162 | 162 | dma_ren : IN STD_LOGIC); |
|
163 | 163 | END COMPONENT; |
|
164 | 164 | |
|
165 | 165 | COMPONENT lpp_dma_ip |
|
166 | 166 | GENERIC ( |
|
167 | 167 | tech : INTEGER; |
|
168 | 168 | hindex : INTEGER); |
|
169 | 169 | PORT ( |
|
170 | 170 | HCLK : IN STD_ULOGIC; |
|
171 | 171 | HRESETn : IN STD_ULOGIC; |
|
172 | 172 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
173 | 173 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
174 | 174 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
175 | 175 | fifo_empty : IN STD_LOGIC; |
|
176 | 176 | fifo_ren : OUT STD_LOGIC; |
|
177 | 177 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
178 | 178 | header_val : IN STD_LOGIC; |
|
179 | 179 | header_ack : OUT STD_LOGIC; |
|
180 | 180 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
181 | 181 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
182 | 182 | ready_matrix_f1 : OUT STD_LOGIC; |
|
183 | 183 | ready_matrix_f2 : OUT STD_LOGIC; |
|
184 | 184 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
185 | 185 | error_bad_component_error : OUT STD_LOGIC; |
|
186 | 186 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
187 | 187 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
188 | 188 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
189 | 189 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
190 | 190 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
191 | 191 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
192 | 192 | status_error_bad_component_error : IN STD_LOGIC; |
|
193 | 193 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
194 | 194 | config_active_interruption_onError : IN STD_LOGIC; |
|
195 | 195 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
196 | 196 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
197 | 197 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
198 | 198 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
199 | 199 | END COMPONENT; |
|
200 | 200 | |
|
201 | 201 | COMPONENT lpp_dma_singleOrBurst |
|
202 | 202 | GENERIC ( |
|
203 | 203 | tech : INTEGER; |
|
204 | 204 | hindex : INTEGER); |
|
205 | 205 | PORT ( |
|
206 | 206 | HCLK : IN STD_ULOGIC; |
|
207 | 207 | HRESETn : IN STD_ULOGIC; |
|
208 | 208 | run : IN STD_LOGIC; |
|
209 | 209 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
210 | 210 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
211 | 211 | send : IN STD_LOGIC; |
|
212 | 212 | valid_burst : IN STD_LOGIC; |
|
213 | 213 | done : OUT STD_LOGIC; |
|
214 | 214 | ren : OUT STD_LOGIC; |
|
215 | 215 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
216 | 216 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
217 | 217 | debug_dmaout_okay : OUT STD_LOGIC); |
|
218 | 218 | END COMPONENT; |
|
219 | 219 | |
|
220 | 220 | |
|
221 | 221 | ----------------------------------------------------------------------------- |
|
222 | 222 | -- DMA_SubSystem |
|
223 | 223 | ----------------------------------------------------------------------------- |
|
224 | 224 | COMPONENT DMA_SubSystem |
|
225 | 225 | GENERIC ( |
|
226 | 226 | hindex : INTEGER; |
|
227 | 227 | CUSTOM_DMA : INTEGER := 1); |
|
228 | 228 | PORT ( |
|
229 | 229 | clk : IN STD_LOGIC; |
|
230 | 230 | rstn : IN STD_LOGIC; |
|
231 | 231 | run : IN STD_LOGIC; |
|
232 | 232 | ahbi : IN AHB_Mst_In_Type; |
|
233 | 233 | ahbo : OUT AHB_Mst_Out_Type; |
|
234 | 234 | fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
235 | 235 | fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
236 | 236 | fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
237 | 237 | buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
238 | 238 | buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
239 | 239 | buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); |
|
240 | 240 | buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
241 | 241 | buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
242 |
grant_error : OUT STD_LOGIC |
|
|
242 | grant_error : OUT STD_LOGIC; | |
|
243 | debug_vector : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) | |
|
244 | ); | |
|
243 | 245 | END COMPONENT; |
|
244 | 246 | |
|
245 | 247 | COMPONENT DMA_SubSystem_GestionBuffer |
|
246 | 248 | GENERIC ( |
|
247 | 249 | BUFFER_ADDR_SIZE : INTEGER; |
|
248 | 250 | BUFFER_LENGTH_SIZE : INTEGER); |
|
249 | 251 | PORT ( |
|
250 | 252 | clk : IN STD_LOGIC; |
|
251 | 253 | rstn : IN STD_LOGIC; |
|
252 | 254 | run : IN STD_LOGIC; |
|
253 | 255 | buffer_new : IN STD_LOGIC; |
|
254 | 256 | buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0); |
|
255 | 257 | buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0); |
|
256 | 258 | buffer_full : OUT STD_LOGIC; |
|
257 | 259 | buffer_full_err : OUT STD_LOGIC; |
|
258 | 260 | burst_send : IN STD_LOGIC; |
|
259 | 261 | burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0)); |
|
260 | 262 | END COMPONENT; |
|
261 | 263 | |
|
262 | 264 | COMPONENT DMA_SubSystem_Arbiter |
|
263 | 265 | PORT ( |
|
264 | 266 | clk : IN STD_LOGIC; |
|
265 | 267 | rstn : IN STD_LOGIC; |
|
266 | 268 | run : IN STD_LOGIC; |
|
267 | 269 | data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
268 | 270 | data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); |
|
269 | 271 | END COMPONENT; |
|
270 | 272 | |
|
271 | 273 | COMPONENT DMA_SubSystem_MUX |
|
272 | 274 | PORT ( |
|
273 | 275 | clk : IN STD_LOGIC; |
|
274 | 276 | rstn : IN STD_LOGIC; |
|
275 | 277 | run : IN STD_LOGIC; |
|
276 | 278 | fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
277 | 279 | fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
278 | 280 | fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
279 | 281 | fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
280 | 282 | fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
281 | 283 | dma_send : OUT STD_LOGIC; |
|
282 | 284 | dma_valid_burst : OUT STD_LOGIC; |
|
283 | 285 | dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
284 | 286 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
285 | 287 | dma_ren : IN STD_LOGIC; |
|
286 | 288 | dma_done : IN STD_LOGIC; |
|
287 | 289 | grant_error : OUT STD_LOGIC); |
|
288 | 290 | END COMPONENT; |
|
289 | 291 | |
|
290 | 292 | COMPONENT lpp_dma_SEND16B_FIFO2DMA |
|
291 | 293 | GENERIC ( |
|
292 | 294 | hindex : INTEGER; |
|
293 | 295 | vendorid : in Integer; |
|
294 | 296 | deviceid : in Integer; |
|
295 | 297 | version : in Integer); |
|
296 | 298 | PORT ( |
|
297 | 299 | clk : IN STD_LOGIC; |
|
298 | 300 | rstn : IN STD_LOGIC; |
|
299 | 301 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
300 | 302 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
301 | 303 | ren : OUT STD_LOGIC; |
|
302 | 304 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
303 | 305 | send : IN STD_LOGIC; |
|
304 | 306 | valid_burst : IN STD_LOGIC; |
|
305 | 307 | done : OUT STD_LOGIC; |
|
306 | 308 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
307 | 309 | END COMPONENT; |
|
308 | 310 | |
|
309 | 311 | END; |
@@ -1,545 +1,579 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | USE ieee.numeric_std.ALL; |
|
4 | 4 | |
|
5 | 5 | LIBRARY lpp; |
|
6 | 6 | USE lpp.lpp_ad_conv.ALL; |
|
7 | 7 | USE lpp.iir_filter.ALL; |
|
8 | 8 | USE lpp.FILTERcfg.ALL; |
|
9 | 9 | USE lpp.lpp_memory.ALL; |
|
10 | 10 | USE lpp.lpp_waveform_pkg.ALL; |
|
11 | 11 | USE lpp.lpp_dma_pkg.ALL; |
|
12 | 12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
13 | 13 | USE lpp.lpp_lfr_pkg.ALL; |
|
14 | 14 | USE lpp.general_purpose.ALL; |
|
15 | 15 | |
|
16 | 16 | LIBRARY techmap; |
|
17 | 17 | USE techmap.gencomp.ALL; |
|
18 | 18 | |
|
19 | 19 | LIBRARY grlib; |
|
20 | 20 | USE grlib.amba.ALL; |
|
21 | 21 | USE grlib.stdlib.ALL; |
|
22 | 22 | USE grlib.devices.ALL; |
|
23 | 23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
24 | 24 | |
|
25 | 25 | ENTITY lpp_lfr IS |
|
26 | 26 | GENERIC ( |
|
27 | 27 | Mem_use : INTEGER := use_RAM; |
|
28 | tech : INTEGER := inferred; | |
|
28 | 29 | nb_data_by_buffer_size : INTEGER := 11; |
|
29 | 30 | nb_snapshot_param_size : INTEGER := 11; |
|
30 | 31 | delta_vector_size : INTEGER := 20; |
|
31 | 32 | delta_vector_size_f0_2 : INTEGER := 7; |
|
32 | 33 | |
|
33 | 34 |
|
|
34 | 35 | paddr : INTEGER := 4; |
|
35 | 36 | pmask : INTEGER := 16#fff#; |
|
36 | 37 | pirq_ms : INTEGER := 0; |
|
37 | 38 | pirq_wfp : INTEGER := 1; |
|
38 | 39 | |
|
39 | 40 | hindex : INTEGER := 2; |
|
40 | 41 | |
|
41 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') | |
|
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0'); | |
|
43 | ||
|
44 | DEBUG_FORCE_DATA_DMA : INTEGER := 0 | |
|
42 | 45 | |
|
43 | 46 |
|
|
44 | 47 | PORT ( |
|
45 | 48 | clk : IN STD_LOGIC; |
|
46 | 49 | rstn : IN STD_LOGIC; |
|
47 | 50 | -- SAMPLE |
|
48 | 51 | sample_B : IN Samples(2 DOWNTO 0); |
|
49 | 52 | sample_E : IN Samples(4 DOWNTO 0); |
|
50 | 53 | sample_val : IN STD_LOGIC; |
|
51 | 54 | -- APB |
|
52 | 55 | apbi : IN apb_slv_in_type; |
|
53 | 56 | apbo : OUT apb_slv_out_type; |
|
54 | 57 | -- AHB |
|
55 | 58 | ahbi : IN AHB_Mst_In_Type; |
|
56 | 59 | ahbo : OUT AHB_Mst_Out_Type; |
|
57 | 60 | -- TIME |
|
58 | 61 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | 62 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | 63 | -- |
|
61 | 64 | data_shaping_BW : OUT STD_LOGIC; |
|
62 | 65 | -- |
|
63 | 66 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
64 | 67 | debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) |
|
65 | 68 | ); |
|
66 | 69 | END lpp_lfr; |
|
67 | 70 | |
|
68 | 71 | ARCHITECTURE beh OF lpp_lfr IS |
|
69 | 72 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
70 | 73 | -- |
|
71 | 74 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
72 | 75 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
73 | 76 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
74 | 77 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
75 | 78 | SIGNAL data_shaping_R2 : STD_LOGIC; |
|
76 | 79 | -- |
|
77 | 80 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
78 | 81 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
79 | 82 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
80 | 83 | -- |
|
81 | 84 | SIGNAL sample_f0_val : STD_LOGIC; |
|
82 | 85 | SIGNAL sample_f1_val : STD_LOGIC; |
|
83 | 86 | SIGNAL sample_f2_val : STD_LOGIC; |
|
84 | 87 | SIGNAL sample_f3_val : STD_LOGIC; |
|
85 | 88 | -- |
|
86 | 89 | SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
87 | 90 | SIGNAL sample_f_data : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0); |
|
88 | 91 | -- |
|
89 | 92 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
90 | 93 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
91 | 94 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
92 | 95 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
93 | 96 | -- |
|
94 | 97 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
95 | 98 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
96 | 99 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
97 | 100 | |
|
98 | 101 | -- SM |
|
99 | 102 | SIGNAL ready_matrix_f0 : STD_LOGIC; |
|
100 | 103 | -- SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
101 | 104 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
102 | 105 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
103 | 106 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; |
|
104 | 107 | -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
105 | 108 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
106 | 109 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
107 | 110 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
108 | 111 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
109 | 112 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
110 | 113 | SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
111 | 114 | SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
112 | 115 | SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
113 | 116 | |
|
114 | 117 | -- WFP |
|
115 | 118 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
116 | 119 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
117 | 120 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
118 | 121 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
119 | 122 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
120 | 123 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
121 | 124 | |
|
122 | 125 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
123 | 126 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
124 | 127 | SIGNAL enable_f0 : STD_LOGIC; |
|
125 | 128 | SIGNAL enable_f1 : STD_LOGIC; |
|
126 | 129 | SIGNAL enable_f2 : STD_LOGIC; |
|
127 | 130 | SIGNAL enable_f3 : STD_LOGIC; |
|
128 | 131 | SIGNAL burst_f0 : STD_LOGIC; |
|
129 | 132 | SIGNAL burst_f1 : STD_LOGIC; |
|
130 | 133 | SIGNAL burst_f2 : STD_LOGIC; |
|
131 | 134 | |
|
132 | 135 | --SIGNAL run : STD_LOGIC; |
|
133 | 136 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
134 | 137 | |
|
135 | 138 | ----------------------------------------------------------------------------- |
|
136 | 139 | -- |
|
137 | 140 | ----------------------------------------------------------------------------- |
|
138 | 141 | -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
139 | 142 | -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
|
140 | 143 | -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
|
141 | 144 | --f1 |
|
142 | 145 | -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
143 | 146 | -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
|
144 | 147 | -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
|
145 | 148 | --f2 |
|
146 | 149 | -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
147 | 150 | -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
|
148 | 151 | -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
|
149 | 152 | --f3 |
|
150 | 153 | -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
151 | 154 | -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
|
152 | 155 | -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
|
153 | 156 | |
|
154 | 157 | SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
155 | 158 | SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
|
156 | 159 | SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
157 | 160 | SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
158 | 161 | SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
159 | 162 | SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
160 | 163 | ----------------------------------------------------------------------------- |
|
161 | 164 | -- DMA RR |
|
162 | 165 | ----------------------------------------------------------------------------- |
|
163 | 166 | -- SIGNAL dma_sel_valid : STD_LOGIC; |
|
164 | 167 | -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
165 | 168 | -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
166 | 169 | -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
167 | 170 | -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
168 | 171 | |
|
169 | 172 | -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
170 | 173 | -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
171 | 174 | |
|
172 | 175 | ----------------------------------------------------------------------------- |
|
173 | 176 | -- DMA_REG |
|
174 | 177 | ----------------------------------------------------------------------------- |
|
175 | 178 | -- SIGNAL ongoing_reg : STD_LOGIC; |
|
176 | 179 | -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
177 | 180 | -- SIGNAL dma_send_reg : STD_LOGIC; |
|
178 | 181 | -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
179 | 182 | -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
180 | 183 | -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
181 | 184 | |
|
182 | 185 | |
|
183 | 186 | ----------------------------------------------------------------------------- |
|
184 | 187 | -- DMA |
|
185 | 188 | ----------------------------------------------------------------------------- |
|
186 | 189 | -- SIGNAL dma_send : STD_LOGIC; |
|
187 | 190 | -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
188 | 191 | -- SIGNAL dma_done : STD_LOGIC; |
|
189 | 192 | -- SIGNAL dma_ren : STD_LOGIC; |
|
190 | 193 | -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
191 | 194 | -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
192 | 195 | -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
193 | 196 | |
|
194 | 197 | ----------------------------------------------------------------------------- |
|
195 | 198 | -- MS |
|
196 | 199 | ----------------------------------------------------------------------------- |
|
197 | 200 | |
|
198 | 201 | -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
199 | 202 | -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
200 | 203 | -- SIGNAL data_ms_valid : STD_LOGIC; |
|
201 | 204 | -- SIGNAL data_ms_valid_burst : STD_LOGIC; |
|
202 | 205 | -- SIGNAL data_ms_ren : STD_LOGIC; |
|
203 | 206 | -- SIGNAL data_ms_done : STD_LOGIC; |
|
204 | 207 | -- SIGNAL dma_ms_ongoing : STD_LOGIC; |
|
205 | 208 | |
|
206 | 209 | -- SIGNAL run_ms : STD_LOGIC; |
|
207 | 210 | -- SIGNAL ms_softandhard_rstn : STD_LOGIC; |
|
208 | 211 | |
|
209 | 212 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
210 | 213 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
211 | 214 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
212 | 215 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
213 | 216 | |
|
214 | 217 | |
|
215 | 218 | SIGNAL error_buffer_full : STD_LOGIC; |
|
216 | 219 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
217 | 220 | |
|
218 | 221 | -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
219 | 222 | -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
220 | 223 | |
|
221 | 224 | ----------------------------------------------------------------------------- |
|
222 | 225 | SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
223 | 226 | SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
227 | SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015 | |
|
228 | SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015 | |
|
229 | SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015 | |
|
224 | 230 | SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
225 | 231 | SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
226 | 232 | SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
227 | 233 | SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); |
|
228 | 234 | SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
229 | 235 | SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
230 | 236 | SIGNAL dma_grant_error : STD_LOGIC; |
|
231 | 237 | |
|
232 | 238 | SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
233 | 239 | ----------------------------------------------------------------------------- |
|
234 | 240 | SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
235 | 241 | SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
236 | 242 | SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
237 | 243 | SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
238 | 244 | SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
239 | 245 | |
|
240 | 246 | BEGIN |
|
241 | 247 | |
|
242 |
|
|
|
248 | --apb_reg_debug_vector; | |
|
243 | 249 | ----------------------------------------------------------------------------- |
|
244 | 250 | |
|
245 | 251 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
246 | 252 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
247 | 253 | sample_time <= coarse_time & fine_time; |
|
248 | 254 | |
|
249 | 255 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
|
250 | 256 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
251 | 257 | --END GENERATE all_channel; |
|
252 | 258 | |
|
253 | 259 | ----------------------------------------------------------------------------- |
|
254 | 260 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
255 | 261 | GENERIC MAP ( |
|
256 | 262 | Mem_use => Mem_use) |
|
257 | 263 | PORT MAP ( |
|
258 | 264 | sample => sample_s, |
|
259 | 265 | sample_val => sample_val, |
|
260 | 266 | sample_time => sample_time, |
|
261 | 267 | clk => clk, |
|
262 | 268 | rstn => rstn, |
|
263 | 269 | data_shaping_SP0 => data_shaping_SP0, |
|
264 | 270 | data_shaping_SP1 => data_shaping_SP1, |
|
265 | 271 | data_shaping_R0 => data_shaping_R0, |
|
266 | 272 | data_shaping_R1 => data_shaping_R1, |
|
267 | 273 | data_shaping_R2 => data_shaping_R2, |
|
268 | 274 | sample_f0_val => sample_f0_val, |
|
269 | 275 | sample_f1_val => sample_f1_val, |
|
270 | 276 | sample_f2_val => sample_f2_val, |
|
271 | 277 | sample_f3_val => sample_f3_val, |
|
272 | 278 | sample_f0_wdata => sample_f0_data, |
|
273 | 279 | sample_f1_wdata => sample_f1_data, |
|
274 | 280 | sample_f2_wdata => sample_f2_data, |
|
275 | 281 | sample_f3_wdata => sample_f3_data, |
|
276 | 282 | sample_f0_time => sample_f0_time, |
|
277 | 283 | sample_f1_time => sample_f1_time, |
|
278 | 284 | sample_f2_time => sample_f2_time, |
|
279 | 285 | sample_f3_time => sample_f3_time |
|
280 | 286 | ); |
|
281 | 287 | |
|
282 | 288 | ----------------------------------------------------------------------------- |
|
283 | 289 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
284 | 290 | GENERIC MAP ( |
|
285 | 291 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
286 | 292 | -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO |
|
287 | 293 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
288 | 294 | delta_vector_size => delta_vector_size, |
|
289 | 295 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
290 | 296 | pindex => pindex, |
|
291 | 297 | paddr => paddr, |
|
292 | 298 | pmask => pmask, |
|
293 | 299 | pirq_ms => pirq_ms, |
|
294 | 300 | pirq_wfp => pirq_wfp, |
|
295 | 301 | top_lfr_version => top_lfr_version) |
|
296 | 302 | PORT MAP ( |
|
297 | 303 | HCLK => clk, |
|
298 | 304 | HRESETn => rstn, |
|
299 | 305 | apbi => apbi, |
|
300 | 306 | apbo => apbo, |
|
301 | 307 | |
|
302 | 308 | run_ms => OPEN,--run_ms, |
|
303 | 309 | |
|
304 | 310 | ready_matrix_f0 => ready_matrix_f0, |
|
305 | 311 | ready_matrix_f1 => ready_matrix_f1, |
|
306 | 312 | ready_matrix_f2 => ready_matrix_f2, |
|
307 | 313 | error_buffer_full => error_buffer_full, -- TODO |
|
308 | 314 | error_input_fifo_write => error_input_fifo_write, -- TODO |
|
309 | 315 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
310 | 316 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
311 | 317 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
312 | 318 | |
|
313 | 319 | matrix_time_f0 => matrix_time_f0, |
|
314 | 320 | matrix_time_f1 => matrix_time_f1, |
|
315 | 321 | matrix_time_f2 => matrix_time_f2, |
|
316 | 322 | |
|
317 | 323 | addr_matrix_f0 => addr_matrix_f0, |
|
318 | 324 | addr_matrix_f1 => addr_matrix_f1, |
|
319 | 325 | addr_matrix_f2 => addr_matrix_f2, |
|
320 | 326 | |
|
321 | 327 | length_matrix_f0 => length_matrix_f0, |
|
322 | 328 | length_matrix_f1 => length_matrix_f1, |
|
323 | 329 | length_matrix_f2 => length_matrix_f2, |
|
324 | 330 | ------------------------------------------------------------------------- |
|
325 | 331 | --status_full => status_full, -- TODo |
|
326 | 332 | --status_full_ack => status_full_ack, -- TODo |
|
327 | 333 | --status_full_err => status_full_err, -- TODo |
|
328 | 334 | status_new_err => status_new_err, |
|
329 | 335 | data_shaping_BW => data_shaping_BW, |
|
330 | 336 | data_shaping_SP0 => data_shaping_SP0, |
|
331 | 337 | data_shaping_SP1 => data_shaping_SP1, |
|
332 | 338 | data_shaping_R0 => data_shaping_R0, |
|
333 | 339 | data_shaping_R1 => data_shaping_R1, |
|
334 | 340 | data_shaping_R2 => data_shaping_R2, |
|
335 | 341 | delta_snapshot => delta_snapshot, |
|
336 | 342 | delta_f0 => delta_f0, |
|
337 | 343 | delta_f0_2 => delta_f0_2, |
|
338 | 344 | delta_f1 => delta_f1, |
|
339 | 345 | delta_f2 => delta_f2, |
|
340 | 346 | nb_data_by_buffer => nb_data_by_buffer, |
|
341 | 347 | -- nb_word_by_buffer => nb_word_by_buffer, -- TODO |
|
342 | 348 | nb_snapshot_param => nb_snapshot_param, |
|
343 | 349 | enable_f0 => enable_f0, |
|
344 | 350 | enable_f1 => enable_f1, |
|
345 | 351 | enable_f2 => enable_f2, |
|
346 | 352 | enable_f3 => enable_f3, |
|
347 | 353 | burst_f0 => burst_f0, |
|
348 | 354 | burst_f1 => burst_f1, |
|
349 | 355 | burst_f2 => burst_f2, |
|
350 | 356 | run => OPEN, --run, |
|
351 | 357 | start_date => start_date, |
|
352 | 358 | -- debug_signal => debug_signal, |
|
353 | 359 | wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO |
|
354 | 360 | wfp_addr_buffer => wfp_addr_buffer,-- TODO |
|
355 | 361 | wfp_length_buffer => wfp_length_buffer,-- TODO |
|
356 | 362 | |
|
357 | 363 | wfp_ready_buffer => wfp_ready_buffer,-- TODO |
|
358 | 364 | wfp_buffer_time => wfp_buffer_time,-- TODO |
|
359 | 365 | wfp_error_buffer_full => wfp_error_buffer_full, -- TODO |
|
360 | 366 | ------------------------------------------------------------------------- |
|
361 | 367 | sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16), |
|
362 | 368 | sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16), |
|
363 | 369 | sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16), |
|
364 | 370 | sample_f3_valid => sample_f3_val, |
|
365 | 371 | debug_vector => apb_reg_debug_vector |
|
366 | 372 | ); |
|
367 | 373 | |
|
368 | 374 | ----------------------------------------------------------------------------- |
|
369 | 375 | ----------------------------------------------------------------------------- |
|
370 | 376 | lpp_waveform_1 : lpp_waveform |
|
371 | 377 | GENERIC MAP ( |
|
372 |
tech => |
|
|
378 | tech => tech, | |
|
373 | 379 | data_size => 6*16, |
|
374 | 380 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
375 | 381 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
376 | 382 | delta_vector_size => delta_vector_size, |
|
377 | 383 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
378 | 384 | ) |
|
379 | 385 | PORT MAP ( |
|
380 | 386 | clk => clk, |
|
381 | 387 | rstn => rstn, |
|
382 | 388 | |
|
383 | 389 | reg_run => '1',--run, |
|
384 | 390 | reg_start_date => start_date, |
|
385 | 391 | reg_delta_snapshot => delta_snapshot, |
|
386 | 392 | reg_delta_f0 => delta_f0, |
|
387 | 393 | reg_delta_f0_2 => delta_f0_2, |
|
388 | 394 | reg_delta_f1 => delta_f1, |
|
389 | 395 | reg_delta_f2 => delta_f2, |
|
390 | 396 | |
|
391 | 397 | enable_f0 => enable_f0, |
|
392 | 398 | enable_f1 => enable_f1, |
|
393 | 399 | enable_f2 => enable_f2, |
|
394 | 400 | enable_f3 => enable_f3, |
|
395 | 401 | burst_f0 => burst_f0, |
|
396 | 402 | burst_f1 => burst_f1, |
|
397 | 403 | burst_f2 => burst_f2, |
|
398 | 404 | |
|
399 | 405 | nb_data_by_buffer => nb_data_by_buffer, |
|
400 | 406 | nb_snapshot_param => nb_snapshot_param, |
|
401 | 407 | status_new_err => status_new_err, |
|
402 | 408 | |
|
403 | 409 | status_buffer_ready => wfp_status_buffer_ready, |
|
404 | 410 | addr_buffer => wfp_addr_buffer, |
|
405 | 411 | length_buffer => wfp_length_buffer, |
|
406 | 412 | ready_buffer => wfp_ready_buffer, |
|
407 | 413 | buffer_time => wfp_buffer_time, |
|
408 | 414 | error_buffer_full => wfp_error_buffer_full, |
|
409 | 415 | |
|
410 | 416 | coarse_time => coarse_time, |
|
411 | 417 | -- fine_time => fine_time, |
|
412 | 418 | |
|
413 | 419 | --f0 |
|
414 | 420 | data_f0_in_valid => sample_f0_val, |
|
415 | 421 | data_f0_in => sample_f0_data, |
|
416 | 422 | data_f0_time => sample_f0_time, |
|
417 | 423 | --f1 |
|
418 | 424 | data_f1_in_valid => sample_f1_val, |
|
419 | 425 | data_f1_in => sample_f1_data, |
|
420 | 426 | data_f1_time => sample_f1_time, |
|
421 | 427 | --f2 |
|
422 | 428 | data_f2_in_valid => sample_f2_val, |
|
423 | 429 | data_f2_in => sample_f2_data, |
|
424 | 430 | data_f2_time => sample_f2_time, |
|
425 | 431 | --f3 |
|
426 | 432 | data_f3_in_valid => sample_f3_val, |
|
427 | 433 | data_f3_in => sample_f3_data, |
|
428 | 434 | data_f3_time => sample_f3_time, |
|
429 | 435 | -- OUTPUT -- DMA interface |
|
430 | 436 | |
|
431 | 437 | dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0), |
|
432 | 438 | dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0), |
|
433 | 439 | dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0), |
|
434 | 440 | dma_buffer_new => dma_buffer_new(3 DOWNTO 0), |
|
435 | 441 | dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0), |
|
436 | 442 | dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0), |
|
437 | 443 | dma_buffer_full => dma_buffer_full(3 DOWNTO 0), |
|
438 | 444 | dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0) |
|
439 | 445 | |
|
440 | 446 | ); |
|
441 | 447 | |
|
442 | 448 | ----------------------------------------------------------------------------- |
|
443 | 449 | -- Matrix Spectral |
|
444 | 450 | ----------------------------------------------------------------------------- |
|
445 | 451 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
446 | 452 | NOT(sample_f0_val) & NOT(sample_f0_val); |
|
447 | 453 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
448 | 454 | NOT(sample_f1_val) & NOT(sample_f1_val); |
|
449 | 455 | sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & |
|
450 | 456 | NOT(sample_f2_val) & NOT(sample_f2_val); |
|
451 | 457 | |
|
458 | ||
|
452 | 459 |
|
|
453 | 460 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
454 | 461 | sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16)); |
|
455 | 462 | |
|
456 | 463 | ------------------------------------------------------------------------------- |
|
457 | 464 | |
|
458 | 465 | --ms_softandhard_rstn <= rstn AND run_ms AND run; |
|
459 | 466 | |
|
460 | 467 | ----------------------------------------------------------------------------- |
|
461 | 468 | lpp_lfr_ms_1 : lpp_lfr_ms |
|
462 | 469 | GENERIC MAP ( |
|
463 | 470 | Mem_use => Mem_use) |
|
464 | 471 | PORT MAP ( |
|
465 | 472 | clk => clk, |
|
466 | 473 | --rstn => ms_softandhard_rstn, --rstn, |
|
467 | 474 | rstn => rstn, |
|
468 | 475 | |
|
469 | 476 | run => '1',--run_ms, |
|
470 | 477 | |
|
471 | 478 | start_date => start_date, |
|
472 | 479 | |
|
473 | 480 | coarse_time => coarse_time, |
|
474 | 481 | |
|
475 | 482 | sample_f0_wen => sample_f0_wen, |
|
476 | 483 | sample_f0_wdata => sample_f0_wdata, |
|
477 | 484 | sample_f0_time => sample_f0_time, |
|
478 | 485 | sample_f1_wen => sample_f1_wen, |
|
479 | 486 | sample_f1_wdata => sample_f1_wdata, |
|
480 | 487 | sample_f1_time => sample_f1_time, |
|
481 | 488 | sample_f2_wen => sample_f2_wen, |
|
482 | 489 | sample_f2_wdata => sample_f2_wdata, |
|
483 | 490 | sample_f2_time => sample_f2_time, |
|
484 | 491 | |
|
485 | 492 | --DMA |
|
486 | 493 | dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT |
|
487 | 494 | dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT |
|
488 | 495 | dma_fifo_ren => dma_fifo_ren(4), -- IN |
|
489 | 496 | dma_buffer_new => dma_buffer_new(4), -- OUT |
|
490 | 497 | dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT |
|
491 | 498 | dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT |
|
492 | 499 | dma_buffer_full => dma_buffer_full(4), -- IN |
|
493 | 500 | dma_buffer_full_err => dma_buffer_full_err(4), -- IN |
|
494 | 501 | |
|
495 | 502 | |
|
496 | 503 | |
|
497 | 504 | --REG |
|
498 | 505 | ready_matrix_f0 => ready_matrix_f0, |
|
499 | 506 | ready_matrix_f1 => ready_matrix_f1, |
|
500 | 507 | ready_matrix_f2 => ready_matrix_f2, |
|
501 | 508 | error_buffer_full => error_buffer_full, |
|
502 | 509 | error_input_fifo_write => error_input_fifo_write, |
|
503 | 510 | |
|
504 | 511 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
505 | 512 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
506 | 513 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
507 | 514 | addr_matrix_f0 => addr_matrix_f0, |
|
508 | 515 | addr_matrix_f1 => addr_matrix_f1, |
|
509 | 516 | addr_matrix_f2 => addr_matrix_f2, |
|
510 | 517 | |
|
511 | 518 | length_matrix_f0 => length_matrix_f0, |
|
512 | 519 | length_matrix_f1 => length_matrix_f1, |
|
513 | 520 | length_matrix_f2 => length_matrix_f2, |
|
514 | 521 | |
|
515 | 522 | matrix_time_f0 => matrix_time_f0, |
|
516 | 523 | matrix_time_f1 => matrix_time_f1, |
|
517 | 524 | matrix_time_f2 => matrix_time_f2, |
|
518 | 525 | |
|
519 | 526 | debug_vector => debug_vector_ms); |
|
520 | 527 | |
|
521 | 528 | ----------------------------------------------------------------------------- |
|
522 | --run_dma <= run_ms OR run; | |
|
529 | PROCESS (clk, rstn) | |
|
530 | BEGIN | |
|
531 | IF rstn = '0' THEN | |
|
532 | dma_fifo_data_forced_gen <= X"00040003"; | |
|
533 | ELSIF clk'event AND clk = '1' THEN | |
|
534 | IF dma_fifo_ren(0) = '0' THEN | |
|
535 | CASE dma_fifo_data_forced_gen IS | |
|
536 | WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002"; | |
|
537 | WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001"; | |
|
538 | WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003"; | |
|
539 | WHEN OTHERS => NULL; | |
|
540 | END CASE; | |
|
541 | END IF; | |
|
542 | END IF; | |
|
543 | END PROCESS; | |
|
544 | ||
|
545 | dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen; | |
|
546 | dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100"; | |
|
547 | dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000"; | |
|
548 | dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000"; | |
|
549 | dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00"; | |
|
550 | ||
|
551 | dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced; | |
|
523 | 552 | |
|
524 | 553 | DMA_SubSystem_1 : DMA_SubSystem |
|
525 | 554 | GENERIC MAP ( |
|
526 |
hindex => hindex |
|
|
555 | hindex => hindex, | |
|
556 | CUSTOM_DMA => 1) | |
|
527 | 557 | PORT MAP ( |
|
528 | 558 | clk => clk, |
|
529 | 559 | rstn => rstn, |
|
530 | 560 | run => '1',--run_dma, |
|
531 | 561 | ahbi => ahbi, |
|
532 | 562 | ahbo => ahbo, |
|
533 | 563 | |
|
534 | 564 | fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid, |
|
535 | fifo_data => dma_fifo_data, --fifo_data, | |
|
565 | fifo_data => dma_fifo_data_debug, --fifo_data, | |
|
536 | 566 | fifo_ren => dma_fifo_ren, --fifo_ren, |
|
537 | 567 | |
|
538 | 568 | buffer_new => dma_buffer_new, --buffer_new, |
|
539 | 569 | buffer_addr => dma_buffer_addr, --buffer_addr, |
|
540 | 570 | buffer_length => dma_buffer_length, --buffer_length, |
|
541 | 571 | buffer_full => dma_buffer_full, --buffer_full, |
|
542 | 572 | buffer_full_err => dma_buffer_full_err, --buffer_full_err, |
|
543 |
grant_error => dma_grant_error |
|
|
573 | grant_error => dma_grant_error, | |
|
574 | debug_vector => debug_vector(8 DOWNTO 0) | |
|
575 | ); --grant_error); | |
|
576 | ||
|
577 | ||
|
544 | 578 | |
|
545 | 579 | END beh; |
@@ -1,403 +1,405 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | |
|
4 | 4 | LIBRARY grlib; |
|
5 | 5 | USE grlib.amba.ALL; |
|
6 | 6 | |
|
7 | 7 | LIBRARY lpp; |
|
8 | 8 | USE lpp.lpp_ad_conv.ALL; |
|
9 | 9 | USE lpp.iir_filter.ALL; |
|
10 | 10 | USE lpp.FILTERcfg.ALL; |
|
11 | 11 | USE lpp.lpp_memory.ALL; |
|
12 | 12 | LIBRARY techmap; |
|
13 | 13 | USE techmap.gencomp.ALL; |
|
14 | 14 | |
|
15 | 15 | PACKAGE lpp_lfr_pkg IS |
|
16 | 16 | ----------------------------------------------------------------------------- |
|
17 | 17 | -- TEMP |
|
18 | 18 | ----------------------------------------------------------------------------- |
|
19 | 19 | COMPONENT lpp_lfr_ms_test |
|
20 | 20 | GENERIC ( |
|
21 | 21 | Mem_use : INTEGER); |
|
22 | 22 | PORT ( |
|
23 | 23 | clk : IN STD_LOGIC; |
|
24 | 24 | rstn : IN STD_LOGIC; |
|
25 | 25 | |
|
26 | 26 | -- TIME |
|
27 | 27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
28 | 28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
29 | 29 | -- |
|
30 | 30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
31 | 31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
32 | 32 | -- |
|
33 | 33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
34 | 34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
35 | 35 | -- |
|
36 | 36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
37 | 37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
38 | 38 | |
|
39 | 39 | |
|
40 | 40 | |
|
41 | 41 | --------------------------------------------------------------------------- |
|
42 | 42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
43 | 43 | |
|
44 | 44 | -- |
|
45 | 45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
46 | 46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
47 | 47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
48 | 48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
49 | 49 | |
|
50 | 50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
51 | 51 | |
|
52 | 52 | -- IN |
|
53 | 53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
54 | 54 | |
|
55 | 55 | ----------------------------------------------------------------------------- |
|
56 | 56 | |
|
57 | 57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
58 | 58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
59 | 59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
60 | 60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
61 | 61 | |
|
62 | 62 | SM_correlation_start : OUT STD_LOGIC; |
|
63 | 63 | SM_correlation_auto : OUT STD_LOGIC; |
|
64 | 64 | SM_correlation_done : IN STD_LOGIC |
|
65 | 65 | ); |
|
66 | 66 | END COMPONENT; |
|
67 | 67 | |
|
68 | 68 | |
|
69 | 69 | ----------------------------------------------------------------------------- |
|
70 | 70 | COMPONENT lpp_lfr_ms |
|
71 | 71 | GENERIC ( |
|
72 | 72 | Mem_use : INTEGER); |
|
73 | 73 | PORT ( |
|
74 | 74 | clk : IN STD_LOGIC; |
|
75 | 75 | rstn : IN STD_LOGIC; |
|
76 | 76 | run : IN STD_LOGIC; |
|
77 | 77 | start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
78 | 78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | 79 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
80 | 80 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
81 | 81 | sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
82 | 82 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
83 | 83 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
84 | 84 | sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
85 | 85 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
86 | 86 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
87 | 87 | sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
88 | 88 | dma_fifo_burst_valid : OUT STD_LOGIC; |
|
89 | 89 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | 90 | dma_fifo_ren : IN STD_LOGIC; |
|
91 | 91 | dma_buffer_new : OUT STD_LOGIC; |
|
92 | 92 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | 93 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
94 | 94 | dma_buffer_full : IN STD_LOGIC; |
|
95 | 95 | dma_buffer_full_err : IN STD_LOGIC; |
|
96 | 96 | ready_matrix_f0 : OUT STD_LOGIC; |
|
97 | 97 | ready_matrix_f1 : OUT STD_LOGIC; |
|
98 | 98 | ready_matrix_f2 : OUT STD_LOGIC; |
|
99 | 99 | error_buffer_full : OUT STD_LOGIC; |
|
100 | 100 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
101 | 101 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
102 | 102 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
103 | 103 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
104 | 104 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
105 | 105 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
106 | 106 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
107 | 107 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
108 | 108 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
109 | 109 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
110 | 110 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
111 | 111 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
112 | 112 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
113 | 113 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); |
|
114 | 114 | END COMPONENT; |
|
115 | 115 | |
|
116 | 116 | COMPONENT lpp_lfr_ms_fsmdma |
|
117 | 117 | PORT ( |
|
118 | 118 | clk : IN STD_ULOGIC; |
|
119 | 119 | rstn : IN STD_ULOGIC; |
|
120 | 120 | run : IN STD_LOGIC; |
|
121 | 121 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
122 | 122 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
123 | 123 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
124 | 124 | fifo_empty : IN STD_LOGIC; |
|
125 | 125 | fifo_empty_threshold : IN STD_LOGIC; |
|
126 | 126 | fifo_ren : OUT STD_LOGIC; |
|
127 | 127 | dma_fifo_valid_burst : OUT STD_LOGIC; |
|
128 | 128 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
129 | 129 | dma_fifo_ren : IN STD_LOGIC; |
|
130 | 130 | dma_buffer_new : OUT STD_LOGIC; |
|
131 | 131 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
132 | 132 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
133 | 133 | dma_buffer_full : IN STD_LOGIC; |
|
134 | 134 | dma_buffer_full_err : IN STD_LOGIC; |
|
135 | 135 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
136 | 136 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
137 | 137 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
138 | 138 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
139 | 139 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | 140 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
141 | 141 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
142 | 142 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
143 | 143 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
144 | 144 | ready_matrix_f0 : OUT STD_LOGIC; |
|
145 | 145 | ready_matrix_f1 : OUT STD_LOGIC; |
|
146 | 146 | ready_matrix_f2 : OUT STD_LOGIC; |
|
147 | 147 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
148 | 148 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
149 | 149 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
150 | 150 | error_buffer_full : OUT STD_LOGIC); |
|
151 | 151 | END COMPONENT; |
|
152 | 152 | |
|
153 | 153 | COMPONENT lpp_lfr_ms_FFT |
|
154 | 154 | PORT ( |
|
155 | 155 | clk : IN STD_LOGIC; |
|
156 | 156 | rstn : IN STD_LOGIC; |
|
157 | 157 | sample_valid : IN STD_LOGIC; |
|
158 | 158 | fft_read : IN STD_LOGIC; |
|
159 | 159 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
160 | 160 | sample_load : OUT STD_LOGIC; |
|
161 | 161 | fft_pong : OUT STD_LOGIC; |
|
162 | 162 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
163 | 163 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
164 | 164 | fft_data_valid : OUT STD_LOGIC; |
|
165 | 165 | fft_ready : OUT STD_LOGIC); |
|
166 | 166 | END COMPONENT; |
|
167 | 167 | |
|
168 | 168 | COMPONENT lpp_lfr_filter |
|
169 | 169 | GENERIC ( |
|
170 | 170 | Mem_use : INTEGER); |
|
171 | 171 | PORT ( |
|
172 | 172 | sample : IN Samples(7 DOWNTO 0); |
|
173 | 173 | sample_val : IN STD_LOGIC; |
|
174 | 174 | sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
175 | 175 | clk : IN STD_LOGIC; |
|
176 | 176 | rstn : IN STD_LOGIC; |
|
177 | 177 | data_shaping_SP0 : IN STD_LOGIC; |
|
178 | 178 | data_shaping_SP1 : IN STD_LOGIC; |
|
179 | 179 | data_shaping_R0 : IN STD_LOGIC; |
|
180 | 180 | data_shaping_R1 : IN STD_LOGIC; |
|
181 | 181 | data_shaping_R2 : IN STD_LOGIC; |
|
182 | 182 | sample_f0_val : OUT STD_LOGIC; |
|
183 | 183 | sample_f1_val : OUT STD_LOGIC; |
|
184 | 184 | sample_f2_val : OUT STD_LOGIC; |
|
185 | 185 | sample_f3_val : OUT STD_LOGIC; |
|
186 | 186 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
187 | 187 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
188 | 188 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
189 | 189 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
190 | 190 | sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
191 | 191 | sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
192 | 192 | sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
193 | 193 | sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
194 | 194 | ); |
|
195 | 195 | END COMPONENT; |
|
196 | 196 | |
|
197 | 197 | COMPONENT lpp_lfr |
|
198 | 198 | GENERIC ( |
|
199 | 199 | Mem_use : INTEGER; |
|
200 | tech : INTEGER; | |
|
200 | 201 | nb_data_by_buffer_size : INTEGER; |
|
201 | 202 | -- nb_word_by_buffer_size : INTEGER; |
|
202 | 203 | nb_snapshot_param_size : INTEGER; |
|
203 | 204 | delta_vector_size : INTEGER; |
|
204 | 205 | delta_vector_size_f0_2 : INTEGER; |
|
205 | 206 | pindex : INTEGER; |
|
206 | 207 | paddr : INTEGER; |
|
207 | 208 | pmask : INTEGER; |
|
208 | 209 | pirq_ms : INTEGER; |
|
209 | 210 | pirq_wfp : INTEGER; |
|
210 | 211 | hindex : INTEGER; |
|
211 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) | |
|
212 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0); | |
|
213 | DEBUG_FORCE_DATA_DMA : INTEGER | |
|
212 | 214 | ); |
|
213 | 215 | PORT ( |
|
214 | 216 | clk : IN STD_LOGIC; |
|
215 | 217 | rstn : IN STD_LOGIC; |
|
216 | 218 | sample_B : IN Samples(2 DOWNTO 0); |
|
217 | 219 | sample_E : IN Samples(4 DOWNTO 0); |
|
218 | 220 | sample_val : IN STD_LOGIC; |
|
219 | 221 | apbi : IN apb_slv_in_type; |
|
220 | 222 | apbo : OUT apb_slv_out_type; |
|
221 | 223 | ahbi : IN AHB_Mst_In_Type; |
|
222 | 224 | ahbo : OUT AHB_Mst_Out_Type; |
|
223 | 225 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
224 | 226 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
225 | 227 | data_shaping_BW : OUT STD_LOGIC; |
|
226 | 228 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
227 | 229 | debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) |
|
228 | 230 | ); |
|
229 | 231 | END COMPONENT; |
|
230 | 232 | |
|
231 | 233 | ----------------------------------------------------------------------------- |
|
232 | 234 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) |
|
233 | 235 | ----------------------------------------------------------------------------- |
|
234 | 236 | COMPONENT lpp_lfr_WFP_nMS |
|
235 | 237 | GENERIC ( |
|
236 | 238 | Mem_use : INTEGER; |
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237 | 239 | nb_data_by_buffer_size : INTEGER; |
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238 | 240 | nb_word_by_buffer_size : INTEGER; |
|
239 | 241 | nb_snapshot_param_size : INTEGER; |
|
240 | 242 | delta_vector_size : INTEGER; |
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241 | 243 | delta_vector_size_f0_2 : INTEGER; |
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242 | 244 | pindex : INTEGER; |
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243 | 245 | paddr : INTEGER; |
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244 | 246 | pmask : INTEGER; |
|
245 | 247 | pirq_ms : INTEGER; |
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246 | 248 | pirq_wfp : INTEGER; |
|
247 | 249 | hindex : INTEGER; |
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248 | 250 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
249 | 251 | PORT ( |
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250 | 252 | clk : IN STD_LOGIC; |
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251 | 253 | rstn : IN STD_LOGIC; |
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252 | 254 | sample_B : IN Samples(2 DOWNTO 0); |
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253 | 255 | sample_E : IN Samples(4 DOWNTO 0); |
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254 | 256 | sample_val : IN STD_LOGIC; |
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255 | 257 | apbi : IN apb_slv_in_type; |
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256 | 258 | apbo : OUT apb_slv_out_type; |
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257 | 259 | ahbi : IN AHB_Mst_In_Type; |
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258 | 260 | ahbo : OUT AHB_Mst_Out_Type; |
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259 | 261 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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260 | 262 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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261 | 263 | data_shaping_BW : OUT STD_LOGIC; |
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262 | 264 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
263 | 265 | END COMPONENT; |
|
264 | 266 | ----------------------------------------------------------------------------- |
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265 | 267 | |
|
266 | 268 | COMPONENT lpp_lfr_apbreg |
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267 | 269 | GENERIC ( |
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268 | 270 | nb_data_by_buffer_size : INTEGER; |
|
269 | 271 | nb_snapshot_param_size : INTEGER; |
|
270 | 272 | delta_vector_size : INTEGER; |
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271 | 273 | delta_vector_size_f0_2 : INTEGER; |
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272 | 274 | pindex : INTEGER; |
|
273 | 275 | paddr : INTEGER; |
|
274 | 276 | pmask : INTEGER; |
|
275 | 277 | pirq_ms : INTEGER; |
|
276 | 278 | pirq_wfp : INTEGER; |
|
277 | 279 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
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278 | 280 | PORT ( |
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279 | 281 | HCLK : IN STD_ULOGIC; |
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280 | 282 | HRESETn : IN STD_ULOGIC; |
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281 | 283 | apbi : IN apb_slv_in_type; |
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282 | 284 | apbo : OUT apb_slv_out_type; |
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283 | 285 | run_ms : OUT STD_LOGIC; |
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284 | 286 | ready_matrix_f0 : IN STD_LOGIC; |
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285 | 287 | ready_matrix_f1 : IN STD_LOGIC; |
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286 | 288 | ready_matrix_f2 : IN STD_LOGIC; |
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287 | 289 | error_buffer_full : IN STD_LOGIC; |
|
288 | 290 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
289 | 291 | status_ready_matrix_f0 : OUT STD_LOGIC; |
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290 | 292 | status_ready_matrix_f1 : OUT STD_LOGIC; |
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291 | 293 | status_ready_matrix_f2 : OUT STD_LOGIC; |
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292 | 294 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
293 | 295 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
294 | 296 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
295 | 297 | length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
296 | 298 | length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
297 | 299 | length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
298 | 300 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
299 | 301 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
300 | 302 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
301 | 303 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
302 | 304 | data_shaping_BW : OUT STD_LOGIC; |
|
303 | 305 | data_shaping_SP0 : OUT STD_LOGIC; |
|
304 | 306 | data_shaping_SP1 : OUT STD_LOGIC; |
|
305 | 307 | data_shaping_R0 : OUT STD_LOGIC; |
|
306 | 308 | data_shaping_R1 : OUT STD_LOGIC; |
|
307 | 309 | data_shaping_R2 : OUT STD_LOGIC; |
|
308 | 310 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
309 | 311 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
310 | 312 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
311 | 313 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
312 | 314 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
313 | 315 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
314 | 316 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
315 | 317 | enable_f0 : OUT STD_LOGIC; |
|
316 | 318 | enable_f1 : OUT STD_LOGIC; |
|
317 | 319 | enable_f2 : OUT STD_LOGIC; |
|
318 | 320 | enable_f3 : OUT STD_LOGIC; |
|
319 | 321 | burst_f0 : OUT STD_LOGIC; |
|
320 | 322 | burst_f1 : OUT STD_LOGIC; |
|
321 | 323 | burst_f2 : OUT STD_LOGIC; |
|
322 | 324 | run : OUT STD_LOGIC; |
|
323 | 325 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
324 | 326 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
325 | 327 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
|
326 | 328 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
327 | 329 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
328 | 330 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
329 | 331 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
330 | 332 | sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
331 | 333 | sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
332 | 334 | sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
333 | 335 | sample_f3_valid : IN STD_LOGIC; |
|
334 | 336 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); |
|
335 | 337 | END COMPONENT; |
|
336 | 338 | |
|
337 | 339 | COMPONENT lpp_top_ms |
|
338 | 340 | GENERIC ( |
|
339 | 341 | Mem_use : INTEGER; |
|
340 | 342 | nb_burst_available_size : INTEGER; |
|
341 | 343 | nb_snapshot_param_size : INTEGER; |
|
342 | 344 | delta_snapshot_size : INTEGER; |
|
343 | 345 | delta_f2_f0_size : INTEGER; |
|
344 | 346 | delta_f2_f1_size : INTEGER; |
|
345 | 347 | pindex : INTEGER; |
|
346 | 348 | paddr : INTEGER; |
|
347 | 349 | pmask : INTEGER; |
|
348 | 350 | pirq_ms : INTEGER; |
|
349 | 351 | pirq_wfp : INTEGER; |
|
350 | 352 | hindex_wfp : INTEGER; |
|
351 | 353 | hindex_ms : INTEGER); |
|
352 | 354 | PORT ( |
|
353 | 355 | clk : IN STD_LOGIC; |
|
354 | 356 | rstn : IN STD_LOGIC; |
|
355 | 357 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
356 | 358 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
357 | 359 | sample_val : IN STD_LOGIC; |
|
358 | 360 | apbi : IN apb_slv_in_type; |
|
359 | 361 | apbo : OUT apb_slv_out_type; |
|
360 | 362 | ahbi_ms : IN AHB_Mst_In_Type; |
|
361 | 363 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
362 | 364 | data_shaping_BW : OUT STD_LOGIC; |
|
363 | 365 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
364 | 366 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
365 | 367 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
366 | 368 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
367 | 369 | ); |
|
368 | 370 | END COMPONENT; |
|
369 | 371 | |
|
370 | 372 | COMPONENT lpp_apbreg_ms_pointer |
|
371 | 373 | PORT ( |
|
372 | 374 | clk : IN STD_LOGIC; |
|
373 | 375 | rstn : IN STD_LOGIC; |
|
374 | 376 | run : IN STD_LOGIC; |
|
375 | 377 | reg0_status_ready_matrix : IN STD_LOGIC; |
|
376 | 378 | reg0_ready_matrix : OUT STD_LOGIC; |
|
377 | 379 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
378 | 380 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
379 | 381 | reg1_status_ready_matrix : IN STD_LOGIC; |
|
380 | 382 | reg1_ready_matrix : OUT STD_LOGIC; |
|
381 | 383 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
382 | 384 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
383 | 385 | ready_matrix : IN STD_LOGIC; |
|
384 | 386 | status_ready_matrix : OUT STD_LOGIC; |
|
385 | 387 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
386 | 388 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
387 | 389 | END COMPONENT; |
|
388 | 390 | |
|
389 | 391 | COMPONENT lpp_lfr_ms_reg_head |
|
390 | 392 | PORT ( |
|
391 | 393 | clk : IN STD_LOGIC; |
|
392 | 394 | rstn : IN STD_LOGIC; |
|
393 | 395 | in_wen : IN STD_LOGIC; |
|
394 | 396 | in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
|
395 | 397 | in_full : IN STD_LOGIC; |
|
396 | 398 | in_empty : IN STD_LOGIC; |
|
397 | 399 | out_write_error : OUT STD_LOGIC; |
|
398 | 400 | out_wen : OUT STD_LOGIC; |
|
399 | 401 | out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
|
400 | 402 | out_full : OUT STD_LOGIC); |
|
401 | 403 | END COMPONENT; |
|
402 | 404 | |
|
403 | END lpp_lfr_pkg; No newline at end of file | |
|
405 | END lpp_lfr_pkg; |
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