@@ -1,411 +1,411 | |||||
1 | LIBRARY ieee; |
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1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
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2 | USE ieee.std_logic_1164.ALL; | |
3 |
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3 | |||
4 | LIBRARY lpp; |
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4 | LIBRARY lpp; | |
5 | USE lpp.lpp_ad_conv.ALL; |
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5 | USE lpp.lpp_ad_conv.ALL; | |
6 | USE lpp.iir_filter.ALL; |
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6 | USE lpp.iir_filter.ALL; | |
7 | USE lpp.FILTERcfg.ALL; |
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7 | USE lpp.FILTERcfg.ALL; | |
8 | USE lpp.lpp_memory.ALL; |
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8 | USE lpp.lpp_memory.ALL; | |
9 | USE lpp.lpp_waveform_pkg.ALL; |
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9 | USE lpp.lpp_waveform_pkg.ALL; | |
10 |
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10 | |||
11 | LIBRARY techmap; |
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11 | LIBRARY techmap; | |
12 | USE techmap.gencomp.ALL; |
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12 | USE techmap.gencomp.ALL; | |
13 |
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13 | |||
14 | LIBRARY grlib; |
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14 | LIBRARY grlib; | |
15 | USE grlib.amba.ALL; |
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15 | USE grlib.amba.ALL; | |
16 | USE grlib.stdlib.ALL; |
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16 | USE grlib.stdlib.ALL; | |
17 | USE grlib.devices.ALL; |
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17 | USE grlib.devices.ALL; | |
18 | USE GRLIB.DMA2AHB_Package.ALL; |
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18 | USE GRLIB.DMA2AHB_Package.ALL; | |
19 |
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19 | |||
20 | ENTITY Top_Data_Acquisition IS |
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20 | ENTITY Top_Data_Acquisition IS | |
21 | GENERIC( |
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21 | GENERIC( | |
22 | hindex : INTEGER := 2; |
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22 | hindex : INTEGER := 2; | |
23 | nb_burst_available_size : INTEGER := 11; |
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23 | nb_burst_available_size : INTEGER := 11; | |
24 | nb_snapshot_param_size : INTEGER := 11; |
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24 | nb_snapshot_param_size : INTEGER := 11; | |
25 | delta_snapshot_size : INTEGER := 16; |
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25 | delta_snapshot_size : INTEGER := 16; | |
26 | delta_f2_f0_size : INTEGER := 10; |
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26 | delta_f2_f0_size : INTEGER := 10; | |
27 | delta_f2_f1_size : INTEGER := 10; |
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27 | delta_f2_f1_size : INTEGER := 10; | |
28 | tech : INTEGER := 0 |
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28 | tech : INTEGER := 0 | |
29 | ); |
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29 | ); | |
30 | PORT ( |
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30 | PORT ( | |
31 | -- ADS7886 |
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31 | -- ADS7886 | |
32 | cnv_run : IN STD_LOGIC; |
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32 | cnv_run : IN STD_LOGIC; | |
33 | cnv : OUT STD_LOGIC; |
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33 | cnv : OUT STD_LOGIC; | |
34 | sck : OUT STD_LOGIC; |
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34 | sck : OUT STD_LOGIC; | |
35 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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35 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
36 | -- |
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36 | -- | |
37 | cnv_clk : IN STD_LOGIC; |
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37 | cnv_clk : IN STD_LOGIC; | |
38 | cnv_rstn : IN STD_LOGIC; |
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38 | cnv_rstn : IN STD_LOGIC; | |
39 | -- |
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39 | -- | |
40 | clk : IN STD_LOGIC; |
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40 | clk : IN STD_LOGIC; | |
41 | rstn : IN STD_LOGIC; |
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41 | rstn : IN STD_LOGIC; | |
42 | -- |
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42 | -- | |
43 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
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43 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
44 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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44 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
45 | -- |
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45 | -- | |
46 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
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46 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
47 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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47 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
48 | -- |
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48 | -- | |
49 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
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49 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
50 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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50 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
51 | -- |
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51 | -- | |
52 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
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52 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
53 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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53 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
54 |
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54 | |||
55 | -- AMBA AHB Master Interface |
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55 | -- AMBA AHB Master Interface | |
56 | AHB_Master_In : IN AHB_Mst_In_Type; |
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56 | AHB_Master_In : IN AHB_Mst_In_Type; | |
57 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
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57 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
58 |
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58 | |||
59 | coarse_time_0 : IN STD_LOGIC; |
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59 | coarse_time_0 : IN STD_LOGIC; | |
60 |
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60 | |||
61 | --config |
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61 | --config | |
62 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
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62 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
63 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
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63 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
64 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
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64 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
65 |
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65 | |||
66 | enable_f0 : IN STD_LOGIC; |
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66 | enable_f0 : IN STD_LOGIC; | |
67 | enable_f1 : IN STD_LOGIC; |
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67 | enable_f1 : IN STD_LOGIC; | |
68 | enable_f2 : IN STD_LOGIC; |
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68 | enable_f2 : IN STD_LOGIC; | |
69 | enable_f3 : IN STD_LOGIC; |
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69 | enable_f3 : IN STD_LOGIC; | |
70 |
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70 | |||
71 | burst_f0 : IN STD_LOGIC; |
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71 | burst_f0 : IN STD_LOGIC; | |
72 | burst_f1 : IN STD_LOGIC; |
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72 | burst_f1 : IN STD_LOGIC; | |
73 | burst_f2 : IN STD_LOGIC; |
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73 | burst_f2 : IN STD_LOGIC; | |
74 |
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74 | |||
75 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
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75 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
76 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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76 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
77 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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77 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
78 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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78 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
79 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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79 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
80 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma |
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80 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |
81 |
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81 | |||
82 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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82 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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83 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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84 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
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85 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
86 | ); |
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86 | ); | |
87 | END Top_Data_Acquisition; |
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87 | END Top_Data_Acquisition; | |
88 |
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88 | |||
89 | ARCHITECTURE tb OF Top_Data_Acquisition IS |
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89 | ARCHITECTURE tb OF Top_Data_Acquisition IS | |
90 |
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90 | |||
91 | COMPONENT Downsampling |
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91 | COMPONENT Downsampling | |
92 | GENERIC ( |
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92 | GENERIC ( | |
93 | ChanelCount : INTEGER; |
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93 | ChanelCount : INTEGER; | |
94 | SampleSize : INTEGER; |
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94 | SampleSize : INTEGER; | |
95 | DivideParam : INTEGER); |
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95 | DivideParam : INTEGER); | |
96 | PORT ( |
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96 | PORT ( | |
97 | clk : IN STD_LOGIC; |
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97 | clk : IN STD_LOGIC; | |
98 | rstn : IN STD_LOGIC; |
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98 | rstn : IN STD_LOGIC; | |
99 | sample_in_val : IN STD_LOGIC; |
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99 | sample_in_val : IN STD_LOGIC; | |
100 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); |
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100 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |
101 | sample_out_val : OUT STD_LOGIC; |
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101 | sample_out_val : OUT STD_LOGIC; | |
102 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); |
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102 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |
103 | END COMPONENT; |
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103 | END COMPONENT; | |
104 |
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104 | |||
105 | ----------------------------------------------------------------------------- |
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105 | ----------------------------------------------------------------------------- | |
106 | CONSTANT ChanelCount : INTEGER := 8; |
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106 | CONSTANT ChanelCount : INTEGER := 8; | |
107 | CONSTANT ncycle_cnv_high : INTEGER := 79; |
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107 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
108 | CONSTANT ncycle_cnv : INTEGER := 500; |
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108 | CONSTANT ncycle_cnv : INTEGER := 500; | |
109 |
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109 | |||
110 | ----------------------------------------------------------------------------- |
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110 | ----------------------------------------------------------------------------- | |
111 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); |
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111 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
112 | SIGNAL sample_val : STD_LOGIC; |
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112 | SIGNAL sample_val : STD_LOGIC; | |
113 | SIGNAL sample_val_delay : STD_LOGIC; |
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113 | SIGNAL sample_val_delay : STD_LOGIC; | |
114 | ----------------------------------------------------------------------------- |
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114 | ----------------------------------------------------------------------------- | |
115 | CONSTANT Coef_SZ : INTEGER := 9; |
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115 | CONSTANT Coef_SZ : INTEGER := 9; | |
116 | CONSTANT CoefCntPerCel : INTEGER := 6; |
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116 | CONSTANT CoefCntPerCel : INTEGER := 6; | |
117 | CONSTANT CoefPerCel : INTEGER := 5; |
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117 | CONSTANT CoefPerCel : INTEGER := 5; | |
118 | CONSTANT Cels_count : INTEGER := 5; |
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118 | CONSTANT Cels_count : INTEGER := 5; | |
119 |
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119 | |||
120 | SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); |
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120 | SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); | |
121 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); |
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121 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |
122 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
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122 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
123 | SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
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123 | SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
124 | -- |
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124 | -- | |
125 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; |
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125 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
126 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
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126 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
127 | SIGNAL sample_filter_v2_out_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
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127 | SIGNAL sample_filter_v2_out_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
128 | ----------------------------------------------------------------------------- |
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128 | ----------------------------------------------------------------------------- | |
129 | SIGNAL sample_f0_val : STD_LOGIC; |
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129 | SIGNAL sample_f0_val : STD_LOGIC; | |
130 | SIGNAL sample_f0 : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
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130 | SIGNAL sample_f0 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
131 | -- |
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131 | -- | |
132 | SIGNAL sample_f1_val : STD_LOGIC; |
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132 | SIGNAL sample_f1_val : STD_LOGIC; | |
133 | SIGNAL sample_f1 : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
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133 | SIGNAL sample_f1 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
134 | -- |
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134 | -- | |
135 | SIGNAL sample_f2_val : STD_LOGIC; |
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135 | SIGNAL sample_f2_val : STD_LOGIC; | |
136 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
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136 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
137 | -- |
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137 | -- | |
138 | SIGNAL sample_f3_val : STD_LOGIC; |
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138 | SIGNAL sample_f3_val : STD_LOGIC; | |
139 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
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139 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
140 |
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140 | |||
141 | ----------------------------------------------------------------------------- |
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141 | ----------------------------------------------------------------------------- | |
142 | SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
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142 | SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
143 | SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
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143 | SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
144 | SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
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144 | SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
145 | SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
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145 | SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
146 | ----------------------------------------------------------------------------- |
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146 | ----------------------------------------------------------------------------- | |
147 |
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147 | |||
148 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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148 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
149 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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149 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
150 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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150 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
151 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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151 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
152 | BEGIN |
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152 | BEGIN | |
153 |
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153 | |||
154 | -- component instantiation |
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154 | -- component instantiation | |
155 | ----------------------------------------------------------------------------- |
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155 | ----------------------------------------------------------------------------- | |
156 | DIGITAL_acquisition : AD7688_drvr |
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156 | DIGITAL_acquisition : AD7688_drvr | |
157 | GENERIC MAP ( |
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157 | GENERIC MAP ( | |
158 | ChanelCount => ChanelCount, |
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158 | ChanelCount => ChanelCount, | |
159 | ncycle_cnv_high => ncycle_cnv_high, |
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159 | ncycle_cnv_high => ncycle_cnv_high, | |
160 | ncycle_cnv => ncycle_cnv) |
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160 | ncycle_cnv => ncycle_cnv) | |
161 | PORT MAP ( |
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161 | PORT MAP ( | |
162 | cnv_clk => cnv_clk, -- |
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162 | cnv_clk => cnv_clk, -- | |
163 | cnv_rstn => cnv_rstn, -- |
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163 | cnv_rstn => cnv_rstn, -- | |
164 | cnv_run => cnv_run, -- |
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164 | cnv_run => cnv_run, -- | |
165 | cnv => cnv, -- |
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165 | cnv => cnv, -- | |
166 | clk => clk, -- |
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166 | clk => clk, -- | |
167 | rstn => rstn, -- |
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167 | rstn => rstn, -- | |
168 | sck => sck, -- |
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168 | sck => sck, -- | |
169 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- |
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169 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |
170 | sample => sample, |
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170 | sample => sample, | |
171 | sample_val => sample_val); |
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171 | sample_val => sample_val); | |
172 |
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172 | |||
173 | ----------------------------------------------------------------------------- |
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173 | ----------------------------------------------------------------------------- | |
174 |
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174 | |||
175 | PROCESS (clk, rstn) |
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175 | PROCESS (clk, rstn) | |
176 | BEGIN -- PROCESS |
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176 | BEGIN -- PROCESS | |
177 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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177 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
178 | sample_val_delay <= '0'; |
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178 | sample_val_delay <= '0'; | |
179 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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179 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
180 | sample_val_delay <= sample_val; |
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180 | sample_val_delay <= sample_val; | |
181 | END IF; |
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181 | END IF; | |
182 | END PROCESS; |
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182 | END PROCESS; | |
183 |
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183 | |||
184 | ----------------------------------------------------------------------------- |
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184 | ----------------------------------------------------------------------------- | |
185 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE |
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185 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |
186 | SampleLoop : FOR j IN 0 TO 15 GENERATE |
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186 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |
187 | sample_filter_in(i, j) <= sample(i)(j); |
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187 | sample_filter_in(i, j) <= sample(i)(j); | |
188 | END GENERATE; |
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188 | END GENERATE; | |
189 |
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189 | |||
190 | sample_filter_in(i, 16) <= sample(i)(15); |
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190 | sample_filter_in(i, 16) <= sample(i)(15); | |
191 | sample_filter_in(i, 17) <= sample(i)(15); |
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191 | sample_filter_in(i, 17) <= sample(i)(15); | |
192 | END GENERATE; |
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192 | END GENERATE; | |
193 |
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193 | |||
194 |
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194 | coefs_v2 <= CoefsInitValCst_v2; | |
195 |
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195 | |||
196 |
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196 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
197 |
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197 | GENERIC MAP ( | |
198 |
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198 | tech => 0, | |
199 |
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199 | Mem_use => use_RAM, | |
200 |
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200 | Sample_SZ => 18, | |
201 |
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201 | Coef_SZ => Coef_SZ, | |
202 |
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202 | Coef_Nb => 25, | |
203 |
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203 | Coef_sel_SZ => 5, | |
204 |
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204 | Cels_count => Cels_count, | |
205 |
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205 | ChanelsCount => ChanelCount) | |
206 |
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206 | PORT MAP ( | |
207 |
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207 | rstn => rstn, | |
208 |
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208 | clk => clk, | |
209 |
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209 | virg_pos => 7, | |
210 |
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210 | coefs => coefs_v2, | |
211 |
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211 | sample_in_val => sample_val_delay, | |
212 |
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212 | sample_in => sample_filter_in, | |
213 |
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213 | sample_out_val => sample_filter_v2_out_val, | |
214 |
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214 | sample_out => sample_filter_v2_out); | |
215 |
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215 | |||
216 | sample_filter_v2_out_val <= sample_val_delay; |
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216 | --sample_filter_v2_out_val <= sample_val_delay; | |
217 |
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217 | |||
218 | ChanelLoopOut : FOR i IN 0 TO 5 GENERATE |
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218 | ChanelLoopOut : FOR i IN 0 TO 5 GENERATE | |
219 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE |
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219 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE | |
220 |
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|
220 | sample_filter_v2_out_s(i, j) <= sample_filter_v2_out(i, j); | |
221 | sample_filter_v2_out_s(i, j) <= sample_filter_in(i, j); |
|
221 | --sample_filter_v2_out_s(i, j) <= sample_filter_in(i, j); | |
222 | END GENERATE; |
|
222 | END GENERATE; | |
223 | END GENERATE; |
|
223 | END GENERATE; | |
224 | ----------------------------------------------------------------------------- |
|
224 | ----------------------------------------------------------------------------- | |
225 | -- F0 -- @24.576 kHz |
|
225 | -- F0 -- @24.576 kHz | |
226 | ----------------------------------------------------------------------------- |
|
226 | ----------------------------------------------------------------------------- | |
227 | Downsampling_f0 : Downsampling |
|
227 | Downsampling_f0 : Downsampling | |
228 | GENERIC MAP ( |
|
228 | GENERIC MAP ( | |
229 | ChanelCount => 6, |
|
229 | ChanelCount => 6, | |
230 | SampleSize => 16, |
|
230 | SampleSize => 16, | |
231 | DivideParam => 4) |
|
231 | DivideParam => 4) | |
232 | PORT MAP ( |
|
232 | PORT MAP ( | |
233 | clk => clk, |
|
233 | clk => clk, | |
234 | rstn => rstn, |
|
234 | rstn => rstn, | |
235 | sample_in_val => sample_filter_v2_out_val, |
|
235 | sample_in_val => sample_filter_v2_out_val, | |
236 | sample_in => sample_filter_v2_out_s, |
|
236 | sample_in => sample_filter_v2_out_s, | |
237 | sample_out_val => sample_f0_val, |
|
237 | sample_out_val => sample_f0_val, | |
238 | sample_out => sample_f0); |
|
238 | sample_out => sample_f0); | |
239 |
|
239 | |||
240 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE |
|
240 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
241 | sample_f0_wdata_s(I) <= sample_f0(0, I); |
|
241 | sample_f0_wdata_s(I) <= sample_f0(0, I); | |
242 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I); |
|
242 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I); | |
243 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I); |
|
243 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I); | |
244 | sample_f0_wdata_s(16*3+I) <= sample_f0(3, I); |
|
244 | sample_f0_wdata_s(16*3+I) <= sample_f0(3, I); | |
245 | sample_f0_wdata_s(16*4+I) <= sample_f0(4, I); |
|
245 | sample_f0_wdata_s(16*4+I) <= sample_f0(4, I); | |
246 | sample_f0_wdata_s(16*5+I) <= sample_f0(5, I); |
|
246 | sample_f0_wdata_s(16*5+I) <= sample_f0(5, I); | |
247 | END GENERATE all_bit_sample_f0; |
|
247 | END GENERATE all_bit_sample_f0; | |
248 |
|
248 | |||
249 | sample_f0_wen <= NOT(sample_f0_val) & |
|
249 | sample_f0_wen <= NOT(sample_f0_val) & | |
250 | NOT(sample_f0_val) & |
|
250 | NOT(sample_f0_val) & | |
251 | NOT(sample_f0_val) & |
|
251 | NOT(sample_f0_val) & | |
252 | NOT(sample_f0_val) & |
|
252 | NOT(sample_f0_val) & | |
253 | NOT(sample_f0_val) & |
|
253 | NOT(sample_f0_val) & | |
254 | NOT(sample_f0_val); |
|
254 | NOT(sample_f0_val); | |
255 |
|
255 | |||
256 | ----------------------------------------------------------------------------- |
|
256 | ----------------------------------------------------------------------------- | |
257 | -- F1 -- @4096 Hz |
|
257 | -- F1 -- @4096 Hz | |
258 | ----------------------------------------------------------------------------- |
|
258 | ----------------------------------------------------------------------------- | |
259 | Downsampling_f1 : Downsampling |
|
259 | Downsampling_f1 : Downsampling | |
260 | GENERIC MAP ( |
|
260 | GENERIC MAP ( | |
261 | ChanelCount => 6, |
|
261 | ChanelCount => 6, | |
262 | SampleSize => 16, |
|
262 | SampleSize => 16, | |
263 | DivideParam => 6) |
|
263 | DivideParam => 6) | |
264 | PORT MAP ( |
|
264 | PORT MAP ( | |
265 | clk => clk, |
|
265 | clk => clk, | |
266 | rstn => rstn, |
|
266 | rstn => rstn, | |
267 | sample_in_val => sample_f0_val , |
|
267 | sample_in_val => sample_f0_val , | |
268 | sample_in => sample_f0, |
|
268 | sample_in => sample_f0, | |
269 | sample_out_val => sample_f1_val, |
|
269 | sample_out_val => sample_f1_val, | |
270 | sample_out => sample_f1); |
|
270 | sample_out => sample_f1); | |
271 |
|
271 | |||
272 | sample_f1_wen <= NOT(sample_f1_val) & |
|
272 | sample_f1_wen <= NOT(sample_f1_val) & | |
273 | NOT(sample_f1_val) & |
|
273 | NOT(sample_f1_val) & | |
274 | NOT(sample_f1_val) & |
|
274 | NOT(sample_f1_val) & | |
275 | NOT(sample_f1_val) & |
|
275 | NOT(sample_f1_val) & | |
276 | NOT(sample_f1_val) & |
|
276 | NOT(sample_f1_val) & | |
277 | NOT(sample_f1_val); |
|
277 | NOT(sample_f1_val); | |
278 |
|
278 | |||
279 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE |
|
279 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
280 | sample_f1_wdata_s(I) <= sample_f1(0, I); |
|
280 | sample_f1_wdata_s(I) <= sample_f1(0, I); | |
281 | sample_f1_wdata_s(16*1+I) <= sample_f1(1, I); |
|
281 | sample_f1_wdata_s(16*1+I) <= sample_f1(1, I); | |
282 | sample_f1_wdata_s(16*2+I) <= sample_f1(2, I); |
|
282 | sample_f1_wdata_s(16*2+I) <= sample_f1(2, I); | |
283 | sample_f1_wdata_s(16*3+I) <= sample_f1(3, I); |
|
283 | sample_f1_wdata_s(16*3+I) <= sample_f1(3, I); | |
284 | sample_f1_wdata_s(16*4+I) <= sample_f1(4, I); |
|
284 | sample_f1_wdata_s(16*4+I) <= sample_f1(4, I); | |
285 | sample_f1_wdata_s(16*5+I) <= sample_f1(5, I); |
|
285 | sample_f1_wdata_s(16*5+I) <= sample_f1(5, I); | |
286 | END GENERATE all_bit_sample_f1; |
|
286 | END GENERATE all_bit_sample_f1; | |
287 |
|
287 | |||
288 | ----------------------------------------------------------------------------- |
|
288 | ----------------------------------------------------------------------------- | |
289 | -- F2 -- @256 Hz |
|
289 | -- F2 -- @256 Hz | |
290 | ----------------------------------------------------------------------------- |
|
290 | ----------------------------------------------------------------------------- | |
291 | Downsampling_f2 : Downsampling |
|
291 | Downsampling_f2 : Downsampling | |
292 | GENERIC MAP ( |
|
292 | GENERIC MAP ( | |
293 | ChanelCount => 6, |
|
293 | ChanelCount => 6, | |
294 | SampleSize => 16, |
|
294 | SampleSize => 16, | |
295 | DivideParam => 96) |
|
295 | DivideParam => 96) | |
296 | PORT MAP ( |
|
296 | PORT MAP ( | |
297 | clk => clk, |
|
297 | clk => clk, | |
298 | rstn => rstn, |
|
298 | rstn => rstn, | |
299 | sample_in_val => sample_f0_val , |
|
299 | sample_in_val => sample_f0_val , | |
300 | sample_in => sample_f0, |
|
300 | sample_in => sample_f0, | |
301 | sample_out_val => sample_f2_val, |
|
301 | sample_out_val => sample_f2_val, | |
302 | sample_out => sample_f2); |
|
302 | sample_out => sample_f2); | |
303 |
|
303 | |||
304 | sample_f2_wen <= NOT(sample_f2_val) & |
|
304 | sample_f2_wen <= NOT(sample_f2_val) & | |
305 | NOT(sample_f2_val) & |
|
305 | NOT(sample_f2_val) & | |
306 | NOT(sample_f2_val) & |
|
306 | NOT(sample_f2_val) & | |
307 | NOT(sample_f2_val) & |
|
307 | NOT(sample_f2_val) & | |
308 | NOT(sample_f2_val) & |
|
308 | NOT(sample_f2_val) & | |
309 | NOT(sample_f2_val); |
|
309 | NOT(sample_f2_val); | |
310 |
|
310 | |||
311 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE |
|
311 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |
312 | sample_f2_wdata_s(I) <= sample_f2(0, I); |
|
312 | sample_f2_wdata_s(I) <= sample_f2(0, I); | |
313 | sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); |
|
313 | sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); | |
314 | sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); |
|
314 | sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); | |
315 | sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); |
|
315 | sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); | |
316 | sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); |
|
316 | sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); | |
317 | sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); |
|
317 | sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); | |
318 | END GENERATE all_bit_sample_f2; |
|
318 | END GENERATE all_bit_sample_f2; | |
319 |
|
319 | |||
320 | ----------------------------------------------------------------------------- |
|
320 | ----------------------------------------------------------------------------- | |
321 | -- F3 -- @16 Hz |
|
321 | -- F3 -- @16 Hz | |
322 | ----------------------------------------------------------------------------- |
|
322 | ----------------------------------------------------------------------------- | |
323 | Downsampling_f3 : Downsampling |
|
323 | Downsampling_f3 : Downsampling | |
324 | GENERIC MAP ( |
|
324 | GENERIC MAP ( | |
325 | ChanelCount => 6, |
|
325 | ChanelCount => 6, | |
326 | SampleSize => 16, |
|
326 | SampleSize => 16, | |
327 | DivideParam => 256) |
|
327 | DivideParam => 256) | |
328 | PORT MAP ( |
|
328 | PORT MAP ( | |
329 | clk => clk, |
|
329 | clk => clk, | |
330 | rstn => rstn, |
|
330 | rstn => rstn, | |
331 | sample_in_val => sample_f1_val , |
|
331 | sample_in_val => sample_f1_val , | |
332 | sample_in => sample_f1, |
|
332 | sample_in => sample_f1, | |
333 | sample_out_val => sample_f3_val, |
|
333 | sample_out_val => sample_f3_val, | |
334 | sample_out => sample_f3); |
|
334 | sample_out => sample_f3); | |
335 |
|
335 | |||
336 | sample_f3_wen <= (NOT sample_f3_val) & |
|
336 | sample_f3_wen <= (NOT sample_f3_val) & | |
337 | (NOT sample_f3_val) & |
|
337 | (NOT sample_f3_val) & | |
338 | (NOT sample_f3_val) & |
|
338 | (NOT sample_f3_val) & | |
339 | (NOT sample_f3_val) & |
|
339 | (NOT sample_f3_val) & | |
340 | (NOT sample_f3_val) & |
|
340 | (NOT sample_f3_val) & | |
341 | (NOT sample_f3_val); |
|
341 | (NOT sample_f3_val); | |
342 |
|
342 | |||
343 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE |
|
343 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
344 | sample_f3_wdata_s(I) <= sample_f3(0, I); |
|
344 | sample_f3_wdata_s(I) <= sample_f3(0, I); | |
345 | sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); |
|
345 | sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); | |
346 | sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); |
|
346 | sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); | |
347 | sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); |
|
347 | sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); | |
348 | sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); |
|
348 | sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); | |
349 | sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); |
|
349 | sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); | |
350 | END GENERATE all_bit_sample_f3; |
|
350 | END GENERATE all_bit_sample_f3; | |
351 |
|
351 | |||
352 | lpp_waveform_1 : lpp_waveform |
|
352 | lpp_waveform_1 : lpp_waveform | |
353 | GENERIC MAP ( |
|
353 | GENERIC MAP ( | |
354 | hindex => hindex, |
|
354 | hindex => hindex, | |
355 | tech => tech, |
|
355 | tech => tech, | |
356 | data_size => 160, |
|
356 | data_size => 160, | |
357 | nb_burst_available_size => nb_burst_available_size, |
|
357 | nb_burst_available_size => nb_burst_available_size, | |
358 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
358 | nb_snapshot_param_size => nb_snapshot_param_size, | |
359 | delta_snapshot_size => delta_snapshot_size, |
|
359 | delta_snapshot_size => delta_snapshot_size, | |
360 | delta_f2_f0_size => delta_f2_f0_size, |
|
360 | delta_f2_f0_size => delta_f2_f0_size, | |
361 | delta_f2_f1_size => delta_f2_f1_size) |
|
361 | delta_f2_f1_size => delta_f2_f1_size) | |
362 | PORT MAP ( |
|
362 | PORT MAP ( | |
363 | clk => clk, |
|
363 | clk => clk, | |
364 | rstn => rstn, |
|
364 | rstn => rstn, | |
365 |
|
365 | |||
366 | AHB_Master_In => AHB_Master_In, |
|
366 | AHB_Master_In => AHB_Master_In, | |
367 | AHB_Master_Out => AHB_Master_Out, |
|
367 | AHB_Master_Out => AHB_Master_Out, | |
368 |
|
368 | |||
369 | coarse_time_0 => coarse_time_0, -- IN |
|
369 | coarse_time_0 => coarse_time_0, -- IN | |
370 | delta_snapshot => delta_snapshot, -- IN |
|
370 | delta_snapshot => delta_snapshot, -- IN | |
371 | delta_f2_f1 => delta_f2_f1, -- IN |
|
371 | delta_f2_f1 => delta_f2_f1, -- IN | |
372 | delta_f2_f0 => delta_f2_f0, -- IN |
|
372 | delta_f2_f0 => delta_f2_f0, -- IN | |
373 | enable_f0 => enable_f0, -- IN |
|
373 | enable_f0 => enable_f0, -- IN | |
374 | enable_f1 => enable_f1, -- IN |
|
374 | enable_f1 => enable_f1, -- IN | |
375 | enable_f2 => enable_f2, -- IN |
|
375 | enable_f2 => enable_f2, -- IN | |
376 | enable_f3 => enable_f3, -- IN |
|
376 | enable_f3 => enable_f3, -- IN | |
377 | burst_f0 => burst_f0, -- IN |
|
377 | burst_f0 => burst_f0, -- IN | |
378 | burst_f1 => burst_f1, -- IN |
|
378 | burst_f1 => burst_f1, -- IN | |
379 | burst_f2 => burst_f2, -- IN |
|
379 | burst_f2 => burst_f2, -- IN | |
380 | nb_burst_available => nb_burst_available, |
|
380 | nb_burst_available => nb_burst_available, | |
381 | nb_snapshot_param => nb_snapshot_param, |
|
381 | nb_snapshot_param => nb_snapshot_param, | |
382 | status_full => status_full, |
|
382 | status_full => status_full, | |
383 | status_full_ack => status_full_ack, -- IN |
|
383 | status_full_ack => status_full_ack, -- IN | |
384 | status_full_err => status_full_err, |
|
384 | status_full_err => status_full_err, | |
385 | status_new_err => status_new_err, |
|
385 | status_new_err => status_new_err, | |
386 |
|
386 | |||
387 | addr_data_f0 => addr_data_f0, -- IN |
|
387 | addr_data_f0 => addr_data_f0, -- IN | |
388 | addr_data_f1 => addr_data_f1, -- IN |
|
388 | addr_data_f1 => addr_data_f1, -- IN | |
389 | addr_data_f2 => addr_data_f2, -- IN |
|
389 | addr_data_f2 => addr_data_f2, -- IN | |
390 | addr_data_f3 => addr_data_f3, -- IN |
|
390 | addr_data_f3 => addr_data_f3, -- IN | |
391 |
|
391 | |||
392 | data_f0_in => data_f0_in_valid, |
|
392 | data_f0_in => data_f0_in_valid, | |
393 | data_f1_in => data_f1_in_valid, |
|
393 | data_f1_in => data_f1_in_valid, | |
394 | data_f2_in => data_f2_in_valid, |
|
394 | data_f2_in => data_f2_in_valid, | |
395 | data_f3_in => data_f3_in_valid, |
|
395 | data_f3_in => data_f3_in_valid, | |
396 | data_f0_in_valid => sample_f0_val, |
|
396 | data_f0_in_valid => sample_f0_val, | |
397 | data_f1_in_valid => sample_f1_val, |
|
397 | data_f1_in_valid => sample_f1_val, | |
398 | data_f2_in_valid => sample_f2_val, |
|
398 | data_f2_in_valid => sample_f2_val, | |
399 | data_f3_in_valid => sample_f3_val); |
|
399 | data_f3_in_valid => sample_f3_val); | |
400 |
|
400 | |||
401 | data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; |
|
401 | data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; | |
402 | data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; |
|
402 | data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; | |
403 | data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; |
|
403 | data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; | |
404 | data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; |
|
404 | data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; | |
405 |
|
405 | |||
406 | sample_f0_wdata <= sample_f0_wdata_s; |
|
406 | sample_f0_wdata <= sample_f0_wdata_s; | |
407 | sample_f1_wdata <= sample_f1_wdata_s; |
|
407 | sample_f1_wdata <= sample_f1_wdata_s; | |
408 | sample_f2_wdata <= sample_f2_wdata_s; |
|
408 | sample_f2_wdata <= sample_f2_wdata_s; | |
409 | sample_f3_wdata <= sample_f3_wdata_s; |
|
409 | sample_f3_wdata <= sample_f3_wdata_s; | |
410 |
|
410 | |||
411 | END tb; |
|
411 | END tb; |
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