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1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY lpp;
5 5 USE lpp.lpp_ad_conv.ALL;
6 6 USE lpp.iir_filter.ALL;
7 7 USE lpp.FILTERcfg.ALL;
8 8 USE lpp.lpp_memory.ALL;
9 9 USE lpp.lpp_waveform_pkg.ALL;
10 10
11 11 LIBRARY techmap;
12 12 USE techmap.gencomp.ALL;
13 13
14 14 LIBRARY grlib;
15 15 USE grlib.amba.ALL;
16 16 USE grlib.stdlib.ALL;
17 17 USE grlib.devices.ALL;
18 18 USE GRLIB.DMA2AHB_Package.ALL;
19 19
20 20 ENTITY Top_Data_Acquisition IS
21 21 GENERIC(
22 22 hindex : INTEGER := 2;
23 23 nb_burst_available_size : INTEGER := 11;
24 24 nb_snapshot_param_size : INTEGER := 11;
25 25 delta_snapshot_size : INTEGER := 16;
26 26 delta_f2_f0_size : INTEGER := 10;
27 27 delta_f2_f1_size : INTEGER := 10;
28 28 tech : INTEGER := 0
29 29 );
30 30 PORT (
31 31 -- ADS7886
32 32 cnv_run : IN STD_LOGIC;
33 33 cnv : OUT STD_LOGIC;
34 34 sck : OUT STD_LOGIC;
35 35 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
36 36 --
37 37 cnv_clk : IN STD_LOGIC;
38 38 cnv_rstn : IN STD_LOGIC;
39 39 --
40 40 clk : IN STD_LOGIC;
41 41 rstn : IN STD_LOGIC;
42 42 --
43 43 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
44 44 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
45 45 --
46 46 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
47 47 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
48 48 --
49 49 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
50 50 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
51 51 --
52 52 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
53 53 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
54 54
55 55 -- AMBA AHB Master Interface
56 56 AHB_Master_In : IN AHB_Mst_In_Type;
57 57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 58
59 59 coarse_time_0 : IN STD_LOGIC;
60 60
61 61 --config
62 62 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
63 63 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
64 64 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
65 65
66 66 enable_f0 : IN STD_LOGIC;
67 67 enable_f1 : IN STD_LOGIC;
68 68 enable_f2 : IN STD_LOGIC;
69 69 enable_f3 : IN STD_LOGIC;
70 70
71 71 burst_f0 : IN STD_LOGIC;
72 72 burst_f1 : IN STD_LOGIC;
73 73 burst_f2 : IN STD_LOGIC;
74 74
75 75 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
76 76 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
77 77 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
78 78 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
79 79 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 80 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
81 81
82 82 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
86 86 );
87 87 END Top_Data_Acquisition;
88 88
89 89 ARCHITECTURE tb OF Top_Data_Acquisition IS
90 90
91 91 COMPONENT Downsampling
92 92 GENERIC (
93 93 ChanelCount : INTEGER;
94 94 SampleSize : INTEGER;
95 95 DivideParam : INTEGER);
96 96 PORT (
97 97 clk : IN STD_LOGIC;
98 98 rstn : IN STD_LOGIC;
99 99 sample_in_val : IN STD_LOGIC;
100 100 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
101 101 sample_out_val : OUT STD_LOGIC;
102 102 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
103 103 END COMPONENT;
104 104
105 105 -----------------------------------------------------------------------------
106 106 CONSTANT ChanelCount : INTEGER := 8;
107 107 CONSTANT ncycle_cnv_high : INTEGER := 79;
108 108 CONSTANT ncycle_cnv : INTEGER := 500;
109 109
110 110 -----------------------------------------------------------------------------
111 111 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
112 112 SIGNAL sample_val : STD_LOGIC;
113 113 SIGNAL sample_val_delay : STD_LOGIC;
114 114 -----------------------------------------------------------------------------
115 115 CONSTANT Coef_SZ : INTEGER := 9;
116 116 CONSTANT CoefCntPerCel : INTEGER := 6;
117 117 CONSTANT CoefPerCel : INTEGER := 5;
118 118 CONSTANT Cels_count : INTEGER := 5;
119 119
120 120 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
121 121 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
122 122 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
123 123 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
124 124 --
125 125 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
126 126 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
127 127 SIGNAL sample_filter_v2_out_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
128 128 -----------------------------------------------------------------------------
129 129 SIGNAL sample_f0_val : STD_LOGIC;
130 130 SIGNAL sample_f0 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
131 131 --
132 132 SIGNAL sample_f1_val : STD_LOGIC;
133 133 SIGNAL sample_f1 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
134 134 --
135 135 SIGNAL sample_f2_val : STD_LOGIC;
136 136 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
137 137 --
138 138 SIGNAL sample_f3_val : STD_LOGIC;
139 139 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
140 140
141 141 -----------------------------------------------------------------------------
142 142 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
143 143 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
144 144 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
145 145 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
146 146 -----------------------------------------------------------------------------
147 147
148 148 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
149 149 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
150 150 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
151 151 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
152 152 BEGIN
153 153
154 154 -- component instantiation
155 155 -----------------------------------------------------------------------------
156 156 DIGITAL_acquisition : AD7688_drvr
157 157 GENERIC MAP (
158 158 ChanelCount => ChanelCount,
159 159 ncycle_cnv_high => ncycle_cnv_high,
160 160 ncycle_cnv => ncycle_cnv)
161 161 PORT MAP (
162 162 cnv_clk => cnv_clk, --
163 163 cnv_rstn => cnv_rstn, --
164 164 cnv_run => cnv_run, --
165 165 cnv => cnv, --
166 166 clk => clk, --
167 167 rstn => rstn, --
168 168 sck => sck, --
169 169 sdo => sdo(ChanelCount-1 DOWNTO 0), --
170 170 sample => sample,
171 171 sample_val => sample_val);
172 172
173 173 -----------------------------------------------------------------------------
174 174
175 175 PROCESS (clk, rstn)
176 176 BEGIN -- PROCESS
177 177 IF rstn = '0' THEN -- asynchronous reset (active low)
178 178 sample_val_delay <= '0';
179 179 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
180 180 sample_val_delay <= sample_val;
181 181 END IF;
182 182 END PROCESS;
183 183
184 184 -----------------------------------------------------------------------------
185 185 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
186 186 SampleLoop : FOR j IN 0 TO 15 GENERATE
187 187 sample_filter_in(i, j) <= sample(i)(j);
188 188 END GENERATE;
189 189
190 190 sample_filter_in(i, 16) <= sample(i)(15);
191 191 sample_filter_in(i, 17) <= sample(i)(15);
192 192 END GENERATE;
193 193
194 --coefs_v2 <= CoefsInitValCst_v2;
194 coefs_v2 <= CoefsInitValCst_v2;
195 195
196 --IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
197 -- GENERIC MAP (
198 -- tech => 0,
199 -- Mem_use => use_RAM,
200 -- Sample_SZ => 18,
201 -- Coef_SZ => Coef_SZ,
202 -- Coef_Nb => 25,
203 -- Coef_sel_SZ => 5,
204 -- Cels_count => Cels_count,
205 -- ChanelsCount => ChanelCount)
206 -- PORT MAP (
207 -- rstn => rstn,
208 -- clk => clk,
209 -- virg_pos => 7,
210 -- coefs => coefs_v2,
211 -- sample_in_val => sample_val_delay,
212 -- sample_in => sample_filter_in,
213 -- sample_out_val => sample_filter_v2_out_val,
214 -- sample_out => sample_filter_v2_out);
196 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
197 GENERIC MAP (
198 tech => 0,
199 Mem_use => use_RAM,
200 Sample_SZ => 18,
201 Coef_SZ => Coef_SZ,
202 Coef_Nb => 25,
203 Coef_sel_SZ => 5,
204 Cels_count => Cels_count,
205 ChanelsCount => ChanelCount)
206 PORT MAP (
207 rstn => rstn,
208 clk => clk,
209 virg_pos => 7,
210 coefs => coefs_v2,
211 sample_in_val => sample_val_delay,
212 sample_in => sample_filter_in,
213 sample_out_val => sample_filter_v2_out_val,
214 sample_out => sample_filter_v2_out);
215 215
216 sample_filter_v2_out_val <= sample_val_delay;
216 --sample_filter_v2_out_val <= sample_val_delay;
217 217
218 218 ChanelLoopOut : FOR i IN 0 TO 5 GENERATE
219 219 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
220 --sample_filter_v2_out_s(i, j) <= sample_filter_v2_out(i, j);
221 sample_filter_v2_out_s(i, j) <= sample_filter_in(i, j);
220 sample_filter_v2_out_s(i, j) <= sample_filter_v2_out(i, j);
221 --sample_filter_v2_out_s(i, j) <= sample_filter_in(i, j);
222 222 END GENERATE;
223 223 END GENERATE;
224 224 -----------------------------------------------------------------------------
225 225 -- F0 -- @24.576 kHz
226 226 -----------------------------------------------------------------------------
227 227 Downsampling_f0 : Downsampling
228 228 GENERIC MAP (
229 229 ChanelCount => 6,
230 230 SampleSize => 16,
231 231 DivideParam => 4)
232 232 PORT MAP (
233 233 clk => clk,
234 234 rstn => rstn,
235 235 sample_in_val => sample_filter_v2_out_val,
236 236 sample_in => sample_filter_v2_out_s,
237 237 sample_out_val => sample_f0_val,
238 238 sample_out => sample_f0);
239 239
240 240 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
241 241 sample_f0_wdata_s(I) <= sample_f0(0, I);
242 242 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I);
243 243 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I);
244 244 sample_f0_wdata_s(16*3+I) <= sample_f0(3, I);
245 245 sample_f0_wdata_s(16*4+I) <= sample_f0(4, I);
246 246 sample_f0_wdata_s(16*5+I) <= sample_f0(5, I);
247 247 END GENERATE all_bit_sample_f0;
248 248
249 249 sample_f0_wen <= NOT(sample_f0_val) &
250 250 NOT(sample_f0_val) &
251 251 NOT(sample_f0_val) &
252 252 NOT(sample_f0_val) &
253 253 NOT(sample_f0_val) &
254 254 NOT(sample_f0_val);
255 255
256 256 -----------------------------------------------------------------------------
257 257 -- F1 -- @4096 Hz
258 258 -----------------------------------------------------------------------------
259 259 Downsampling_f1 : Downsampling
260 260 GENERIC MAP (
261 261 ChanelCount => 6,
262 262 SampleSize => 16,
263 263 DivideParam => 6)
264 264 PORT MAP (
265 265 clk => clk,
266 266 rstn => rstn,
267 267 sample_in_val => sample_f0_val ,
268 268 sample_in => sample_f0,
269 269 sample_out_val => sample_f1_val,
270 270 sample_out => sample_f1);
271 271
272 272 sample_f1_wen <= NOT(sample_f1_val) &
273 273 NOT(sample_f1_val) &
274 274 NOT(sample_f1_val) &
275 275 NOT(sample_f1_val) &
276 276 NOT(sample_f1_val) &
277 277 NOT(sample_f1_val);
278 278
279 279 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
280 280 sample_f1_wdata_s(I) <= sample_f1(0, I);
281 281 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I);
282 282 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I);
283 283 sample_f1_wdata_s(16*3+I) <= sample_f1(3, I);
284 284 sample_f1_wdata_s(16*4+I) <= sample_f1(4, I);
285 285 sample_f1_wdata_s(16*5+I) <= sample_f1(5, I);
286 286 END GENERATE all_bit_sample_f1;
287 287
288 288 -----------------------------------------------------------------------------
289 289 -- F2 -- @256 Hz
290 290 -----------------------------------------------------------------------------
291 291 Downsampling_f2 : Downsampling
292 292 GENERIC MAP (
293 293 ChanelCount => 6,
294 294 SampleSize => 16,
295 295 DivideParam => 96)
296 296 PORT MAP (
297 297 clk => clk,
298 298 rstn => rstn,
299 299 sample_in_val => sample_f0_val ,
300 300 sample_in => sample_f0,
301 301 sample_out_val => sample_f2_val,
302 302 sample_out => sample_f2);
303 303
304 304 sample_f2_wen <= NOT(sample_f2_val) &
305 305 NOT(sample_f2_val) &
306 306 NOT(sample_f2_val) &
307 307 NOT(sample_f2_val) &
308 308 NOT(sample_f2_val) &
309 309 NOT(sample_f2_val);
310 310
311 311 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
312 312 sample_f2_wdata_s(I) <= sample_f2(0, I);
313 313 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
314 314 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
315 315 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
316 316 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
317 317 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
318 318 END GENERATE all_bit_sample_f2;
319 319
320 320 -----------------------------------------------------------------------------
321 321 -- F3 -- @16 Hz
322 322 -----------------------------------------------------------------------------
323 323 Downsampling_f3 : Downsampling
324 324 GENERIC MAP (
325 325 ChanelCount => 6,
326 326 SampleSize => 16,
327 327 DivideParam => 256)
328 328 PORT MAP (
329 329 clk => clk,
330 330 rstn => rstn,
331 331 sample_in_val => sample_f1_val ,
332 332 sample_in => sample_f1,
333 333 sample_out_val => sample_f3_val,
334 334 sample_out => sample_f3);
335 335
336 336 sample_f3_wen <= (NOT sample_f3_val) &
337 337 (NOT sample_f3_val) &
338 338 (NOT sample_f3_val) &
339 339 (NOT sample_f3_val) &
340 340 (NOT sample_f3_val) &
341 341 (NOT sample_f3_val);
342 342
343 343 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
344 344 sample_f3_wdata_s(I) <= sample_f3(0, I);
345 345 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
346 346 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
347 347 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
348 348 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
349 349 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
350 350 END GENERATE all_bit_sample_f3;
351 351
352 352 lpp_waveform_1 : lpp_waveform
353 353 GENERIC MAP (
354 354 hindex => hindex,
355 355 tech => tech,
356 356 data_size => 160,
357 357 nb_burst_available_size => nb_burst_available_size,
358 358 nb_snapshot_param_size => nb_snapshot_param_size,
359 359 delta_snapshot_size => delta_snapshot_size,
360 360 delta_f2_f0_size => delta_f2_f0_size,
361 361 delta_f2_f1_size => delta_f2_f1_size)
362 362 PORT MAP (
363 363 clk => clk,
364 364 rstn => rstn,
365 365
366 366 AHB_Master_In => AHB_Master_In,
367 367 AHB_Master_Out => AHB_Master_Out,
368 368
369 369 coarse_time_0 => coarse_time_0, -- IN
370 370 delta_snapshot => delta_snapshot, -- IN
371 371 delta_f2_f1 => delta_f2_f1, -- IN
372 372 delta_f2_f0 => delta_f2_f0, -- IN
373 373 enable_f0 => enable_f0, -- IN
374 374 enable_f1 => enable_f1, -- IN
375 375 enable_f2 => enable_f2, -- IN
376 376 enable_f3 => enable_f3, -- IN
377 377 burst_f0 => burst_f0, -- IN
378 378 burst_f1 => burst_f1, -- IN
379 379 burst_f2 => burst_f2, -- IN
380 380 nb_burst_available => nb_burst_available,
381 381 nb_snapshot_param => nb_snapshot_param,
382 382 status_full => status_full,
383 383 status_full_ack => status_full_ack, -- IN
384 384 status_full_err => status_full_err,
385 385 status_new_err => status_new_err,
386 386
387 387 addr_data_f0 => addr_data_f0, -- IN
388 388 addr_data_f1 => addr_data_f1, -- IN
389 389 addr_data_f2 => addr_data_f2, -- IN
390 390 addr_data_f3 => addr_data_f3, -- IN
391 391
392 392 data_f0_in => data_f0_in_valid,
393 393 data_f1_in => data_f1_in_valid,
394 394 data_f2_in => data_f2_in_valid,
395 395 data_f3_in => data_f3_in_valid,
396 396 data_f0_in_valid => sample_f0_val,
397 397 data_f1_in_valid => sample_f1_val,
398 398 data_f2_in_valid => sample_f2_val,
399 399 data_f3_in_valid => sample_f3_val);
400 400
401 401 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
402 402 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
403 403 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
404 404 data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s;
405 405
406 406 sample_f0_wdata <= sample_f0_wdata_s;
407 407 sample_f1_wdata <= sample_f1_wdata_s;
408 408 sample_f2_wdata <= sample_f2_wdata_s;
409 409 sample_f3_wdata <= sample_f3_wdata_s;
410 410
411 411 END tb;
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