@@ -505,7 +505,7 BEGIN -- beh | |||
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505 | 505 | pirq_ms => 6, |
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506 | 506 | pirq_wfp => 14, |
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507 | 507 | hindex => 2, |
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508 |
top_lfr_version => X"00012 |
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508 | top_lfr_version => X"000125") -- aa.bb.cc version | |
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509 | 509 | PORT MAP ( |
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510 | 510 | clk => clk_25, |
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511 | 511 | rstn => LFR_rstn, |
@@ -342,6 +342,11 BEGIN | |||
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342 | 342 | wfp_ready_buffer => wfp_ready_buffer,-- TODO |
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343 | 343 | wfp_buffer_time => wfp_buffer_time,-- TODO |
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344 | 344 | wfp_error_buffer_full => wfp_error_buffer_full, -- TODO |
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345 | ------------------------------------------------------------------------- | |
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346 | sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16), | |
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347 | sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16), | |
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348 | sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16), | |
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349 | sample_f3_valid => sample_f3_val, | |
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345 | 350 | debug_vector => apb_reg_debug_vector |
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346 | 351 | ); |
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347 | 352 |
@@ -139,6 +139,11 ENTITY lpp_lfr_apbreg IS | |||
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139 | 139 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
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140 | 140 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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141 | 141 | --------------------------------------------------------------------------- |
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142 | sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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143 | sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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144 | sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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145 | sample_f3_valid : IN STD_LOGIC; | |
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146 | --------------------------------------------------------------------------- | |
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142 | 147 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) |
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143 | 148 | |
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144 | 149 | ); |
@@ -269,6 +274,10 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
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269 | 274 | |
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270 | 275 | SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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271 | 276 | |
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277 | SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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278 | SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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279 | SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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280 | ||
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272 | 281 | BEGIN -- beh |
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273 | 282 | |
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274 | 283 | debug_vector(0) <= error_buffer_full; |
@@ -330,6 +339,23 BEGIN -- beh | |||
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330 | 339 | length_matrix_f1 <= reg_sp.length_matrix; |
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331 | 340 | length_matrix_f2 <= reg_sp.length_matrix; |
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332 | 341 | wfp_length_buffer <= reg_wp.length_buffer; |
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342 | ||
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343 | ||
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344 | ||
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345 | PROCESS (HCLK, HRESETn) | |
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346 | BEGIN -- PROCESS | |
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347 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
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348 | sample_f3_v_reg <= (OTHERS => '0'); | |
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349 | sample_f3_e1_reg <= (OTHERS => '0'); | |
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350 | sample_f3_e2_reg <= (OTHERS => '0'); | |
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351 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
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352 | IF sample_f3_valid = '1' THEN | |
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353 | sample_f3_v_reg <= sample_f3_v; | |
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354 | sample_f3_e1_reg <= sample_f3_e1; | |
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355 | sample_f3_e2_reg <= sample_f3_e2; | |
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356 | END IF; | |
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357 | END IF; | |
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358 | END PROCESS; | |
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333 | 359 | |
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334 | 360 | |
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335 | 361 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
@@ -542,7 +568,14 BEGIN -- beh | |||
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542 | 568 | WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7); |
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543 | 569 | WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32); |
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544 | 570 | |
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545 |
WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; |
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571 | WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; | |
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572 | ||
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573 | WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg; | |
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574 | prdata(31 DOWNTO 16) <= (OTHERS => '0'); | |
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575 | WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg; | |
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576 | prdata(31 DOWNTO 16) <= (OTHERS => '0'); | |
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577 | WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg; | |
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578 | prdata(31 DOWNTO 16) <= (OTHERS => '0'); | |
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546 | 579 | --------------------------------------------------------------------- |
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547 | 580 | WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); |
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548 | 581 | WHEN OTHERS => NULL; |
@@ -80,7 +80,11 PACKAGE lpp_lfr_apbreg_pkg IS | |||
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80 | 80 | CONSTANT ADDR_LFR_WP_F3_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110110"; |
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81 | 81 | CONSTANT ADDR_LFR_WP_F3_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110111"; |
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82 | 82 | |
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83 |
CONSTANT ADDR_LFR_WP_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111000"; |
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83 | CONSTANT ADDR_LFR_WP_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111000"; | |
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84 | ||
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85 | CONSTANT ADDR_LFR_WP_F3_V : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111001"; | |
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86 | CONSTANT ADDR_LFR_WP_F3_E1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111010"; | |
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87 | CONSTANT ADDR_LFR_WP_F3_E2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111011"; | |
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84 | 88 | ----------------------------------------------------------------------------- |
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85 | 89 | -- LFR |
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86 | 90 | ----------------------------------------------------------------------------- |
@@ -319,6 +319,10 PACKAGE lpp_lfr_pkg IS | |||
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319 | 319 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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320 | 320 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
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321 | 321 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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322 | sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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323 | sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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324 | sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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325 | sample_f3_valid : IN STD_LOGIC; | |
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322 | 326 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); |
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323 | 327 | END COMPONENT; |
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324 | 328 |
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