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1 | ################################################################################ | |
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2 | # SDC WRITER VERSION "3.1"; | |
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3 | # DESIGN "LFR_EQM"; | |
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4 | # Timing constraints scenario: "Primary"; | |
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5 | # DATE "Fri Apr 24 16:02:16 2015"; | |
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6 | # VENDOR "Actel"; | |
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7 | # PROGRAM "Actel Designer Software Release v9.1 SP5"; | |
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8 | # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. | |
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9 | ################################################################################ | |
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10 | ||
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11 | ||
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12 | set sdc_version 1.7 | |
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13 | ||
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14 | ||
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15 | ######## Clock Constraints ######## | |
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16 | ||
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17 | create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } | |
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18 | ||
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19 | create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } | |
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20 | ||
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21 | create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } | |
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22 | ||
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23 | create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } | |
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24 | ||
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25 | create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } | |
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26 | ||
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27 | create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } | |
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28 | ||
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29 | ||
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30 | ||
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31 | ######## Generated Clock Constraints ######## | |
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32 | ||
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33 | ||
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34 | ||
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35 | ######## Clock Source Latency Constraints ######### | |
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36 | ||
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37 | ||
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38 | ||
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39 | ######## Input Delay Constraints ######## | |
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40 | ||
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41 | set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |
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42 | set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ | |
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43 | data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ | |
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44 | data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ | |
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45 | data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] | |
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46 | set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ | |
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47 | data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ | |
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48 | data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ | |
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49 | data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] | |
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50 | ||
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51 | set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] | |
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52 | set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] | |
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53 | set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] | |
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54 | ||
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55 | ||
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56 | ||
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57 | ######## Output Delay Constraints ######## | |
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58 | ||
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59 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |
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60 | set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ | |
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61 | data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ | |
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62 | data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ | |
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63 | data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |
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64 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ | |
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65 | data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ | |
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66 | data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ | |
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67 | data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |
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68 | ||
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69 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] | |
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70 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ | |
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71 | address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ | |
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72 | address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ | |
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73 | address[7] address[8] address[9] }] | |
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74 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ | |
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75 | address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ | |
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76 | address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ | |
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77 | address[7] address[8] address[9] }] | |
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78 | ||
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79 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] | |
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80 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] | |
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81 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] | |
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82 | ||
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83 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] | |
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84 | set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] | |
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85 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] | |
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86 | ||
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87 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] | |
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88 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] | |
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89 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] | |
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90 | ||
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91 | ||
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92 | ||
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93 | ######## Delay Constraints ######## | |
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94 | ||
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95 | set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ | |
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96 | nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ | |
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97 | {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] | |
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98 | ||
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99 | set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ | |
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100 | nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ | |
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101 | {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] | |
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102 | ||
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103 | ||
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104 | ||
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105 | ######## Delay Constraints ######## | |
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106 | ||
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107 | ||
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108 | ||
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109 | ######## Multicycle Constraints ######## | |
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110 | ||
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111 | ||
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112 | ||
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113 | ######## False Path Constraints ######## | |
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114 | ||
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115 | ||
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116 | ||
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117 | ######## Output load Constraints ######## | |
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118 | ||
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119 | ||
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120 | ||
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121 | ######## Disable Timing Constraints ######### | |
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122 | ||
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123 | ||
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124 | ||
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125 | ######## Clock Uncertainty Constraints ######### | |
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126 | ||
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127 | ||
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128 |
@@ -1,39 +1,46 | |||
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1 | 1 | # Top Level Design Parameters |
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2 | 2 | |
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3 | 3 | # Clocks |
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4 | 4 | |
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5 | 5 | create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz |
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6 | 6 | create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q |
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7 | 7 | |
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8 | 8 | #create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q} |
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9 | 9 | |
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10 | 10 | create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz |
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11 | 11 | create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q |
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12 | 12 | #create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} |
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13 | 13 | |
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14 | 14 | |
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15 | 15 | # False Paths Between Clocks |
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16 | 16 | |
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17 | 17 | |
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18 | 18 | # False Path Constraints |
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19 | 19 | |
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20 | 20 | |
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21 | 21 | # Maximum Delay Constraints |
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22 | 22 | |
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23 | 23 | # Multicycle Constraints |
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24 | 24 | |
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25 | 25 | |
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26 | 26 | # Virtual Clocks |
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27 | 27 | # Output Load Constraints |
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28 | 28 | # Driving Cell Constraints |
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29 | 29 | # Wire Loads |
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30 | 30 | # set_wire_load_mode top |
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31 | 31 | |
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32 | 32 | # Other Constraints |
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33 | 33 | |
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34 | 34 | |
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35 | 35 | ## GRSPW constraints |
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36 | 36 | create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y} |
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37 | 37 | create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y} |
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38 | 38 | set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y] |
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39 | 39 | set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y] |
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40 | ||
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41 | ## set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout | |
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42 | ## set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout | |
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43 | ## set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout | |
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44 | ## set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout ## > max 20ns | |
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45 | ## set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout | |
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46 | ## set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout |
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