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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

ICI4 EGSE now working, need some more cleaning.
Alexis Jeandet -
r219:df1aff8cd31b alexis
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1 -- DC_GATE_GEN.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6
7
8
9
10
11
12
13 entity DC_GATE_GEN is
14 generic(WordCnt : integer := 144);
15 port
16 (
17 clk : in std_logic;
18 Wcount : in integer range 0 to WordCnt-1;
19 Gate : out std_logic
20 );
21 end entity;
22
23
24
25
26 architecture ar_DC_GATE_GEN of DC_GATE_GEN is
27 begin
28 process(clk)
29 begin
30 if clk'event and clk ='0' then
31 case Wcount is
32 when 48 =>
33 gate <= '1';
34 when 49 =>
35 gate <= '1';
36
37 when 50 =>
38 gate <= '1';
39 when 51 =>
40 gate <= '1';
41
42 when 52 =>
43 gate <= '1';
44 when 53 =>
45 gate <= '1';
46
47
48 when others =>
49 gate <= '0';
50 end case;
51 end if;
52 end process;
53 end architecture; No newline at end of file
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1 -- ICI_EGSE_PROTOCOL.vhd
2 -- ICI_EGSE_PROTOCOL.vhd
3 library IEEE;
4 use IEEE.std_logic_1164.all;
5 use IEEE.numeric_std.all;
6
7 entity ICI_EGSE_PROTOCOL is
8 generic(WordSize : integer := 8;WordCnt : integer :=144;MinFCount : integer := 64;Simu : integer :=0);
9 port(
10 clk : in std_logic;
11 reset : in std_logic;
12 WEN : in std_logic;
13 WordCnt_in : in integer range 0 to WordCnt-1;
14 MinfCnt_in : in integer range 0 to MinFCount-1;
15 DATAIN : in std_logic_vector (WordSize-1 downto 0);
16 FULL : in std_logic;
17 WR : out std_logic;
18 DATAOUT : out std_logic_vector (WordSize-1 downto 0)
19 );
20 end ICI_EGSE_PROTOCOL;
21
22
23 architecture ar_ICI_EGSE_PROTOCOL of ICI_EGSE_PROTOCOL is
24
25 type DATA_pipe_t is array(NATURAL RANGE <>) of std_logic_vector (WordSize-1 downto 0);
26
27 signal DATA_pipe : DATA_pipe_t(10 downto 0);
28 signal WR_pipe : std_logic_vector(10 downto 0);
29 signal headerSended : std_logic := '0';
30
31
32 begin
33
34 WR <= WR_pipe(0);
35
36 DATAOUT <= DATA_pipe(0);
37
38
39 process(reset,clk)
40 begin
41 if reset = '0' then
42 WR_pipe(10 downto 0) <= (others => '1');
43 rstloop: for i in 0 to 10 loop
44 DATA_pipe(i) <= X"00";
45 end loop;
46 headerSended <= '0';
47 elsif clk'event and clk ='1' then
48 if WordCnt_in = 1 and headerSended = '0' then
49 WR_pipe(4 downto 1) <= (others => '0');
50 WR_pipe(1) <= '0';
51 WR_pipe(3) <= '0';
52 WR_pipe(5) <= '0';
53 WR_pipe(7) <= '0';
54 WR_pipe(9) <= '0';
55 DATA_pipe(1) <= X"0F";
56 DATA_pipe(3) <= X"5a";
57 DATA_pipe(5) <= X"a5";
58 DATA_pipe(7) <= X"F0";
59 DATA_pipe(9) <= std_logic_vector(TO_UNSIGNED(MinfCnt_in,WordSize));
60 WR_pipe(0) <= '1';
61 WR_pipe(2) <= '1';
62 WR_pipe(4) <= '1';
63 WR_pipe(6) <= '1';
64 WR_pipe(8) <= '1';
65 WR_pipe(10) <= '1';
66 DATA_pipe(0) <= X"00";
67 DATA_pipe(2) <= X"00";
68 DATA_pipe(4) <= X"00";
69 DATA_pipe(6) <= X"00";
70 DATA_pipe(10) <= X"00";
71 headerSended <= '1';
72 elsif (FULL = '0') then
73 if WordCnt_in /= 1 then
74 headerSended <= '0';
75 end if;
76 DATA_pipe(0) <= DATA_pipe(1);
77 DATA_pipe(1) <= DATA_pipe(2);
78 DATA_pipe(2) <= DATA_pipe(3);
79 DATA_pipe(3) <= DATA_pipe(4);
80 DATA_pipe(4) <= DATA_pipe(5);
81 DATA_pipe(5) <= DATA_pipe(6);
82 DATA_pipe(6) <= DATA_pipe(7);
83 DATA_pipe(7) <= DATA_pipe(8);
84 DATA_pipe(8) <= DATA_pipe(9);
85 DATA_pipe(9) <= DATA_pipe(10);
86 DATA_pipe(10) <= DATAIN;
87 WR_pipe(10 downto 0) <= WEN & WR_pipe(10 downto 1);
88 else
89 WR_pipe(0) <= '1';
90 if WordCnt_in /= 1 then
91 headerSended <= '0';
92 end if;
93 end if;
94 end if;
95 end process;
96
97
98 end ar_ICI_EGSE_PROTOCOL; No newline at end of file
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1 -- ICI_EGSE_PROTOCOL.vhd
2 -- ICI_EGSE_PROTOCOL.vhd
3 library IEEE;
4 use IEEE.std_logic_1164.all;
5 use IEEE.numeric_std.all;
6
7 entity ICI_EGSE_PROTOCOL2 is
8 generic(WordSize : integer := 8;Simu : integer :=0);
9 port(
10 clk : in std_logic;
11 reset : in std_logic;
12 WEN : in std_logic;
13 MinF : in std_logic;
14 DATAIN : in std_logic_vector (WordSize-1 downto 0);
15 FULL : in std_logic;
16 WR : out std_logic;
17 DATAOUT : out std_logic_vector (WordSize-1 downto 0)
18 );
19 end ICI_EGSE_PROTOCOL2;
20
21
22 architecture ar_ICI_EGSE_PROTOCOL2 of ICI_EGSE_PROTOCOL2 is
23
24 type state_t is (idle,forward,header1,header2,header3,header4);
25 signal MinFReg : std_logic;
26 signal state : state_t;
27
28 begin
29
30 process(reset,clk)
31 begin
32 if reset = '0' then
33 MinFReg <= '1';
34 state <= idle;
35 DATAOUT <= X"00";
36 WR <= '1';
37 elsif clk'event and clk ='1' then
38 MinFReg <= MinF;
39 case state is
40 when idle =>
41 DATAOUT <= X"00";
42 WR <= '1';
43 state <= forward;
44 when forward =>
45 DATAOUT <= DATAIN;
46 WR <= WEN;
47 if MinFReg = '0' and MinF = '1' then
48 state <= header1;
49 end if;
50 when header1 =>
51 if FULL = '0' then
52 WR <= '0';
53 DATAOUT <= X"5a";
54 state <= header2;
55 else
56 WR <= '1';
57 end if;
58 when header2 =>
59 if FULL = '0' then
60 WR <= '0';
61 DATAOUT <= X"F0";
62 state <= header3;
63 else
64 WR <= '1';
65 end if;
66 when header3 =>
67 if FULL = '0' then
68 WR <= '0';
69 DATAOUT <= X"0F";
70 state <= header4;
71 else
72 WR <= '1';
73 end if;
74 when header4 =>
75 if FULL = '0' then
76 WR <= '0';
77 DATAOUT <= X"a5";
78 state <= forward;
79 else
80 WR <= '1';
81 end if;
82 end case;
83 end if;
84 end process;
85
86
87 end ar_ICI_EGSE_PROTOCOL2; No newline at end of file
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1 -- LF_GATE_GEN.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6
7
8
9
10
11
12
13 entity LF_GATE_GEN is
14 generic(WordCnt : integer := 144);
15 port
16 (
17 clk : in std_logic;
18 Wcount : in integer range 0 to WordCnt-1;
19 Gate : out std_logic
20 );
21 end entity;
22
23
24
25
26 architecture ar_LF_GATE_GEN of LF_GATE_GEN is
27 begin
28 process(clk)
29 begin
30 if clk'event and clk ='0' then
31 case Wcount is
32 when 6 =>
33 gate <= '1';
34 when 7 =>
35 gate <= '1';
36 when 8 =>
37 gate <= '1';
38 when 9 =>
39 gate <= '1';
40 when 10 =>
41 gate <= '1';
42 when 11 =>
43 gate <= '1';
44
45 when 30 =>
46 gate <= '1';
47 when 31 =>
48 gate <= '1';
49 when 32 =>
50 gate <= '1';
51 when 33 =>
52 gate <= '1';
53 when 34 =>
54 gate <= '1';
55 when 35 =>
56 gate <= '1';
57
58 when 54 =>
59 gate <= '1';
60 when 55 =>
61 gate <= '1';
62 when 56 =>
63 gate <= '1';
64 when 57 =>
65 gate <= '1';
66 when 58 =>
67 gate <= '1';
68 when 59 =>
69 gate <= '1';
70
71 when 78 =>
72 gate <= '1';
73 when 79 =>
74 gate <= '1';
75 when 80 =>
76 gate <= '1';
77 when 81 =>
78 gate <= '1';
79 when 82 =>
80 gate <= '1';
81 when 83 =>
82 gate <= '1';
83
84 when 102 =>
85 gate <= '1';
86 when 103 =>
87 gate <= '1';
88 when 104 =>
89 gate <= '1';
90 when 105 =>
91 gate <= '1';
92 when 106 =>
93 gate <= '1';
94 when 107 =>
95 gate <= '1';
96
97 when 126 =>
98 gate <= '1';
99 when 127 =>
100 gate <= '1';
101 when 128 =>
102 gate <= '1';
103 when 129 =>
104 gate <= '1';
105 when 130 =>
106 gate <= '1';
107 when 131 =>
108 gate <= '1';
109
110
111 when others =>
112 gate <= '0';
113 end case;
114 end if;
115 end process;
116 end architecture; No newline at end of file
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1 -- MajF_Gen.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6
7
8 entity MajF_Gen is
9 generic(WordCnt : integer :=144;MinFCount : integer := 64);
10 port(
11 clk : in std_logic;
12 reset : in std_logic;
13 WordCnt_in : in integer range 0 to WordCnt-1;
14 MinfCnt_in : in integer range 0 to MinFCount-1;
15 WordClk : in std_logic;
16 MajF_Clk : out std_logic
17 );
18 end entity;
19
20
21
22
23
24
25 architecture arMajF_Gen of MajF_Gen is
26
27 begin
28
29 process(clk)
30 begin
31 if reset = '0' then
32 MajF_Clk <= '0';
33 elsif clk'event and clk = '0' then
34 if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' then
35 MajF_Clk <= '1';
36 else
37 MajF_Clk <= '0';
38 end if;
39 end if;
40 end process;
41
42 end architecture; No newline at end of file
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1 -- MinF_Gen.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6
7
8 entity MinF_Gen is
9 generic(WordCnt : integer :=144);
10 port(
11 clk : in std_logic;
12 reset : in std_logic;
13 WordCnt_in : in integer range 0 to WordCnt-1;
14 WordClk : in std_logic;
15 MinF_Clk : out std_logic
16 );
17 end entity;
18
19
20
21
22
23
24 architecture arMinF_Gen of MinF_Gen is
25
26 begin
27
28 process(clk)
29 begin
30 if reset = '0' then
31 MinF_Clk <= '0';
32 elsif clk'event and clk = '0' then
33 if WordCnt_in = 0 and WordClk = '1' then
34 MinF_Clk <= '1';
35 else
36 MinF_Clk <= '0';
37 end if;
38 end if;
39 end process;
40
41 end architecture; No newline at end of file
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1 -- Serial_driver.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6
7
8
9
10 entity Serial_driver2 is
11 generic(Sz : integer := 8);
12 port(
13 Sclk : in std_logic;
14 rstn : in std_logic;
15 Sdata : in std_logic;
16 Gate : in std_logic;
17 NwDat : out std_logic;
18 Data : out std_logic_vector(Sz-1 downto 0)
19 );
20 end entity;
21
22
23
24 architecture arSerial_driver2 of Serial_driver2 is
25 signal DataR : std_logic_vector(Sz-1 downto 0);
26 signal DataCnt : integer range 0 to Sz-1 :=0;
27 signal DataCntR : integer range 0 to Sz-1 :=0;
28 begin
29
30
31 process(rstn,Sclk)
32 begin
33 if rstn = '0' then
34 DataR <= (others=>'0');
35 NwDat <= '0';
36 elsif Sclk'event and Sclk ='1' then
37 DataCntR <= DataCnt;
38 if DataCntR = Sz-1 then
39 NwDat <= '1';
40 Data <= DataR;
41 else
42 NwDat <= '0';
43 end if;
44 if Gate ='1' then
45 DataR <= DataR(Sz-2 downto 0) & Sdata;
46 if DataCnt = Sz-1 then
47 DataCnt <= 0;
48 else
49 DataCnt <= DataCnt +1;
50 end if;
51 else
52 DataCnt <= 0;
53 end if;
54 end if;
55 end process;
56
57
58 end architecture;
59
60
61
62
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1 -- LF_GATE_GEN.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6
7
8
9
10
11
12
13 entity testbench is
14 port
15 (
16 );
17 end entity;
18
19
20
21
22 architecture ar_testbench of testbench is
23 signal Clock : std_logic;
24 signal reset : std_logic;
25 signal DataRTX : std_logic;
26 signal DataRTX_echo : std_logic;
27 signal SCLK : std_logic;
28 signal Gate : std_logic;
29 signal Major_Frame : std_logic;
30 signal Minor_Frame : std_logic;
31 signal if_clk : STD_LOGIC;
32 signal flagb : STD_LOGIC;
33 signal slwr : STD_LOGIC;
34 signal slrd : std_logic;
35 signal pktend : STD_LOGIC;
36 signal sloe : STD_LOGIC;
37 signal fdbusw : std_logic_vector (7 downto 0);
38 signal fifoadr : std_logic_vector (1 downto 0);
39
40 begin
41 EGSE: entity TOP_EGSE2
42 generic map(8,144,64,1)
43 port map(Clock,
44 reset,
45 DataRTX,
46 DataRTX_echo,
47 SCLK,
48 Gate,
49 Major_Frame,
50 Minor_Frame,
51 if_clk,
52 flagb,
53 slwr,
54 slrd,
55 pktend,
56 sloe,
57 fdbusw,
58 fifoadr
59 );
60
61 end architecture; No newline at end of file
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@@ -1,39 +1,47
1 1 #
2 2 # IO banks setting
3 3 #
4 4
5 5 set_iobank Bank3 -vcci 3.30 -fixed no
6 6 set_iobank Bank2 -vcci 3.30 -fixed no
7 7 set_iobank Bank1 -vcci 3.30 -fixed no
8 8 set_iobank Bank0 -vcci 3.30 -fixed no
9 9
10 10 #
11 11 # I/O constraints
12 12 #
13 13
14 14 set_io Clock -iostd LVTTL -REGISTER No -RES_PULL None -pinname 151 -fixed yes
15 15 set_io DataRTX -iostd LVTTL -REGISTER No -RES_PULL None -pinname 190 -fixed yes
16 set_io DataRTX_echo -iostd LVTTL -REGISTER No -RES_PULL None -pinname 42 -fixed yes
16 17 set_io Gate -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 189 -fixed yes
17 18 set_io Major_Frame -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 185 -fixed yes
18 19 set_io Minor_Frame -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 183 -fixed yes
19 20 set_io SCLK -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 181 -fixed yes
20 21 #set_io Sdatabis -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 182 -fixed yes
21 22 set_io fdbusw\[0\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 135 -fixed yes
22 23 set_io fdbusw\[1\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 136 -fixed yes
23 24 set_io fdbusw\[2\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 137 -fixed yes
24 25 set_io fdbusw\[3\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 138 -fixed yes
25 26 set_io fdbusw\[4\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 139 -fixed yes
26 27 set_io fdbusw\[5\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 143 -fixed yes
27 28 set_io fdbusw\[6\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 144 -fixed yes
28 29 set_io fdbusw\[7\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 145 -fixed yes
29 30 set_io fifoadr\[0\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 159 -fixed yes
30 31 set_io fifoadr\[1\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 160 -fixed yes
31 32 set_io flagb -iostd LVTTL -REGISTER No -RES_PULL None -pinname 148 -fixed yes
32 33 #set_io gatebis -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 179 -fixed yes
33 34 set_io if_clk -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 152 -fixed yes
34 35 set_io pktend -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 161 -fixed yes
35 36 set_io reset -iostd LVTTL -REGISTER No -RES_PULL None -pinname 177 -fixed yes
36 37 #set_io sclkbis -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 180 -fixed yes
37 38 set_io sloe -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 153 -fixed yes
38 39 set_io slrd -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 167 -fixed yes
39 set_io slwr -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 166 -fixed yes No newline at end of file
40 set_io slwr -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 166 -fixed yes
41 set_io BUS0 -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 48 -fixed yes
42 set_io BUS12 -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 9 -fixed yes
43 set_io BUS13 -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 7 -fixed yes
44 set_io BUS14 -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 5 -fixed yes
45
46
47
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@@ -1,18 +1,18
1 1 TECHNOLOGY=PROASIC3
2 2 PACKAGE=\"\"
3 3 SPEED=Std
4 4 SYNFREQ=50
5 5
6 6 PART=A3PE1500
7 DESIGNER_PACKAGE=PQFP
7 DESIGNER_PACKAGE=PQFF
8 8 DESIGNER_PINS=208
9 9 DESIGNER_VOLTAGE=COM
10 10 DESIGNER_TEMP=COM
11 11
12 12 MANUFACTURER=Actel
13 13 MGCPART=$(PART)
14 MGCTECHNOLOGY=PROASIC3
15 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
16 LIBERO_DIE=IT14X14M4LDP
17 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
14 MGCTECHNOLOGY=ProASIC3E
15 MGCPACKAGE= {$(DESIGNER_PINS)$(DESIGNER_PACKAGE)}
16 LIBERO_DIE=IT10X10M3
17 LIBERO_PACKAGE=pq$(DESIGNER_PINS)
18 18
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@@ -1,59 +1,61
1 1 # Synplicity, Inc. constraint file
2 2 # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
3 3 # Written on Wed Aug 1 19:29:24 2007
4 4 # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
5 5
6 6 #
7 7 # Collections
8 8 #
9 9
10 10 #
11 11 # Clocks
12 12 #
13 define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5
13 define_clock {clk} -name {clk} -freq 48 -clockgroup default_clkgroup -route 5
14
15 define_clock {SCLKint} -name {SCLKint} -freq 3.3 -clockgroup default_clkgroup -route 5
14 16
15 17 #
16 18 # Clock to Clock
17 19 #
18 20
19 21 #
20 22 # Inputs/Outputs
21 23 #
22 24 define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
23 25 define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
24 26
25 27
26 28 #
27 29 # Registers
28 30 #
29 31
30 32 #
31 33 # Multicycle Path
32 34 #
33 35
34 36 #
35 37 # False Path
36 38 #
37 39
38 40 #
39 41 # Path Delay
40 42 #
41 43
42 44 #
43 45 # Attributes
44 46 #
45 47 define_global_attribute syn_useioff {1}
46 48 define_global_attribute -disable syn_netlist_hierarchy {0}
47 49 define_attribute {etx_clk} syn_noclockbuf {1}
48 50
49 51 #
50 52 # I/O standards
51 53 #
52 54
53 55 #
54 56 # Compile Points
55 57 #
56 58
57 59 #
58 60 # Other Constraints
59 61 #
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@@ -1,158 +1,282
1 -- TOP_GSE.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
1 -- TOP_GSE.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 4 use IEEE.numeric_std.all;
5 5 library lpp;
6 6 use lpp.lpp_usb.all;
7 use lpp.Rocket_PCM_Encoder.all;
8 use lpp.iir_filter.all;
9 use lpp.general_purpose.all;
7 10 library techmap;
8 use techmap.gencomp.all;
9
10 entity TOP_EGSE2 is
11 generic(WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64;Simu : integer :=0);
12 port(
13 Clock : in std_logic;
14 reset : in std_logic;
15 DataRTX : in std_logic;
16 DataRTX_echo : out std_logic;
17 SCLK : out std_logic;
18 Gate : out std_logic;
19 Major_Frame : out std_logic;
20 Minor_Frame : out std_logic;
21 if_clk : out STD_LOGIC;
22 flagb : in STD_LOGIC;
23 slwr : out STD_LOGIC;
24 slrd : out std_logic;
25 pktend : out STD_LOGIC;
26 sloe : out STD_LOGIC;
27 fdbusw : out std_logic_vector (7 downto 0);
28 fifoadr : out std_logic_vector (1 downto 0)
29 );
30 end TOP_EGSE2;
31
32
33
34 architecture ar_TOP_EGSE2 of TOP_EGSE2 is
35
36 component CLKINT
37 port( A : in std_logic := 'U';
38 Y : out std_logic
39 );
40 end component;
41
42 signal clk : std_logic;
43 signal sclkint : std_logic;
44 signal RaZ : std_logic;
45 signal rstn : std_logic;
46 signal WordCount : integer range 0 to WordCnt-1;
47 signal WordClk : std_logic;
48 signal MinFCnt : integer range 0 to MinFCount-1;
49 signal MinF : std_logic;
50 signal MinFclk : std_logic;
51 signal MajF : std_logic;
52 signal GateLF : std_logic;
53 signal GateHF : std_logic;
54 signal GateDC : std_logic;
55 signal Gateint : std_logic;
56 signal GateR : std_logic;
57 signal NwDat : std_logic;
58 signal DATA : std_logic_vector(WordSize-1 downto 0);
59
60 Signal FIFODATin : std_logic_vector(7 downto 0);
61 Signal FIFODATout : std_logic_vector(7 downto 0);
62
63 Signal USB_DATA : std_logic_vector(7 downto 0);
64 Signal FIFOwe,FIFOre,FIFOfull : std_logic;
65 Signal USBwe,USBfull,USBempty : std_logic;
66
67 Signal clk80 : std_logic;
68
69
70
71 begin
11 use techmap.gencomp.all;
12 use work.config.all;
13
14
15 entity TOP_EGSE2 is
16 generic(WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64;Simu : integer :=0);
17 port(
18 Clock : in std_logic;
19 reset : in std_logic;
20 DataRTX : in std_logic;
21 DataRTX_echo : out std_logic;
22 SCLK : out std_logic;
23 Gate : out std_logic;
24 Major_Frame : out std_logic;
25 Minor_Frame : out std_logic;
26 if_clk : out STD_LOGIC;
27 flagb : in STD_LOGIC;
28 slwr : out STD_LOGIC;
29 slrd : out std_logic;
30 pktend : out STD_LOGIC;
31 sloe : out STD_LOGIC;
32 fdbusw : out std_logic_vector (7 downto 0);
33 fifoadr : out std_logic_vector (1 downto 0);
34 BUS0 : out std_logic;
35 BUS12 : out std_logic;
36 BUS13 : out std_logic;
37 BUS14 : out std_logic
38 );
39 end TOP_EGSE2;
40
41
42
43 architecture ar_TOP_EGSE2 of TOP_EGSE2 is
44
45 component CLKINT
46 port( A : in std_logic := 'U';
47 Y : out std_logic
48 );
49 end component;
50
51 signal clk : std_logic;
52 signal clk_48 : std_logic;
53 signal sclkint : std_logic;
54 signal RaZ : std_logic;
55 signal rstn : std_logic;
56 signal WordCount : integer range 0 to WordCnt-1;
57 signal WordClk : std_logic;
58 signal MinFCnt : integer range 0 to MinFCount-1;
59 signal MinF : std_logic;
60 signal MinFclk : std_logic;
61 signal MajF : std_logic;
62 signal GateLF : std_logic;
63 signal GateHF : std_logic;
64 signal GateDC : std_logic;
65 signal GateR : std_logic;
66 signal Gateint : std_logic;
67 signal NwDat : std_logic;
68 signal NwDatR : std_logic;
69 signal DATA : std_logic_vector(WordSize-1 downto 0);
70 signal MinFVector : std_logic_vector(WordSize-1 downto 0);
71
72 Signal PROTO_WEN : std_logic;
73 Signal PROTO_DATAIN : std_logic_vector (WordSize-1 downto 0);
74 Signal PROTO_FULL : std_logic;
75 Signal PROTO_WR : std_logic;
76 Signal PROTO_DATAOUT : std_logic_vector (WordSize-1 downto 0);
77
78 Signal clk80 : std_logic;
79
80
81
82 begin
83
84
85 DataRTX_echo <= DataRTX; --P48
86
87
88 ck_int0 : CLKINT
89 port map(Clock,clk_48);
90
91 DEFPLL: IF simu = 0 generate
92 PLL : entity work.PLL0
93 port map(
94 POWERDOWN => '1',
95 CLKA => clk_48,
96 LOCK => RaZ,
97 GLA => clk80,
98 GLB => clk --33.3MHz
99 );
100 end generate;
101
102
103 SIMPLL: IF simu = 1 generate
104 PLL : entity work.PLL0Sim
105 port map(
106 POWERDOWN => '1',
107 CLKA => clk_48,
108 LOCK => RaZ,
109 GLA => clk80,
110 GLB => clk
111 );
112 end generate;
113
114
115 gene3_3M : entity Clk_Divider2
116 generic map(N => 10)
117 port map(
118 clk_in => clk,
119 clk_out => sclkint
120 );
121
122 Wcounter : entity Word_Cntr
123 generic map(WordSize => WordSize ,N => WordCnt)
124 port map(
125 Sclk => Sclkint,
126 reset => rstn,
127 WordClk => WordClk,
128 Cnt_out => WordCount
129 );
72 130
73
74 DataRTX_echo <= DataRTX; --P48
75
76 ck_int0 : CLKINT
77 port map(Clock,clk);
78
79 DEFPLL: IF simu = 0 generate
80 PLL : entity work.PLL0
81 port map(
82 POWERDOWN => '1',
83 CLKA => clk,
84 LOCK => RaZ,
85 GLA => SCLKint,
86 GLB => clk80
87 );
88 end generate;
89
90
91 SIMPLL: IF simu = 1 generate
92 PLL : entity work.PLL0Sim
93 port map(
94 POWERDOWN => '1',
95 CLKA => clk,
96 LOCK => RaZ,
97 GLA => SCLKint,
98 GLB => clk80
99 );
100 end generate;
101
102
103 USB2: entity work.FX2_WithFIFO
104 generic map(apa3)
105 port map(
106 clk => clk,
107 if_clk => if_clk,
108 reset => rstn,
109 flagb => flagb,
110 slwr => slwr,
111 slrd => slrd,
112 pktend => pktend,
113 sloe => sloe,
114 fdbusw => fdbusw,
115 fifoadr => fifoadr,
116 FULL => USBfull,
117 Write => USBwe,
118 Data => USB_DATA
119
120 );
121
122
123 rstn <= reset and RaZ;
131 MFGEN0 : entity work.MinF_Gen
132 generic map(WordCnt => WordCnt)
133 port map(
134 clk => Sclkint,
135 reset => rstn,
136 WordCnt_in => WordCount,
137 WordClk => WordClk,
138 MinF_Clk => MinF
139 );
140
141 MinFcounter : entity Word_Cntr
142 generic map(WordSize => WordCnt ,N => MinFCount)
143 port map(
144 Sclk => WordClk,
145 reset => rstn,
146 WordClk => MinFclk,
147 Cnt_out => MinFCnt
148 );
149
150 MFGEN1 : entity work.MajF_Gen
151 generic map(WordCnt => WordCnt,MinFCount => MinFCount)
152 port map(
153 clk => Sclkint,
154 reset => rstn,
155 WordCnt_in => WordCount,
156 MinfCnt_in => MinFCnt,
157 WordClk => WordClk,
158 MajF_Clk => MajF
159 );
160
161 LFGATEGEN0 : entity work.LF_GATE_GEN
162 generic map(WordCnt => WordCnt)
163 port map(
164 clk => Sclkint,
165 Wcount => WordCount,
166 Gate => GateLF
167 );
168
169 DCGATEGEN0 : entity work.DC_GATE_GEN
170 generic map(WordCnt => WordCnt)
171 port map(
172 clk => Sclkint,
173 Wcount => WordCount,
174 Gate => GateDC
175 );
176
177 --GateDC <= '0';
178 --GateLF <= '0';
179
180 HFGATEGEN0 :
181 GateHF <= '1' when WordCount = 120 else
182 '1' when WordCount = 121 else '0';
183
184
185
186 SD0 : entity Serial_driver2
187 generic map(Sz => WordSize)
188 port map(
189 Sclk => Sclkint,
190 rstn => rstn,
191 Sdata => DataRTX,
192 Gate => GateR,
193 NwDat => NwDat,
194 Data => DATA
195 );
196
197
198
199 proto: entity work.ICI_EGSE_PROTOCOL
200 generic map(WordSize => WordSize,WordCnt => WordCnt,MinFCount => MinFCount,Simu => 0)
201 port map(
202 clk => clk,
203 -- reset => not MinF,
204 reset => rstn,
205 WEN => PROTO_WEN,
206 MinfCnt_in => MinfCnt,
207 WordCnt_in => WordCount,
208 DATAIN => PROTO_DATAIN,
209 FULL => PROTO_FULL,
210 WR => PROTO_WR,
211 DATAOUT => PROTO_DATAOUT
212 );
213
214
215
216 USB2: entity work.FX2_WithFIFO
217 generic map(CFG_MEMTECH,use_RAM)
218 port map(
219 clk => clk,
220 if_clk => if_clk,
221 reset => rstn,
222 flagb => flagb,
223 slwr => slwr,
224 slrd => slrd,
225 pktend => pktend,
226 sloe => sloe,
227 fdbusw => fdbusw,
228 fifoadr => fifoadr,
229 FULL => PROTO_FULL,
230 wen => PROTO_WR,
231 Data => PROTO_DATAOUT
232 );
233
234
235 rstn <= reset and RaZ;
236 SCLK <= Sclkint;
237
238 Major_Frame <= MajF;
239 --Minor_Frame <= MinF;
240 Minor_Frame <= MinFclk;
241 gateint <= GateDC or GateLF or GateHF;
242 Gate <= gateint;
243
244 process(Sclkint,rstn)
245 begin
246 if rstn = '0' then
247 GateR <= '0';
248 elsif Sclkint'event and Sclkint = '0' then
249 GateR <= Gateint;
250 end if;
251 end process;
252
253 BUS0 <= WordClk;
254 BUS12 <= MinFVector(0);
255 BUS13 <= MinFclk;
256 BUS14 <= '1' when WordCount = 0 else '0';
257
258 MinFVector <= std_logic_vector(TO_UNSIGNED(MinfCnt,WordSize));
259
124 260
125 261 process(clk,rstn)
126 262 begin
127 if rstn = '0' then
128 USB_DATA <= (others => '0');
129 USBwe <= '0';
263 if rstn = '0' then
264 PROTO_DATAIN <= (others => '0');
265 PROTO_WEN <= '1';
130 266 elsif clk'event and clk = '1' then
131 if USBfull = '0' then
132 USB_DATA <= std_logic_vector(unsigned(USB_DATA) + 1 );
133 USBwe <= '1';
267 NwDatR <= NwDat;
268 if NwDat = '1' and NwDatR = '0' then
269 PROTO_DATAIN <= std_logic_vector(unsigned(PROTO_DATAIN) + 1 );
270 PROTO_WEN <= '0';
134 271 else
135 USBwe <= '0';
272 PROTO_WEN <= '1';
136 273 end if;
137 274 end if;
138 end process;
139
140 end ar_TOP_EGSE2;
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
275 end process;
276
277 end ar_TOP_EGSE2;
278
279
280
281
282
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@@ -1,34 +1,34
1 1 GRLIB=../..
2 2 VHDLIB=../..
3 3 TOP=TOP_EGSE2
4 4 BOARD=GSE_ICI
5 5 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
6 6 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 7 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
8 8 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
9 9 EFFORT=high
10 10 XSTOPT=
11 11 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 VHDLSYNFILES=config.vhd EGSE_ICI.vhd
12 VHDLSYNFILES=config.vhd EGSE_ICI.vhd DC_GATE_GEN.vhd LF_GATE_GEN.vhd MajF_Gen.vhd MinF_Gen.vhd Serial_driver.vhd ICI_EGSE_PROTOCOL.vhd
13 13 VHDLSIMFILES=testbench.vhd
14 14 SIMTOP=testbench
15 15 SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
16 16 SDC=$(GRLIB)/boards/$(BOARD)/default.sdc
17 17 PDC=$(GRLIB)/boards/$(BOARD)/GSE_ICI.pdc
18 18 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
19 19 CLEAN=soft-clean
20 20
21 21 TECHLIBS = proasic3
22 22 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
23 23 tmtc openchip hynix ihp gleichmann micron usbhc spw fmf gsi eth spansion esa
24 24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 spacewire leon3 leon3ft sparc can greth net gr1553b lpp_waveform \
26 lpp_dma
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 spacewire leon3 leon3ft can greth net gr1553b ./amba_lcd_16x2_ctrlr ./lpp_waveform \
26 ./lpp_dma
27 27
28 28 FILESKIP = i2cmst.vhd
29 29
30 30 include $(GRLIB)/bin/Makefile
31 31 include $(GRLIB)/software/leon3/Makefile
32 32
33 33 ################## project specific targets ##########################
34 34
Show file before | Show file after | Hide comments
@@ -1,180 +1,40
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design test bench configuration
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 ------------------------------------------------------------------------------
15 15
16 16
17 17 library techmap;
18 18 use techmap.gencomp.all;
19 19
20 20 package config is
21 21
22 22
23 23 -- Technology and synthesis options
24 24 constant CFG_FABTECH : integer := apa3;
25 25 constant CFG_MEMTECH : integer := apa3;
26 26 constant CFG_PADTECH : integer := inferred;
27 27 constant CFG_NOASYNC : integer := 0;
28 28 constant CFG_SCAN : integer := 0;
29 29
30 30 -- Clock generator
31 31 constant CFG_CLKTECH : integer := inferred;
32 32 constant CFG_CLKMUL : integer := (5);
33 33 constant CFG_CLKDIV : integer := (10);
34 34 constant CFG_OCLKDIV : integer := (1);
35 35 constant CFG_PCIDLL : integer := 0;
36 36 constant CFG_PCISYSCLK: integer := 0;
37 37 constant CFG_CLK_NOFB : integer := 0;
38 38
39 -- LEON3 processor core
40 constant CFG_LEON3 : integer := 1;
41 constant CFG_NCPU : integer := (1);
42 constant CFG_NWIN : integer := (7);
43 constant CFG_V8 : integer := 0;
44 constant CFG_MAC : integer := 0;
45 constant CFG_SVT : integer := 0;
46 constant CFG_RSTADDR : integer := 16#00000#;
47 constant CFG_LDDEL : integer := (1);
48 constant CFG_NWP : integer := (0);
49 constant CFG_PWD : integer := 1*2;
50 constant CFG_FPU : integer := 0 + 16*0;
51 constant CFG_GRFPUSH : integer := 0;
52 constant CFG_ICEN : integer := 1;
53 constant CFG_ISETS : integer := 1;
54 constant CFG_ISETSZ : integer := 4;
55 constant CFG_ILINE : integer := 4;
56 constant CFG_IREPL : integer := 0;
57 constant CFG_ILOCK : integer := 0;
58 constant CFG_ILRAMEN : integer := 0;
59 constant CFG_ILRAMADDR: integer := 16#8E#;
60 constant CFG_ILRAMSZ : integer := 1;
61 constant CFG_DCEN : integer := 1;
62 constant CFG_DSETS : integer := 1;
63 constant CFG_DSETSZ : integer := 4;
64 constant CFG_DLINE : integer := 4;
65 constant CFG_DREPL : integer := 0;
66 constant CFG_DLOCK : integer := 0;
67 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
68 constant CFG_DFIXED : integer := 16#00F3#;
69 constant CFG_DLRAMEN : integer := 0;
70 constant CFG_DLRAMADDR: integer := 16#8F#;
71 constant CFG_DLRAMSZ : integer := 1;
72 constant CFG_MMUEN : integer := 0;
73 constant CFG_ITLBNUM : integer := 2;
74 constant CFG_DTLBNUM : integer := 2;
75 constant CFG_TLB_TYPE : integer := 1 + 0*2;
76 constant CFG_TLB_REP : integer := 1;
77 constant CFG_DSU : integer := 1;
78 constant CFG_ITBSZ : integer := 0;
79 constant CFG_ATBSZ : integer := 0;
80 constant CFG_LEON3FT_EN : integer := 0;
81 constant CFG_IUFT_EN : integer := 0;
82 constant CFG_FPUFT_EN : integer := 0;
83 constant CFG_RF_ERRINJ : integer := 0;
84 constant CFG_CACHE_FT_EN : integer := 0;
85 constant CFG_CACHE_ERRINJ : integer := 0;
86 constant CFG_LEON3_NETLIST: integer := 0;
87 constant CFG_DISAS : integer := 0 + 0;
88 constant CFG_PCLOW : integer := 2;
89
90 -- AMBA settings
91 constant CFG_DEFMST : integer := (0);
92 constant CFG_RROBIN : integer := 1;
93 constant CFG_SPLIT : integer := 0;
94 constant CFG_AHBIO : integer := 16#FFF#;
95 constant CFG_APBADDR : integer := 16#800#;
96 constant CFG_AHB_MON : integer := 0;
97 constant CFG_AHB_MONERR : integer := 0;
98 constant CFG_AHB_MONWAR : integer := 0;
99
100 -- DSU UART
101 constant CFG_AHB_UART : integer := 1;
102
103 -- JTAG based DSU interface
104 constant CFG_AHB_JTAG : integer := 0;
105
106 -- Ethernet DSU
107 constant CFG_DSU_ETH : integer := 0 + 0;
108 constant CFG_ETH_BUF : integer := 1;
109 constant CFG_ETH_IPM : integer := 16#C0A8#;
110 constant CFG_ETH_IPL : integer := 16#0033#;
111 constant CFG_ETH_ENM : integer := 16#00007A#;
112 constant CFG_ETH_ENL : integer := 16#CC0001#;
113
114 -- LEON2 memory controller
115 constant CFG_MCTRL_LEON2 : integer := 1;
116 constant CFG_MCTRL_RAM8BIT : integer := 0;
117 constant CFG_MCTRL_RAM16BIT : integer := 0;
118 constant CFG_MCTRL_5CS : integer := 0;
119 constant CFG_MCTRL_SDEN : integer := 0;
120 constant CFG_MCTRL_SEPBUS : integer := 0;
121 constant CFG_MCTRL_INVCLK : integer := 0;
122 constant CFG_MCTRL_SD64 : integer := 0;
123 constant CFG_MCTRL_PAGE : integer := 0 + 0;
124
125 -- SSRAM controller
126 constant CFG_SSCTRL : integer := 0;
127 constant CFG_SSCTRLP16 : integer := 0;
128
129 -- AHB ROM
130 constant CFG_AHBROMEN : integer := 0;
131 constant CFG_AHBROPIP : integer := 0;
132 constant CFG_AHBRODDR : integer := 16#000#;
133 constant CFG_ROMADDR : integer := 16#000#;
134 constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
135
136 -- AHB RAM
137 constant CFG_AHBRAMEN : integer := 0;
138 constant CFG_AHBRSZ : integer := 1;
139 constant CFG_AHBRADDR : integer := 16#A00#;
140
141 -- Gaisler Ethernet core
142 constant CFG_GRETH : integer := 0;
143 constant CFG_GRETH1G : integer := 0;
144 constant CFG_ETH_FIFO : integer := 8;
145
146 -- CAN 2.0 interface
147 constant CFG_CAN : integer := 0;
148 constant CFG_CANIO : integer := 16#0#;
149 constant CFG_CANIRQ : integer := 0;
150 constant CFG_CANLOOP : integer := 0;
151 constant CFG_CAN_SYNCRST : integer := 0;
152 constant CFG_CANFT : integer := 0;
153
154 -- UART 1
155 constant CFG_UART1_ENABLE : integer := 1;
156 constant CFG_UART1_FIFO : integer := 1;
157
158 -- LEON3 interrupt controller
159 constant CFG_IRQ3_ENABLE : integer := 1;
160
161 -- Modular timer
162 constant CFG_GPT_ENABLE : integer := 1;
163 constant CFG_GPT_NTIM : integer := (2);
164 constant CFG_GPT_SW : integer := (8);
165 constant CFG_GPT_TW : integer := (32);
166 constant CFG_GPT_IRQ : integer := (8);
167 constant CFG_GPT_SEPIRQ : integer := 1;
168 constant CFG_GPT_WDOGEN : integer := 0;
169 constant CFG_GPT_WDOG : integer := 16#0#;
170
171 -- GPIO port
172 constant CFG_GRGPIO_ENABLE : integer := 1;
173 constant CFG_GRGPIO_IMASK : integer := 16#0000#;
174 constant CFG_GRGPIO_WIDTH : integer := (7);
175
176 -- GRLIB debugging
177 constant CFG_DUART : integer := 0;
178
179 39
180 40 end;
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@@ -1,70 +1,74
1 1 -- Word_Cntr.vhd
2 2 library IEEE;
3 3 use IEEE.std_logic_1164.all;
4 4 use IEEE.numeric_std.all;
5 5
6 6
7 7
8 8
9 9 entity Word_Cntr is
10 10 generic(WordSize :integer := 8 ;N : integer := 144);
11 11 port(
12 12 Sclk : in std_logic;
13 13 reset : in std_logic;
14 14 WordClk : out std_logic;
15 15 Cnt_out : out integer range 0 to N-1
16 16 );
17 17 end entity;
18 18
19 19
20 20
21 21 architecture ar_Word_Cntr of Word_Cntr is
22 22
23 23 signal Cnt_int : integer range 0 to N-1 := 0;
24 24 signal Wcnt : integer range 0 to WordSize -1 ;
25 25
26 26 begin
27 27
28 28 Cnt_out <= Cnt_int;
29 29
30 30 process(Sclk,reset)
31 31 begin
32 32 if reset = '0' then
33 33 Cnt_int <= 0;
34 34 Wcnt <= 0;
35 35 WordClk <= '0';
36 36 elsif Sclk'event and Sclk = '1' then
37 37 if Wcnt = WordSize - 1 then
38 Cnt_int <= Cnt_int + 1;
38 if Cnt_int = N-1 then
39 Cnt_int <= 0;
40 else
41 Cnt_int <= Cnt_int + 1;
42 end if;
39 43 Wcnt <= 0;
40 44 WordClk <= '1';
41 45 else
42 46 Wcnt <= Wcnt + 1;
43 47 WordClk <= '0';
44 48 end if;
45 49 end if;
46 50 end process;
47 51 end ar_Word_Cntr;
48 52
49 53
50 54
51 55
52 56
53 57
54 58
55 59
56 60
57 61
58 62
59 63
60 64
61 65
62 66
63 67
64 68
65 69
66 70
67 71
68 72
69 73
70 74
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@@ -1,94 +1,93
1 1 -- FX2_WithFIFO.vhd
2 2 library IEEE;
3 3 use IEEE.std_logic_1164.all;
4 4 use IEEE.numeric_std.all;
5 5
6 6 library lpp;
7 7 use lpp.lpp_usb.all;
8 8 use lpp.lpp_memory.all;
9 9 use lpp.iir_filter.all;
10 10 library techmap;
11 11 use techmap.gencomp.all;
12 12
13 13 entity FX2_WithFIFO is
14 14 generic(
15 15 tech : integer := 0;
16 16 Mem_use : integer := use_RAM;
17 17 Enable_ReUse : std_logic := '0'
18 18 );
19 19 port(
20 20 clk : in STD_LOGIC;
21 21 if_clk : out STD_LOGIC;
22 22 reset : in std_logic;
23 23 flagb : in STD_LOGIC;
24 24 slwr : out STD_LOGIC;
25 25 slrd : out std_logic;
26 26 pktend : out STD_LOGIC;
27 27 sloe : out STD_LOGIC;
28 28 fdbusw : out std_logic_vector (7 downto 0);
29 29 fifoadr : out std_logic_vector (1 downto 0);
30 30
31 31 FULL : out std_logic;
32 Write : in std_logic;
32 wen : in std_logic;
33 33 Data : in std_logic_vector(7 downto 0)
34 34 );
35 35 end FX2_WithFIFO;
36 36
37 37
38 38 architecture Ar_FX2_WithFIFO of FX2_WithFIFO is
39 39
40 40 type FX2State is (idle);
41 41
42 42 Signal USB_DATA : std_logic_vector(7 downto 0);
43 Signal FIFOwe,FIFOre,FIFOfull : std_logic;
44 Signal USBwe,USBfull,USBempty : std_logic;
43 Signal FIFOfull : std_logic;
44 Signal USBwe,USBfull : std_logic;
45 45
46 46 begin
47 47
48 48 FULL <= FIFOfull;
49 49
50 FIFO: lpp_fifo
50 --FIFO: lpp_fifo
51 FIFO: FIFO_pipeline
51 52 generic map(
52 53 tech => tech,
53 54 Mem_use => Mem_use,
54 Enable_ReUse => '0',
55 55 DataSz => 8,
56 56 abits => 12
57 57 )
58 58 port map(
59 59 rstn => reset,
60 60 ReUse => '0',
61 61 rclk => clk,
62 62 ren => USBfull,
63 63 rdata => USB_DATA,
64 64 empty => USBwe,
65 65 raddr => open,
66 66 wclk => clk,
67 wen => not Write,
67 wen => wen,
68 68 wdata => Data,
69 69 full => FIFOfull,
70 70 waddr => open
71 71 );
72 72
73 73 USB2: entity FX2_Driver
74 74 port map(
75 75 clk => clk,
76 76 if_clk => if_clk,
77 77 reset => reset,
78 78 flagb => flagb,
79 79 slwr => slwr,
80 80 slrd => slrd,
81 81 pktend => pktend,
82 82 sloe => sloe,
83 83 fdbusw => fdbusw,
84 84 fifoadr => fifoadr,
85 85 FULL => USBfull,
86 86 Write => not USBwe,
87 87 Data => USB_DATA
88 88
89 89 );
90 90
91 91 end ar_FX2_WithFIFO;
92 92
93 93
94
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