##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

TOP_LFR with MS and WFP
pellion -
r305:daa615f43a86 (MINI-LFR) WFP_MS-0-1-1 JC
parent child
Show More
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (503 lines changed) Show them Hide them
@@ -0,0 +1,503
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY MINI_LFR_top IS
49
50 PORT (
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
111
112 END MINI_LFR_top;
113
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
132 SIGNAL I00_s : STD_LOGIC;
133
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
163
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
173 -----------------------------------------------------------------------------
174
175 BEGIN -- beh
176
177 -----------------------------------------------------------------------------
178 -- CLK
179 -----------------------------------------------------------------------------
180
181 PROCESS(clk_50)
182 BEGIN
183 IF clk_50'EVENT AND clk_50 = '1' THEN
184 clk_50_s <= NOT clk_50_s;
185 END IF;
186 END PROCESS;
187
188 PROCESS(clk_50_s)
189 BEGIN
190 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
191 clk_25 <= NOT clk_25;
192 END IF;
193 END PROCESS;
194
195 PROCESS(clk_49)
196 BEGIN
197 IF clk_49'EVENT AND clk_49 = '1' THEN
198 clk_24 <= NOT clk_24;
199 END IF;
200 END PROCESS;
201
202 -----------------------------------------------------------------------------
203
204 PROCESS (clk_25, reset)
205 BEGIN -- PROCESS
206 IF reset = '0' THEN -- asynchronous reset (active low)
207 LED0 <= '0';
208 LED1 <= '0';
209 LED2 <= '0';
210 --IO1 <= '0';
211 --IO2 <= '1';
212 --IO3 <= '0';
213 --IO4 <= '0';
214 --IO5 <= '0';
215 --IO6 <= '0';
216 --IO7 <= '0';
217 --IO8 <= '0';
218 --IO9 <= '0';
219 --IO10 <= '0';
220 --IO11 <= '0';
221 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 LED0 <= '0';
223 LED1 <= '1';
224 LED2 <= BP0;
225 --IO1 <= '1';
226 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO3 <= ADC_SDO(0);
228 --IO4 <= ADC_SDO(1);
229 --IO5 <= ADC_SDO(2);
230 --IO6 <= ADC_SDO(3);
231 --IO7 <= ADC_SDO(4);
232 --IO8 <= ADC_SDO(5);
233 --IO9 <= ADC_SDO(6);
234 --IO10 <= ADC_SDO(7);
235 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 END IF;
237 END PROCESS;
238
239 PROCESS (clk_24, reset)
240 BEGIN -- PROCESS
241 IF reset = '0' THEN -- asynchronous reset (active low)
242 I00_s <= '0';
243 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 I00_s <= NOT I00_s;
245 END IF;
246 END PROCESS;
247 -- IO0 <= I00_s;
248
249 --UARTs
250 nCTS1 <= '1';
251 nCTS2 <= '1';
252 nDCD2 <= '1';
253
254 --EXT CONNECTOR
255
256 --SPACE WIRE
257
258 leon3_soc_1 : leon3_soc
259 GENERIC MAP (
260 fabtech => apa3e,
261 memtech => apa3e,
262 padtech => inferred,
263 clktech => inferred,
264 disas => 0,
265 dbguart => 0,
266 pclow => 2,
267 clk_freq => 25000,
268 NB_CPU => 1,
269 ENABLE_FPU => 1,
270 FPU_NETLIST => 0,
271 ENABLE_DSU => 1,
272 ENABLE_AHB_UART => 1,
273 ENABLE_APB_UART => 1,
274 ENABLE_IRQMP => 1,
275 ENABLE_GPT => 1,
276 NB_AHB_MASTER => NB_AHB_MASTER,
277 NB_AHB_SLAVE => NB_AHB_SLAVE,
278 NB_APB_SLAVE => NB_APB_SLAVE)
279 PORT MAP (
280 clk => clk_25,
281 reset => reset,
282 errorn => errorn,
283 ahbrxd => TXD1,
284 ahbtxd => RXD1,
285 urxd1 => TXD2,
286 utxd1 => RXD2,
287 address => SRAM_A,
288 data => SRAM_DQ,
289 nSRAM_BE0 => SRAM_nBE(0),
290 nSRAM_BE1 => SRAM_nBE(1),
291 nSRAM_BE2 => SRAM_nBE(2),
292 nSRAM_BE3 => SRAM_nBE(3),
293 nSRAM_WE => SRAM_nWE,
294 nSRAM_CE => SRAM_CE,
295 nSRAM_OE => SRAM_nOE,
296
297 apbi_ext => apbi_ext,
298 apbo_ext => apbo_ext,
299 ahbi_s_ext => ahbi_s_ext,
300 ahbo_s_ext => ahbo_s_ext,
301 ahbi_m_ext => ahbi_m_ext,
302 ahbo_m_ext => ahbo_m_ext);
303
304 -------------------------------------------------------------------------------
305 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 -------------------------------------------------------------------------------
307 apb_lfr_time_management_1 : apb_lfr_time_management
308 GENERIC MAP (
309 pindex => 6,
310 paddr => 6,
311 pmask => 16#fff#,
312 pirq => 12,
313 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
314 PORT MAP (
315 clk25MHz => clk_25,
316 clk49_152MHz => clk_24, -- 49.152MHz/2
317 resetn => reset,
318 grspw_tick => swno.tickout,
319 apbi => apbi_ext,
320 apbo => apbo_ext(6),
321 coarse_time => coarse_time,
322 fine_time => fine_time);
323
324 -----------------------------------------------------------------------
325 --- SpaceWire --------------------------------------------------------
326 -----------------------------------------------------------------------
327
328 SPW_EN <= '1';
329
330 spw_clk <= clk_50_s;
331 spw_rxtxclk <= spw_clk;
332 spw_rxclkn <= NOT spw_rxtxclk;
333
334 -- PADS for SPW1
335 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
336 PORT MAP (SPW_NOM_DIN, dtmp(0));
337 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
338 PORT MAP (SPW_NOM_SIN, stmp(0));
339 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_DOUT, swno.d(0));
341 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_SOUT, swno.s(0));
343 -- PADS FOR SPW2
344 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 PORT MAP (SPW_RED_SIN, dtmp(1));
346 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 PORT MAP (SPW_RED_DIN, stmp(1));
348 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
349 PORT MAP (SPW_RED_DOUT, swno.d(1));
350 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
351 PORT MAP (SPW_RED_SOUT, swno.s(1));
352
353 -- GRSPW PHY
354 --spw1_input: if CFG_SPW_GRSPW = 1 generate
355 spw_inputloop : FOR j IN 0 TO 1 GENERATE
356 spw_phy0 : grspw_phy
357 GENERIC MAP(
358 tech => apa3e,
359 rxclkbuftype => 1,
360 scantest => 0)
361 PORT MAP(
362 rxrst => swno.rxrst,
363 di => dtmp(j),
364 si => stmp(j),
365 rxclko => spw_rxclk(j),
366 do => swni.d(j),
367 ndo => swni.nd(j*5+4 DOWNTO j*5),
368 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
369 END GENERATE spw_inputloop;
370
371 -- SPW core
372 sw0 : grspwm GENERIC MAP(
373 tech => apa3e,
374 hindex => 1,
375 pindex => 5,
376 paddr => 5,
377 pirq => 11,
378 sysfreq => 25000, -- CPU_FREQ
379 rmap => 1,
380 rmapcrc => 1,
381 fifosize1 => 16,
382 fifosize2 => 16,
383 rxclkbuftype => 1,
384 rxunaligned => 0,
385 rmapbufs => 4,
386 ft => 0,
387 netlist => 0,
388 ports => 2,
389 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
390 memtech => apa3e,
391 destkey => 2,
392 spwcore => 1
393 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
394 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
395 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
396 )
397 PORT MAP(reset, clk_25, spw_rxclk(0),
398 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
399 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
400 swni, swno);
401
402 swni.tickin <= '0';
403 swni.rmapen <= '1';
404 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
405 swni.tickinraw <= '0';
406 swni.timein <= (OTHERS => '0');
407 swni.dcrstval <= (OTHERS => '0');
408 swni.timerrstval <= (OTHERS => '0');
409
410 -------------------------------------------------------------------------------
411 -- LFR ------------------------------------------------------------------------
412 -------------------------------------------------------------------------------
413 lpp_lfr_1 : lpp_lfr
414 GENERIC MAP (
415 Mem_use => use_RAM,
416 nb_data_by_buffer_size => 32,
417 nb_word_by_buffer_size => 30,
418 nb_snapshot_param_size => 32,
419 delta_vector_size => 32,
420 delta_vector_size_f0_2 => 7, -- log2(96)
421 pindex => 15,
422 paddr => 15,
423 pmask => 16#fff#,
424 pirq_ms => 6,
425 pirq_wfp => 14,
426 hindex => 2,
427 top_lfr_version => X"000101") -- aa.bb.cc version
428 PORT MAP (
429 clk => clk_25,
430 rstn => reset,
431 sample_B => sample(2 DOWNTO 0),
432 sample_E => sample(7 DOWNTO 3),
433 sample_val => sample_val,
434 apbi => apbi_ext,
435 apbo => apbo_ext(15),
436 ahbi => ahbi_m_ext,
437 ahbo => ahbo_m_ext(2),
438 coarse_time => coarse_time,
439 fine_time => fine_time,
440 data_shaping_BW => bias_fail_sw_sig);
441
442 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
443 GENERIC MAP(
444 ChannelCount => 8,
445 SampleNbBits => 14,
446 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
447 ncycle_cnv => 250) -- 49 152 000 / 98304 /2
448 PORT MAP (
449 -- CONV
450 cnv_clk => clk_24,
451 cnv_rstn => reset,
452 cnv => ADC_nCS_sig,
453 -- DATA
454 clk => clk_25,
455 rstn => reset,
456 sck => ADC_CLK_sig,
457 sdo => ADC_SDO_sig,
458 -- SAMPLE
459 sample => sample,
460 sample_val => sample_val);
461
462 IO10 <= ADC_SDO_sig(5);
463 IO9 <= ADC_SDO_sig(4);
464 IO8 <= ADC_SDO_sig(3);
465
466 ADC_nCS <= ADC_nCS_sig;
467 ADC_CLK <= ADC_CLK_sig;
468 ADC_SDO_sig <= ADC_SDO;
469
470 ----------------------------------------------------------------------
471 --- GPIO -----------------------------------------------------------
472 ----------------------------------------------------------------------
473
474 grgpio0 : grgpio
475 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
476 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
477
478 pio_pad_0 : iopad
479 GENERIC MAP (tech => CFG_PADTECH)
480 PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
481 pio_pad_1 : iopad
482 GENERIC MAP (tech => CFG_PADTECH)
483 PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
484 pio_pad_2 : iopad
485 GENERIC MAP (tech => CFG_PADTECH)
486 PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
487 pio_pad_3 : iopad
488 GENERIC MAP (tech => CFG_PADTECH)
489 PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
490 pio_pad_4 : iopad
491 GENERIC MAP (tech => CFG_PADTECH)
492 PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
493 pio_pad_5 : iopad
494 GENERIC MAP (tech => CFG_PADTECH)
495 PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
496 pio_pad_6 : iopad
497 GENERIC MAP (tech => CFG_PADTECH)
498 PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
499 pio_pad_7 : iopad
500 GENERIC MAP (tech => CFG_PADTECH)
501 PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
502
503 END beh;
Show file before | Show file after | Hide comments
@@ -0,0 +1,46
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd
14
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 CLEAN=soft-clean
18
19 TECHLIBS = proasic3e
20
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
23
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 ./amba_lcd_16x2_ctrlr \
27 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_delay \
30 ./lpp_bootloader \
31 ./lpp_cna \
32 ./lpp_uart \
33 ./lpp_usb \
34 ./lpp_sim/CY7C1061DV33 \
35
36 FILESKIP =i2cmst.vhd \
37 APB_MULTI_DIODE.vhd \
38 APB_SIMPLE_DIODE.vhd \
39 Top_MatrixSpec.vhd \
40 APB_FFT.vhd
41
42 include $(GRLIB)/bin/Makefile
43 include $(GRLIB)/software/leon3/Makefile
44
45 ################## project specific targets ##########################
46
Show file before | Show file after | Hide comments
@@ -1,26 +1,28
1 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd
1 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd
2 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
2 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
3 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
3 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
4 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
4 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
5 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
5 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
6 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
6 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
7 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
7 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
8
8
9 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
9 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
10
10
11 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd
12 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd
11 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd
13 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd
12 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
14 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
13
15
14 vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd
16 vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd
15
17
16 vcom -quiet -93 -work lpp testbench_package.vhd
18 vcom -quiet -93 -work lpp testbench_package.vhd
17
19
18 vcom -quiet -93 -work work tb_waveform.vhd
20 vcom -quiet -93 -work work tb_waveform.vhd
19
21
20 vsim work.testbench
22 vsim work.testbench
21
23
22 log -r *
24 log -r *
23
25
24 do wave_waveform_longsim.do
26 do wave_ms.do
25
27
26 run 40 ms
28 run 2 ms
Show file before | Show file after | Hide comments
@@ -1,514 +1,514
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench
2 -- LEON3 Demonstration design test bench
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 ------------------------------------------------------------------------------
4 ------------------------------------------------------------------------------
5 -- This file is a part of the GRLIB VHDL IP LIBRARY
5 -- This file is a part of the GRLIB VHDL IP LIBRARY
6 -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
6 -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
7 --
7 --
8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
10 -- IN ADVANCE IN WRITING.
10 -- IN ADVANCE IN WRITING.
11 ------------------------------------------------------------------------------
11 ------------------------------------------------------------------------------
12
12
13 LIBRARY ieee;
13 LIBRARY ieee;
14 USE ieee.std_logic_1164.ALL;
14 USE ieee.std_logic_1164.ALL;
15
15
16 --LIBRARY std;
16 --LIBRARY std;
17 --USE std.textio.ALL;
17 --USE std.textio.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.AMBA_TestPackage.ALL;
22 USE grlib.AMBA_TestPackage.ALL;
23 LIBRARY gaisler;
23 LIBRARY gaisler;
24 USE gaisler.memctrl.ALL;
24 USE gaisler.memctrl.ALL;
25 USE gaisler.leon3.ALL;
25 USE gaisler.leon3.ALL;
26 USE gaisler.uart.ALL;
26 USE gaisler.uart.ALL;
27 USE gaisler.misc.ALL;
27 USE gaisler.misc.ALL;
28 USE gaisler.libdcom.ALL;
28 USE gaisler.libdcom.ALL;
29 USE gaisler.sim.ALL;
29 USE gaisler.sim.ALL;
30 USE gaisler.jtagtst.ALL;
30 USE gaisler.jtagtst.ALL;
31 USE gaisler.misc.ALL;
31 USE gaisler.misc.ALL;
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 --LIBRARY micron;
36 --LIBRARY micron;
37 --USE micron.components.ALL;
37 --USE micron.components.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_waveform_pkg.ALL;
39 USE lpp.lpp_waveform_pkg.ALL;
40 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.testbench_package.ALL;
42 USE lpp.testbench_package.ALL;
43 USE lpp.lpp_lfr_pkg.ALL;
43 USE lpp.lpp_lfr_pkg.ALL;
44 USE lpp.iir_filter.ALL;
44 USE lpp.iir_filter.ALL;
45 USE lpp.general_purpose.ALL;
45 USE lpp.general_purpose.ALL;
46 USE lpp.CY7C1061DV33_pkg.ALL;
46 USE lpp.CY7C1061DV33_pkg.ALL;
47
47
48 ENTITY testbench IS
48 ENTITY testbench IS
49 END;
49 END;
50
50
51 ARCHITECTURE behav OF testbench IS
51 ARCHITECTURE behav OF testbench IS
52 CONSTANT INDEX_LFR : INTEGER := 15;
52 CONSTANT INDEX_LFR : INTEGER := 15;
53 CONSTANT ADDR_LFR : INTEGER := 15;
53 CONSTANT ADDR_LFR : INTEGER := 15;
54 -- REG MS
54 -- REG MS
55 CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00";
55 CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00";
56 CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04";
56 CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04";
57 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08";
57 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08";
58 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C";
58 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C";
59 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10";
59 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10";
60 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14";
60 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14";
61 CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18";
61 CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18";
62 -- REG WAVEFORM
62 -- REG WAVEFORM
63 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
63 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
64 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
64 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
65 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
65 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
66 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
66 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
67 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
67 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
68 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
68 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
69 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
69 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
70 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
70 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
71 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
71 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
72 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
72 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
73 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
73 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
74 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
74 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
75 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
75 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
76 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
76 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
77 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
77 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
78 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
78 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
79 -- RAM ADDRESS
79 -- RAM ADDRESS
80 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
80 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
81 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
81 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
82 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
82 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
83 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
83 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
84
84
85
85
86 -- Common signal
86 -- Common signal
87 SIGNAL clk49_152MHz : STD_LOGIC := '0';
87 SIGNAL clk49_152MHz : STD_LOGIC := '0';
88 SIGNAL clk25MHz : STD_LOGIC := '0';
88 SIGNAL clk25MHz : STD_LOGIC := '0';
89 SIGNAL rstn : STD_LOGIC := '0';
89 SIGNAL rstn : STD_LOGIC := '0';
90
90
91 -- ADC interface
91 -- ADC interface
92 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
92 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
93 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
93 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
94 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
94 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
95
95
96 -- AD Converter RHF1401
96 -- AD Converter RHF1401
97 SIGNAL sample : Samples14v(7 DOWNTO 0);
97 SIGNAL sample : Samples14v(7 DOWNTO 0);
98 SIGNAL sample_val : STD_LOGIC;
98 SIGNAL sample_val : STD_LOGIC;
99
99
100 -- AHB/APB SIGNAL
100 -- AHB/APB SIGNAL
101 SIGNAL apbi : apb_slv_in_type;
101 SIGNAL apbi : apb_slv_in_type;
102 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
102 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
103 SIGNAL ahbsi : ahb_slv_in_type;
103 SIGNAL ahbsi : ahb_slv_in_type;
104 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
104 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
105 SIGNAL ahbmi : ahb_mst_in_type;
105 SIGNAL ahbmi : ahb_mst_in_type;
106 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
106 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
107
107
108 SIGNAL bias_fail_bw : STD_LOGIC;
108 SIGNAL bias_fail_bw : STD_LOGIC;
109
109
110 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
111 -- LPP_WAVEFORM
111 -- LPP_WAVEFORM
112 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113 CONSTANT data_size : INTEGER := 96;
113 CONSTANT data_size : INTEGER := 96;
114 CONSTANT nb_burst_available_size : INTEGER := 50;
114 CONSTANT nb_burst_available_size : INTEGER := 50;
115 CONSTANT nb_snapshot_param_size : INTEGER := 2;
115 CONSTANT nb_snapshot_param_size : INTEGER := 2;
116 CONSTANT delta_vector_size : INTEGER := 2;
116 CONSTANT delta_vector_size : INTEGER := 2;
117 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
117 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
118
118
119 SIGNAL reg_run : STD_LOGIC;
119 SIGNAL reg_run : STD_LOGIC;
120 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
120 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
121 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
123 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
123 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
124 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
124 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
125 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
125 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
126 SIGNAL enable_f0 : STD_LOGIC;
126 SIGNAL enable_f0 : STD_LOGIC;
127 SIGNAL enable_f1 : STD_LOGIC;
127 SIGNAL enable_f1 : STD_LOGIC;
128 SIGNAL enable_f2 : STD_LOGIC;
128 SIGNAL enable_f2 : STD_LOGIC;
129 SIGNAL enable_f3 : STD_LOGIC;
129 SIGNAL enable_f3 : STD_LOGIC;
130 SIGNAL burst_f0 : STD_LOGIC;
130 SIGNAL burst_f0 : STD_LOGIC;
131 SIGNAL burst_f1 : STD_LOGIC;
131 SIGNAL burst_f1 : STD_LOGIC;
132 SIGNAL burst_f2 : STD_LOGIC;
132 SIGNAL burst_f2 : STD_LOGIC;
133 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
133 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
134 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
134 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
135 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
135 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
136 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
136 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
137 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
137 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
138 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
138 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
139 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
140 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
141 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL data_f0_in_valid : STD_LOGIC;
142 SIGNAL data_f0_in_valid : STD_LOGIC;
143 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL data_f1_in_valid : STD_LOGIC;
145 SIGNAL data_f1_in_valid : STD_LOGIC;
146 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL data_f2_in_valid : STD_LOGIC;
148 SIGNAL data_f2_in_valid : STD_LOGIC;
149 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
149 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL data_f3_in_valid : STD_LOGIC;
151 SIGNAL data_f3_in_valid : STD_LOGIC;
152 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
152 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
153 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL data_f0_data_out_valid : STD_LOGIC;
155 SIGNAL data_f0_data_out_valid : STD_LOGIC;
156 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
156 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
157 SIGNAL data_f0_data_out_ack : STD_LOGIC;
157 SIGNAL data_f0_data_out_ack : STD_LOGIC;
158 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f1_data_out_valid : STD_LOGIC;
160 SIGNAL data_f1_data_out_valid : STD_LOGIC;
161 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
161 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
162 SIGNAL data_f1_data_out_ack : STD_LOGIC;
162 SIGNAL data_f1_data_out_ack : STD_LOGIC;
163 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
164 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
164 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL data_f2_data_out_valid : STD_LOGIC;
165 SIGNAL data_f2_data_out_valid : STD_LOGIC;
166 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
166 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
167 SIGNAL data_f2_data_out_ack : STD_LOGIC;
167 SIGNAL data_f2_data_out_ack : STD_LOGIC;
168 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 SIGNAL data_f3_data_out_valid : STD_LOGIC;
170 SIGNAL data_f3_data_out_valid : STD_LOGIC;
171 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
171 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
172 SIGNAL data_f3_data_out_ack : STD_LOGIC;
172 SIGNAL data_f3_data_out_ack : STD_LOGIC;
173
173
174 --MEM CTRLR
174 --MEM CTRLR
175 SIGNAL memi : memory_in_type;
175 SIGNAL memi : memory_in_type;
176 SIGNAL memo : memory_out_type;
176 SIGNAL memo : memory_out_type;
177 SIGNAL wpo : wprot_out_type;
177 SIGNAL wpo : wprot_out_type;
178 SIGNAL sdo : sdram_out_type;
178 SIGNAL sdo : sdram_out_type;
179
179
180 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000";
180 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000";
181 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 SIGNAL nSRAM_BE0 : STD_LOGIC;
182 SIGNAL nSRAM_BE0 : STD_LOGIC;
183 SIGNAL nSRAM_BE1 : STD_LOGIC;
183 SIGNAL nSRAM_BE1 : STD_LOGIC;
184 SIGNAL nSRAM_BE2 : STD_LOGIC;
184 SIGNAL nSRAM_BE2 : STD_LOGIC;
185 SIGNAL nSRAM_BE3 : STD_LOGIC;
185 SIGNAL nSRAM_BE3 : STD_LOGIC;
186 SIGNAL nSRAM_WE : STD_LOGIC;
186 SIGNAL nSRAM_WE : STD_LOGIC;
187 SIGNAL nSRAM_CE : STD_LOGIC;
187 SIGNAL nSRAM_CE : STD_LOGIC;
188 SIGNAL nSRAM_OE : STD_LOGIC;
188 SIGNAL nSRAM_OE : STD_LOGIC;
189
189
190 CONSTANT padtech : INTEGER := inferred;
190 CONSTANT padtech : INTEGER := inferred;
191 SIGNAL not_ramsn_0 : STD_LOGIC;
191 SIGNAL not_ramsn_0 : STD_LOGIC;
192
192
193 -----------------------------------------------------------------------------
193 -----------------------------------------------------------------------------
194 SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 SIGNAL read_buffer : STD_LOGIC;
195 SIGNAL read_buffer : STD_LOGIC;
196 -----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------
197 SIGNAL run_test_waveform_picker : STD_LOGIC := '1';
197 SIGNAL run_test_waveform_picker : STD_LOGIC := '1';
198 SIGNAL state_read_buffer_on_going : STD_LOGIC;
198 SIGNAL state_read_buffer_on_going : STD_LOGIC;
199 CONSTANT hindex : INTEGER := 1;
199 CONSTANT hindex : INTEGER := 1;
200 SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0);
200 SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0);
201 SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0);
201 SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0);
202 SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0);
202 SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0);
203 SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0);
203 SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0);
204
204
205 SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
207 SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
207 SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
209
209
210 SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
210 SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
211 SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
211 SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
212 SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
212 SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
213
213
214 SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
214 SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
215 SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
215 SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
216 SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
216 SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
217
217
218 SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
218 SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
219 SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
219 SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
220 SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
220 SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
221
221
222 SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
222 SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
223 SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
223 SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
224 SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
224 SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
225
225
226 SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
226 SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
227 SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
227 SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
228 SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
228 SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
229
229
230 SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
230 SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
231 SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
231 SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
232 SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
232 SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
233 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
234
234
235 SIGNAL current_data : INTEGER;
235 SIGNAL current_data : INTEGER;
236 SIGNAL LIMIT_DATA : INTEGER := 64;
236 SIGNAL LIMIT_DATA : INTEGER := 64;
237
237
238 SIGNAL read_buffer_temp : STD_LOGIC;
238 SIGNAL read_buffer_temp : STD_LOGIC;
239 SIGNAL read_buffer_temp_2 : STD_LOGIC;
239 SIGNAL read_buffer_temp_2 : STD_LOGIC;
240
240
241
241
242 BEGIN
242 BEGIN
243
243
244 -----------------------------------------------------------------------------
244 -----------------------------------------------------------------------------
245
245
246 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
246 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
247 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
247 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
248
248
249 -----------------------------------------------------------------------------
249 -----------------------------------------------------------------------------
250
250
251 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
251 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
252 TestModule_RHF1401_1 : TestModule_RHF1401
252 TestModule_RHF1401_1 : TestModule_RHF1401
253 GENERIC MAP (
253 GENERIC MAP (
254 freq => 24*(I+1),
254 freq => 24*(I+1),
255 amplitude => 8000/(I+1),
255 amplitude => 8000/(I+1),
256 impulsion => 0)
256 impulsion => 0)
257 PORT MAP (
257 PORT MAP (
258 ADC_smpclk => ADC_smpclk,
258 ADC_smpclk => ADC_smpclk,
259 ADC_OEB_bar => ADC_OEB_bar_CH(I),
259 ADC_OEB_bar => ADC_OEB_bar_CH(I),
260 ADC_data => ADC_data);
260 ADC_data => ADC_data);
261 END GENERATE MODULE_RHF1401;
261 END GENERATE MODULE_RHF1401;
262
262
263 -----------------------------------------------------------------------------
263 -----------------------------------------------------------------------------
264
264
265 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
265 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
266 GENERIC MAP (
266 GENERIC MAP (
267 ChanelCount => 8,
267 ChanelCount => 8,
268 ncycle_cnv_high => 79,
268 ncycle_cnv_high => 79,
269 ncycle_cnv => 500)
269 ncycle_cnv => 500)
270 PORT MAP (
270 PORT MAP (
271 cnv_clk => clk49_152MHz,
271 cnv_clk => clk49_152MHz,
272 cnv_rstn => rstn,
272 cnv_rstn => rstn,
273 cnv => ADC_smpclk,
273 cnv => ADC_smpclk,
274 clk => clk25MHz,
274 clk => clk25MHz,
275 rstn => rstn,
275 rstn => rstn,
276 ADC_data => ADC_data,
276 ADC_data => ADC_data,
277 ADC_nOE => ADC_OEB_bar_CH,
277 ADC_nOE => ADC_OEB_bar_CH,
278 sample => sample,
278 sample => sample,
279 sample_val => sample_val);
279 sample_val => sample_val);
280
280
281 -----------------------------------------------------------------------------
281 -----------------------------------------------------------------------------
282
282
283 lpp_lfr_1 : lpp_lfr
283 lpp_lfr_1 : lpp_lfr
284 GENERIC MAP (
284 GENERIC MAP (
285 Mem_use => use_CEL, -- use_RAM
285 Mem_use => use_CEL, -- use_RAM
286 nb_data_by_buffer_size => 32,
286 nb_data_by_buffer_size => 32,
287 nb_word_by_buffer_size => 30,
287 nb_word_by_buffer_size => 30,
288 nb_snapshot_param_size => 32,
288 nb_snapshot_param_size => 32,
289 delta_vector_size => 32,
289 delta_vector_size => 32,
290 delta_vector_size_f0_2 => 32,
290 delta_vector_size_f0_2 => 32,
291 pindex => INDEX_LFR,
291 pindex => INDEX_LFR,
292 paddr => ADDR_LFR,
292 paddr => ADDR_LFR,
293 pmask => 16#fff#,
293 pmask => 16#fff#,
294 pirq_ms => 6,
294 pirq_ms => 6,
295 pirq_wfp => 14,
295 pirq_wfp => 14,
296 hindex => 0,
296 hindex => 0,
297 top_lfr_version => X"000001")
297 top_lfr_version => X"000001")
298 PORT MAP (
298 PORT MAP (
299 clk => clk25MHz,
299 clk => clk25MHz,
300 rstn => rstn,
300 rstn => rstn,
301 sample_B => sample(2 DOWNTO 0),
301 sample_B => sample(2 DOWNTO 0),
302 sample_E => sample(7 DOWNTO 3),
302 sample_E => sample(7 DOWNTO 3),
303 sample_val => sample_val,
303 sample_val => sample_val,
304 apbi => apbi,
304 apbi => apbi,
305 apbo => apbo(15),
305 apbo => apbo(15),
306 ahbi => ahbmi,
306 ahbi => ahbmi,
307 ahbo => ahbmo(0),
307 ahbo => ahbmo(0),
308 coarse_time => coarse_time,
308 coarse_time => coarse_time,
309 fine_time => fine_time,
309 fine_time => fine_time,
310 data_shaping_BW => bias_fail_bw);
310 data_shaping_BW => bias_fail_bw);
311
311
312 -----------------------------------------------------------------------------
312 -----------------------------------------------------------------------------
313 --- AHB CONTROLLER -------------------------------------------------
313 --- AHB CONTROLLER -------------------------------------------------
314 ahb0 : ahbctrl -- AHB arbiter/multiplexer
314 ahb0 : ahbctrl -- AHB arbiter/multiplexer
315 GENERIC MAP (defmast => 0, split => 0,
315 GENERIC MAP (defmast => 0, split => 0,
316 rrobin => 1, ioaddr => 16#FFF#,
316 rrobin => 1, ioaddr => 16#FFF#,
317 ioen => 0, nahbm => 2, nahbs => 1)
317 ioen => 0, nahbm => 2, nahbs => 4)
318 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
318 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
319
319
320
320
321
321
322 --- AHB RAM ----------------------------------------------------------
322 --- AHB RAM ----------------------------------------------------------
323 --ahbram0 : ahbram
323 ahbram0 : ahbram
324 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
324 GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
325 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
325 PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
326 --ahbram1 : ahbram
326 ahbram1 : ahbram
327 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
327 GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
328 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
328 PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
329 --ahbram2 : ahbram
329 ahbram2 : ahbram
330 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
330 GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
331 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
331 PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
332 --ahbram3 : ahbram
332 ahbram3 : ahbram
333 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
333 GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
334 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
334 PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
335
335
336 -----------------------------------------------------------------------------
336 -----------------------------------------------------------------------------
337 ----------------------------------------------------------------------
337 ----------------------------------------------------------------------
338 --- Memory controllers ---------------------------------------------
338 --- Memory controllers ---------------------------------------------
339 ----------------------------------------------------------------------
339 ----------------------------------------------------------------------
340 --memctrlr : mctrl GENERIC MAP (
340 --memctrlr : mctrl GENERIC MAP (
341 -- hindex => 0,
341 -- hindex => 0,
342 -- pindex => 0,
342 -- pindex => 0,
343 -- paddr => 0,
343 -- paddr => 0,
344 -- srbanks => 1
344 -- srbanks => 1
345 -- )
345 -- )
346 -- PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
346 -- PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
347
347
348 --memi.brdyn <= '1';
348 --memi.brdyn <= '1';
349 --memi.bexcn <= '1';
349 --memi.bexcn <= '1';
350 --memi.writen <= '1';
350 --memi.writen <= '1';
351 --memi.wrn <= "1111";
351 --memi.wrn <= "1111";
352 --memi.bwidth <= "10";
352 --memi.bwidth <= "10";
353
353
354 --bdr : FOR i IN 0 TO 3 GENERATE
354 --bdr : FOR i IN 0 TO 3 GENERATE
355 -- data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
355 -- data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
356 -- PORT MAP (
356 -- PORT MAP (
357 -- data(31-i*8 DOWNTO 24-i*8),
357 -- data(31-i*8 DOWNTO 24-i*8),
358 -- memo.data(31-i*8 DOWNTO 24-i*8),
358 -- memo.data(31-i*8 DOWNTO 24-i*8),
359 -- memo.bdrive(i),
359 -- memo.bdrive(i),
360 -- memi.data(31-i*8 DOWNTO 24-i*8));
360 -- memi.data(31-i*8 DOWNTO 24-i*8));
361 --END GENERATE;
361 --END GENERATE;
362
362
363 --addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
363 --addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
364 -- PORT MAP (address, memo.address(21 DOWNTO 2));
364 -- PORT MAP (address, memo.address(21 DOWNTO 2));
365
365
366 --not_ramsn_0 <= NOT(memo.ramsn(0));
366 --not_ramsn_0 <= NOT(memo.ramsn(0));
367
367
368 --rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
368 --rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
369 --oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
369 --oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
370 --nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
370 --nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
371 --nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
371 --nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
372 --nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
372 --nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
373 --nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
373 --nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
374 --nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
374 --nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
375
375
376 --async_1Mx16_0: CY7C1061DV33
376 --async_1Mx16_0: CY7C1061DV33
377 -- GENERIC MAP (
377 -- GENERIC MAP (
378 -- ADDR_BITS => 20,
378 -- ADDR_BITS => 20,
379 -- DATA_BITS => 16,
379 -- DATA_BITS => 16,
380 -- depth => 1048576,
380 -- depth => 1048576,
381 -- TimingInfo => TRUE,
381 -- TimingInfo => TRUE,
382 -- TimingChecks => '1')
382 -- TimingChecks => '1')
383 -- PORT MAP (
383 -- PORT MAP (
384 -- CE1_b => '0',
384 -- CE1_b => '0',
385 -- CE2 => nSRAM_CE,
385 -- CE2 => nSRAM_CE,
386 -- WE_b => nSRAM_WE,
386 -- WE_b => nSRAM_WE,
387 -- OE_b => nSRAM_OE,
387 -- OE_b => nSRAM_OE,
388 -- BHE_b => nSRAM_BE1,
388 -- BHE_b => nSRAM_BE1,
389 -- BLE_b => nSRAM_BE0,
389 -- BLE_b => nSRAM_BE0,
390 -- A => address,
390 -- A => address,
391 -- DQ => data(15 DOWNTO 0));
391 -- DQ => data(15 DOWNTO 0));
392
392
393 --async_1Mx16_1: CY7C1061DV33
393 --async_1Mx16_1: CY7C1061DV33
394 -- GENERIC MAP (
394 -- GENERIC MAP (
395 -- ADDR_BITS => 20,
395 -- ADDR_BITS => 20,
396 -- DATA_BITS => 16,
396 -- DATA_BITS => 16,
397 -- depth => 1048576,
397 -- depth => 1048576,
398 -- TimingInfo => TRUE,
398 -- TimingInfo => TRUE,
399 -- TimingChecks => '1')
399 -- TimingChecks => '1')
400 -- PORT MAP (
400 -- PORT MAP (
401 -- CE1_b => '0',
401 -- CE1_b => '0',
402 -- CE2 => nSRAM_CE,
402 -- CE2 => nSRAM_CE,
403 -- WE_b => nSRAM_WE,
403 -- WE_b => nSRAM_WE,
404 -- OE_b => nSRAM_OE,
404 -- OE_b => nSRAM_OE,
405 -- BHE_b => nSRAM_BE3,
405 -- BHE_b => nSRAM_BE3,
406 -- BLE_b => nSRAM_BE2,
406 -- BLE_b => nSRAM_BE2,
407 -- A => address,
407 -- A => address,
408 -- DQ => data(31 DOWNTO 16));
408 -- DQ => data(31 DOWNTO 16));
409
409
410
410
411 -----------------------------------------------------------------------------
411 -----------------------------------------------------------------------------
412
412
413 WaveGen_Proc : PROCESS
413 WaveGen_Proc : PROCESS
414 BEGIN
414 BEGIN
415
415
416 -- insert signal assignments here
416 -- insert signal assignments here
417 WAIT UNTIL clk25MHz = '1';
417 WAIT UNTIL clk25MHz = '1';
418 rstn <= '0';
418 rstn <= '0';
419 apbi.psel(15) <= '0';
419 apbi.psel(15) <= '0';
420 apbi.pwrite <= '0';
420 apbi.pwrite <= '0';
421 apbi.penable <= '0';
421 apbi.penable <= '0';
422 apbi.paddr <= (OTHERS => '0');
422 apbi.paddr <= (OTHERS => '0');
423 apbi.pwdata <= (OTHERS => '0');
423 apbi.pwdata <= (OTHERS => '0');
424 fine_time <= (OTHERS => '0');
424 fine_time <= (OTHERS => '0');
425 coarse_time <= (OTHERS => '0');
425 coarse_time <= (OTHERS => '0');
426 WAIT UNTIL clk25MHz = '1';
426 WAIT UNTIL clk25MHz = '1';
427 -- ahbmi.HGRANT(2) <= '1';
427 -- ahbmi.HGRANT(2) <= '1';
428 -- ahbmi.HREADY <= '1';
428 -- ahbmi.HREADY <= '1';
429 -- ahbmi.HRESP <= HRESP_OKAY;
429 -- ahbmi.HRESP <= HRESP_OKAY;
430
430
431 WAIT UNTIL clk25MHz = '1';
431 WAIT UNTIL clk25MHz = '1';
432 WAIT UNTIL clk25MHz = '1';
432 WAIT UNTIL clk25MHz = '1';
433 rstn <= '1';
433 rstn <= '1';
434 WAIT UNTIL clk25MHz = '1';
434 WAIT UNTIL clk25MHz = '1';
435 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"10000000");
435 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"10000000");
436 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"20020000");
436 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"20020000");
437 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 , X"30040000");
437 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 , X"30040000");
438 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 , X"40060000");
438 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 , X"40060000");
439
439
440 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000");
440 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000");
441 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000");
441 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000");
442 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080");
442 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080");
443 WAIT UNTIL clk25MHz = '1';
443 WAIT UNTIL clk25MHz = '1';
444 ---------------------------------------------------------------------------
444 ---------------------------------------------------------------------------
445 -- CONFIGURATION STEP
445 -- CONFIGURATION STEP
446 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
446 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
447 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
447 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
448 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
448 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
449 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
449 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
450
450
451 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020"
451 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020"
452 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019"
452 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019"
453 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
453 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
454 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019"
454 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019"
455 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
455 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
456
456
457 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
457 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
458 --
458 --
459 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010");
459 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010");
460 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
460 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
461 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022");
461 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022");
462
462
463
463
464 WAIT UNTIL clk25MHz = '1';
464 WAIT UNTIL clk25MHz = '1';
465 WAIT UNTIL clk25MHz = '1';
465 WAIT UNTIL clk25MHz = '1';
466
466
467
467
468 --APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087");
468 --APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087");
469 WAIT UNTIL clk25MHz = '1';
469 WAIT UNTIL clk25MHz = '1';
470 WAIT UNTIL clk25MHz = '1';
470 WAIT UNTIL clk25MHz = '1';
471 WAIT UNTIL clk25MHz = '1';
471 WAIT UNTIL clk25MHz = '1';
472 WAIT UNTIL clk25MHz = '1';
472 WAIT UNTIL clk25MHz = '1';
473 WAIT UNTIL clk25MHz = '1';
473 WAIT UNTIL clk25MHz = '1';
474 WAIT UNTIL clk25MHz = '1';
474 WAIT UNTIL clk25MHz = '1';
475 WAIT FOR 1 us;
475 WAIT FOR 1 us;
476 coarse_time <= X"00000001";
476 coarse_time <= X"00000001";
477 ---------------------------------------------------------------------------
477 ---------------------------------------------------------------------------
478 -- RUN STEP
478 -- RUN STEP
479 WAIT FOR 200 ms;
479 WAIT FOR 200 ms;
480 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
480 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
481 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
481 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
482 WAIT FOR 10 us;
482 WAIT FOR 10 us;
483 WAIT UNTIL clk25MHz = '1';
483 WAIT UNTIL clk25MHz = '1';
484 WAIT UNTIL clk25MHz = '1';
484 WAIT UNTIL clk25MHz = '1';
485 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
485 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
486 WAIT UNTIL clk25MHz = '1';
486 WAIT UNTIL clk25MHz = '1';
487 coarse_time <= X"00000010";
487 coarse_time <= X"00000010";
488 WAIT FOR 100 ms;
488 WAIT FOR 100 ms;
489 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
489 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
490 WAIT FOR 10 us;
490 WAIT FOR 10 us;
491 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
491 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
492 WAIT FOR 200 ms;
492 WAIT FOR 200 ms;
493 REPORT "*** END simulation ***" SEVERITY failure;
493 REPORT "*** END simulation ***" SEVERITY failure;
494
494
495
495
496 WAIT;
496 WAIT;
497
497
498 END PROCESS WaveGen_Proc;
498 END PROCESS WaveGen_Proc;
499 -----------------------------------------------------------------------------
499 -----------------------------------------------------------------------------
500
500
501 -----------------------------------------------------------------------------
501 -----------------------------------------------------------------------------
502 -- IRQ
502 -- IRQ
503 -----------------------------------------------------------------------------
503 -----------------------------------------------------------------------------
504 PROCESS
504 PROCESS (clk25MHz, rstn)
505 BEGIN -- PROCESS
505 BEGIN -- PROCESS
506 IF rstn = '0' THEN -- asynchronous reset (active low)
506 IF rstn = '0' THEN -- asynchronous reset (active low)
507
507
508 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
508 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
509
509
510 END IF;
510 END IF;
511 END PROCESS;
511 END PROCESS;
512 -----------------------------------------------------------------------------
512 -----------------------------------------------------------------------------
513
513
514 END;
514 END;
Show file before | Show file after | Hide comments
@@ -1,23 +1,24
1 general_purpose.vhd
1 general_purpose.vhd
2 ADDRcntr.vhd
2 ADDRcntr.vhd
3 ALU.vhd
3 ALU.vhd
4 Adder.vhd
4 Adder.vhd
5 Clk_Divider2.vhd
5 Clk_Divider2.vhd
6 Clk_divider.vhd
6 Clk_divider.vhd
7 MAC.vhd
7 MAC.vhd
8 MAC_CONTROLER.vhd
8 MAC_CONTROLER.vhd
9 MAC_MUX.vhd
9 MAC_MUX.vhd
10 MAC_MUX2.vhd
10 MAC_MUX2.vhd
11 MAC_REG.vhd
11 MAC_REG.vhd
12 MUX2.vhd
12 MUX2.vhd
13 MUXN.vhd
13 MUXN.vhd
14 Multiplier.vhd
14 Multiplier.vhd
15 REG.vhd
15 REG.vhd
16 SYNC_FF.vhd
16 SYNC_FF.vhd
17 Shifter.vhd
17 Shifter.vhd
18 TwoComplementer.vhd
18 TwoComplementer.vhd
19 Clock_Divider.vhd
19 Clock_Divider.vhd
20 lpp_front_to_level.vhd
20 lpp_front_detection.vhd
21 lpp_front_detection.vhd
21 lpp_front_positive_detection.vhd
22 lpp_front_positive_detection.vhd
22 SYNC_VALID_BIT.vhd
23 SYNC_VALID_BIT.vhd
23 RR_Arbiter_4.vhd
24 RR_Arbiter_4.vhd
Show file before | Show file after | Hide comments
@@ -1,47 +1,47
1
1
2 --=================================================================================
2 --=================================================================================
3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
4 --
4 --
5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
6 --=================================================================================
6 --=================================================================================
7
7
8
8
9 LIBRARY ieee;
9 LIBRARY ieee;
10 USE ieee.std_logic_1164.ALL;
10 USE ieee.std_logic_1164.ALL;
11 LIBRARY grlib;
11 LIBRARY grlib;
12 USE grlib.amba.ALL;
12 USE grlib.amba.ALL;
13 USE std.textio.ALL;
13 USE std.textio.ALL;
14
14
15
15
16 PACKAGE apb_devices_list IS
16 PACKAGE apb_devices_list IS
17
17
18
18
19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
20
20
21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
22 CONSTANT otherCore : amba_device_type := 16#2#;
22 CONSTANT otherCore : amba_device_type := 16#2#;
23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 CONSTANT LPP_UART : amba_device_type := 16#6#;
26 CONSTANT LPP_UART : amba_device_type := 16#6#;
27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
35 CONSTANT LPP_USB : amba_device_type := 16#15#;
35 CONSTANT LPP_USB : amba_device_type := 16#15#;
36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
41
41
42 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
42 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
43 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A1#;
43 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
44
44
45 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
45 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
46
46
47 END;
47 END;
Show file before | Show file after | Hide comments
@@ -1,762 +1,769
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
49 sample_B : IN Samples14v(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC--;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65
65
66 --debug
66 --debug
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 --debug_f0_data_valid : OUT STD_LOGIC;
68 --debug_f0_data_valid : OUT STD_LOGIC;
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 --debug_f1_data_valid : OUT STD_LOGIC;
70 --debug_f1_data_valid : OUT STD_LOGIC;
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f2_data_valid : OUT STD_LOGIC;
72 --debug_f2_data_valid : OUT STD_LOGIC;
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f3_data_valid : OUT STD_LOGIC;
74 --debug_f3_data_valid : OUT STD_LOGIC;
75
75
76 ---- debug FIFO_IN
76 ---- debug FIFO_IN
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85
85
86 ----debug FIFO OUT
86 ----debug FIFO OUT
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95
95
96 ----debug DMA IN
96 ----debug DMA IN
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 );
105 );
106 END lpp_lfr;
106 END lpp_lfr;
107
107
108 ARCHITECTURE beh OF lpp_lfr IS
108 ARCHITECTURE beh OF lpp_lfr IS
109 SIGNAL sample : Samples14v(7 DOWNTO 0);
109 SIGNAL sample : Samples14v(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 --
111 --
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
116 --
116 --
117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 --
120 --
121 SIGNAL sample_f0_val : STD_LOGIC;
121 SIGNAL sample_f0_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
125 --
125 --
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 --
130 --
131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134
134
135 -- SM
135 -- SM
136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
155
156 -- WFP
156 -- WFP
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166
166
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 SIGNAL enable_f0 : STD_LOGIC;
170 SIGNAL enable_f0 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181
181
182 SIGNAL run : STD_LOGIC;
182 SIGNAL run : STD_LOGIC;
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184
184
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 --f1
190 --f1
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 --f2
196 --f2
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 --f3
202 --f3
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208
208
209 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
210 --
210 --
211 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 --f1
215 --f1
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 --f2
219 --f2
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 --f3
223 --f3
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227
227
228 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
229 -- DMA RR
229 -- DMA RR
230 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
231 SIGNAL dma_sel_valid : STD_LOGIC;
231 SIGNAL dma_sel_valid : STD_LOGIC;
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236
236
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239
239
240 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
241 -- DMA_REG
241 -- DMA_REG
242 -----------------------------------------------------------------------------
242 -----------------------------------------------------------------------------
243 SIGNAL ongoing_reg : STD_LOGIC;
243 SIGNAL ongoing_reg : STD_LOGIC;
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 SIGNAL dma_send_reg : STD_LOGIC;
245 SIGNAL dma_send_reg : STD_LOGIC;
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249
249
250
250
251 -----------------------------------------------------------------------------
251 -----------------------------------------------------------------------------
252 -- DMA
252 -- DMA
253 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
254 SIGNAL dma_send : STD_LOGIC;
254 SIGNAL dma_send : STD_LOGIC;
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 SIGNAL dma_done : STD_LOGIC;
256 SIGNAL dma_done : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261
261
262 -----------------------------------------------------------------------------
262 -----------------------------------------------------------------------------
263 -- DEBUG
263 -- DEBUG
264 -----------------------------------------------------------------------------
264 -----------------------------------------------------------------------------
265 --
265 --
266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
270
270
271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
279
279
280 -----------------------------------------------------------------------------
280 -----------------------------------------------------------------------------
281 -- MS
281 -- MS
282 -----------------------------------------------------------------------------
282 -----------------------------------------------------------------------------
283
283
284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
286 SIGNAL data_ms_valid : STD_LOGIC;
286 SIGNAL data_ms_valid : STD_LOGIC;
287 SIGNAL data_ms_valid_burst : STD_LOGIC;
287 SIGNAL data_ms_valid_burst : STD_LOGIC;
288 SIGNAL data_ms_ren : STD_LOGIC;
288 SIGNAL data_ms_ren : STD_LOGIC;
289 SIGNAL data_ms_done : STD_LOGIC;
289 SIGNAL data_ms_done : STD_LOGIC;
290
290
291 BEGIN
291 BEGIN
292
292
293 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
293 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
294 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
294 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
295
295
296 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
296 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
297 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
297 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
298 END GENERATE all_channel;
298 END GENERATE all_channel;
299
299
300 -----------------------------------------------------------------------------
300 -----------------------------------------------------------------------------
301 lpp_lfr_filter_1 : lpp_lfr_filter
301 lpp_lfr_filter_1 : lpp_lfr_filter
302 GENERIC MAP (
302 GENERIC MAP (
303 Mem_use => Mem_use)
303 Mem_use => Mem_use)
304 PORT MAP (
304 PORT MAP (
305 sample => sample_s,
305 sample => sample_s,
306 sample_val => sample_val,
306 sample_val => sample_val,
307 clk => clk,
307 clk => clk,
308 rstn => rstn,
308 rstn => rstn,
309 data_shaping_SP0 => data_shaping_SP0,
309 data_shaping_SP0 => data_shaping_SP0,
310 data_shaping_SP1 => data_shaping_SP1,
310 data_shaping_SP1 => data_shaping_SP1,
311 data_shaping_R0 => data_shaping_R0,
311 data_shaping_R0 => data_shaping_R0,
312 data_shaping_R1 => data_shaping_R1,
312 data_shaping_R1 => data_shaping_R1,
313 sample_f0_val => sample_f0_val,
313 sample_f0_val => sample_f0_val,
314 sample_f1_val => sample_f1_val,
314 sample_f1_val => sample_f1_val,
315 sample_f2_val => sample_f2_val,
315 sample_f2_val => sample_f2_val,
316 sample_f3_val => sample_f3_val,
316 sample_f3_val => sample_f3_val,
317 sample_f0_wdata => sample_f0_data,
317 sample_f0_wdata => sample_f0_data,
318 sample_f1_wdata => sample_f1_data,
318 sample_f1_wdata => sample_f1_data,
319 sample_f2_wdata => sample_f2_data,
319 sample_f2_wdata => sample_f2_data,
320 sample_f3_wdata => sample_f3_data);
320 sample_f3_wdata => sample_f3_data);
321
321
322 -----------------------------------------------------------------------------
322 -----------------------------------------------------------------------------
323 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
323 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
324 GENERIC MAP (
324 GENERIC MAP (
325 nb_data_by_buffer_size => nb_data_by_buffer_size,
325 nb_data_by_buffer_size => nb_data_by_buffer_size,
326 nb_word_by_buffer_size => nb_word_by_buffer_size,
326 nb_word_by_buffer_size => nb_word_by_buffer_size,
327 nb_snapshot_param_size => nb_snapshot_param_size,
327 nb_snapshot_param_size => nb_snapshot_param_size,
328 delta_vector_size => delta_vector_size,
328 delta_vector_size => delta_vector_size,
329 delta_vector_size_f0_2 => delta_vector_size_f0_2,
329 delta_vector_size_f0_2 => delta_vector_size_f0_2,
330 pindex => pindex,
330 pindex => pindex,
331 paddr => paddr,
331 paddr => paddr,
332 pmask => pmask,
332 pmask => pmask,
333 pirq_ms => pirq_ms,
333 pirq_ms => pirq_ms,
334 pirq_wfp => pirq_wfp,
334 pirq_wfp => pirq_wfp,
335 top_lfr_version => top_lfr_version)
335 top_lfr_version => top_lfr_version)
336 PORT MAP (
336 PORT MAP (
337 HCLK => clk,
337 HCLK => clk,
338 HRESETn => rstn,
338 HRESETn => rstn,
339 apbi => apbi,
339 apbi => apbi,
340 apbo => apbo,
340 apbo => apbo,
341 ready_matrix_f0_0 => ready_matrix_f0_0,
341 ready_matrix_f0_0 => ready_matrix_f0_0,
342 ready_matrix_f0_1 => ready_matrix_f0_1,
342 ready_matrix_f0_1 => ready_matrix_f0_1,
343 ready_matrix_f1 => ready_matrix_f1,
343 ready_matrix_f1 => ready_matrix_f1,
344 ready_matrix_f2 => ready_matrix_f2,
344 ready_matrix_f2 => ready_matrix_f2,
345 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
345 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
346 error_bad_component_error => error_bad_component_error,
346 error_bad_component_error => error_bad_component_error,
347 debug_reg => debug_reg,
347 debug_reg => debug_reg,
348 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
348 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
349 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
349 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
350 status_ready_matrix_f1 => status_ready_matrix_f1,
350 status_ready_matrix_f1 => status_ready_matrix_f1,
351 status_ready_matrix_f2 => status_ready_matrix_f2,
351 status_ready_matrix_f2 => status_ready_matrix_f2,
352 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
352 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
353 status_error_bad_component_error => status_error_bad_component_error,
353 status_error_bad_component_error => status_error_bad_component_error,
354 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
354 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
355 config_active_interruption_onError => config_active_interruption_onError,
355 config_active_interruption_onError => config_active_interruption_onError,
356 addr_matrix_f0_0 => addr_matrix_f0_0,
356 addr_matrix_f0_0 => addr_matrix_f0_0,
357 addr_matrix_f0_1 => addr_matrix_f0_1,
357 addr_matrix_f0_1 => addr_matrix_f0_1,
358 addr_matrix_f1 => addr_matrix_f1,
358 addr_matrix_f1 => addr_matrix_f1,
359 addr_matrix_f2 => addr_matrix_f2,
359 addr_matrix_f2 => addr_matrix_f2,
360 status_full => status_full,
360 status_full => status_full,
361 status_full_ack => status_full_ack,
361 status_full_ack => status_full_ack,
362 status_full_err => status_full_err,
362 status_full_err => status_full_err,
363 status_new_err => status_new_err,
363 status_new_err => status_new_err,
364 data_shaping_BW => data_shaping_BW,
364 data_shaping_BW => data_shaping_BW,
365 data_shaping_SP0 => data_shaping_SP0,
365 data_shaping_SP0 => data_shaping_SP0,
366 data_shaping_SP1 => data_shaping_SP1,
366 data_shaping_SP1 => data_shaping_SP1,
367 data_shaping_R0 => data_shaping_R0,
367 data_shaping_R0 => data_shaping_R0,
368 data_shaping_R1 => data_shaping_R1,
368 data_shaping_R1 => data_shaping_R1,
369 delta_snapshot => delta_snapshot,
369 delta_snapshot => delta_snapshot,
370 delta_f0 => delta_f0,
370 delta_f0 => delta_f0,
371 delta_f0_2 => delta_f0_2,
371 delta_f0_2 => delta_f0_2,
372 delta_f1 => delta_f1,
372 delta_f1 => delta_f1,
373 delta_f2 => delta_f2,
373 delta_f2 => delta_f2,
374 nb_data_by_buffer => nb_data_by_buffer,
374 nb_data_by_buffer => nb_data_by_buffer,
375 nb_word_by_buffer => nb_word_by_buffer,
375 nb_word_by_buffer => nb_word_by_buffer,
376 nb_snapshot_param => nb_snapshot_param,
376 nb_snapshot_param => nb_snapshot_param,
377 enable_f0 => enable_f0,
377 enable_f0 => enable_f0,
378 enable_f1 => enable_f1,
378 enable_f1 => enable_f1,
379 enable_f2 => enable_f2,
379 enable_f2 => enable_f2,
380 enable_f3 => enable_f3,
380 enable_f3 => enable_f3,
381 burst_f0 => burst_f0,
381 burst_f0 => burst_f0,
382 burst_f1 => burst_f1,
382 burst_f1 => burst_f1,
383 burst_f2 => burst_f2,
383 burst_f2 => burst_f2,
384 run => run,
384 run => run,
385 addr_data_f0 => addr_data_f0,
385 addr_data_f0 => addr_data_f0,
386 addr_data_f1 => addr_data_f1,
386 addr_data_f1 => addr_data_f1,
387 addr_data_f2 => addr_data_f2,
387 addr_data_f2 => addr_data_f2,
388 addr_data_f3 => addr_data_f3,
388 addr_data_f3 => addr_data_f3,
389 start_date => start_date,
389 start_date => start_date,
390 ---------------------------------------------------------------------------
390 ---------------------------------------------------------------------------
391 debug_reg0 => debug_reg0,
391 debug_reg0 => debug_reg0,
392 debug_reg1 => debug_reg1,
392 debug_reg1 => debug_reg1,
393 debug_reg2 => debug_reg2,
393 debug_reg2 => debug_reg2,
394 debug_reg3 => debug_reg3,
394 debug_reg3 => debug_reg3,
395 debug_reg4 => debug_reg4,
395 debug_reg4 => debug_reg4,
396 debug_reg5 => debug_reg5,
396 debug_reg5 => debug_reg5,
397 debug_reg6 => debug_reg6,
397 debug_reg6 => debug_reg6,
398 debug_reg7 => debug_reg7);
398 debug_reg7 => debug_reg7);
399
399
400 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
400 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
401 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
401 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
402 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
402 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
403 -----------------------------------------------------------------------------
403 -----------------------------------------------------------------------------
404 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
404 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
405 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
405 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
406 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
406 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
407 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
407 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
408
408
409
409
410 -----------------------------------------------------------------------------
410 -----------------------------------------------------------------------------
411 lpp_waveform_1 : lpp_waveform
411 lpp_waveform_1 : lpp_waveform
412 GENERIC MAP (
412 GENERIC MAP (
413 tech => inferred,
413 tech => inferred,
414 data_size => 6*16,
414 data_size => 6*16,
415 nb_data_by_buffer_size => nb_data_by_buffer_size,
415 nb_data_by_buffer_size => nb_data_by_buffer_size,
416 nb_word_by_buffer_size => nb_word_by_buffer_size,
416 nb_word_by_buffer_size => nb_word_by_buffer_size,
417 nb_snapshot_param_size => nb_snapshot_param_size,
417 nb_snapshot_param_size => nb_snapshot_param_size,
418 delta_vector_size => delta_vector_size,
418 delta_vector_size => delta_vector_size,
419 delta_vector_size_f0_2 => delta_vector_size_f0_2
419 delta_vector_size_f0_2 => delta_vector_size_f0_2
420 )
420 )
421 PORT MAP (
421 PORT MAP (
422 clk => clk,
422 clk => clk,
423 rstn => rstn,
423 rstn => rstn,
424
424
425 reg_run => run,
425 reg_run => run,
426 reg_start_date => start_date,
426 reg_start_date => start_date,
427 reg_delta_snapshot => delta_snapshot,
427 reg_delta_snapshot => delta_snapshot,
428 reg_delta_f0 => delta_f0,
428 reg_delta_f0 => delta_f0,
429 reg_delta_f0_2 => delta_f0_2,
429 reg_delta_f0_2 => delta_f0_2,
430 reg_delta_f1 => delta_f1,
430 reg_delta_f1 => delta_f1,
431 reg_delta_f2 => delta_f2,
431 reg_delta_f2 => delta_f2,
432
432
433 enable_f0 => enable_f0,
433 enable_f0 => enable_f0,
434 enable_f1 => enable_f1,
434 enable_f1 => enable_f1,
435 enable_f2 => enable_f2,
435 enable_f2 => enable_f2,
436 enable_f3 => enable_f3,
436 enable_f3 => enable_f3,
437 burst_f0 => burst_f0,
437 burst_f0 => burst_f0,
438 burst_f1 => burst_f1,
438 burst_f1 => burst_f1,
439 burst_f2 => burst_f2,
439 burst_f2 => burst_f2,
440
440
441 nb_data_by_buffer => nb_data_by_buffer,
441 nb_data_by_buffer => nb_data_by_buffer,
442 nb_word_by_buffer => nb_word_by_buffer,
442 nb_word_by_buffer => nb_word_by_buffer,
443 nb_snapshot_param => nb_snapshot_param,
443 nb_snapshot_param => nb_snapshot_param,
444 status_full => status_full,
444 status_full => status_full,
445 status_full_ack => status_full_ack,
445 status_full_ack => status_full_ack,
446 status_full_err => status_full_err,
446 status_full_err => status_full_err,
447 status_new_err => status_new_err,
447 status_new_err => status_new_err,
448
448
449 coarse_time => coarse_time,
449 coarse_time => coarse_time,
450 fine_time => fine_time,
450 fine_time => fine_time,
451
451
452 --f0
452 --f0
453 addr_data_f0 => addr_data_f0,
453 addr_data_f0 => addr_data_f0,
454 data_f0_in_valid => sample_f0_val,
454 data_f0_in_valid => sample_f0_val,
455 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
455 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
456 --f1
456 --f1
457 addr_data_f1 => addr_data_f1,
457 addr_data_f1 => addr_data_f1,
458 data_f1_in_valid => sample_f1_val,
458 data_f1_in_valid => sample_f1_val,
459 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
459 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
460 --f2
460 --f2
461 addr_data_f2 => addr_data_f2,
461 addr_data_f2 => addr_data_f2,
462 data_f2_in_valid => sample_f2_val,
462 data_f2_in_valid => sample_f2_val,
463 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
463 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
464 --f3
464 --f3
465 addr_data_f3 => addr_data_f3,
465 addr_data_f3 => addr_data_f3,
466 data_f3_in_valid => sample_f3_val,
466 data_f3_in_valid => sample_f3_val,
467 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
467 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
468 -- OUTPUT -- DMA interface
468 -- OUTPUT -- DMA interface
469 --f0
469 --f0
470 data_f0_addr_out => data_f0_addr_out_s,
470 data_f0_addr_out => data_f0_addr_out_s,
471 data_f0_data_out => data_f0_data_out,
471 data_f0_data_out => data_f0_data_out,
472 data_f0_data_out_valid => data_f0_data_out_valid_s,
472 data_f0_data_out_valid => data_f0_data_out_valid_s,
473 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
473 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
474 data_f0_data_out_ren => data_f0_data_out_ren,
474 data_f0_data_out_ren => data_f0_data_out_ren,
475 --f1
475 --f1
476 data_f1_addr_out => data_f1_addr_out_s,
476 data_f1_addr_out => data_f1_addr_out_s,
477 data_f1_data_out => data_f1_data_out,
477 data_f1_data_out => data_f1_data_out,
478 data_f1_data_out_valid => data_f1_data_out_valid_s,
478 data_f1_data_out_valid => data_f1_data_out_valid_s,
479 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
479 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
480 data_f1_data_out_ren => data_f1_data_out_ren,
480 data_f1_data_out_ren => data_f1_data_out_ren,
481 --f2
481 --f2
482 data_f2_addr_out => data_f2_addr_out_s,
482 data_f2_addr_out => data_f2_addr_out_s,
483 data_f2_data_out => data_f2_data_out,
483 data_f2_data_out => data_f2_data_out,
484 data_f2_data_out_valid => data_f2_data_out_valid_s,
484 data_f2_data_out_valid => data_f2_data_out_valid_s,
485 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
485 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
486 data_f2_data_out_ren => data_f2_data_out_ren,
486 data_f2_data_out_ren => data_f2_data_out_ren,
487 --f3
487 --f3
488 data_f3_addr_out => data_f3_addr_out_s,
488 data_f3_addr_out => data_f3_addr_out_s,
489 data_f3_data_out => data_f3_data_out,
489 data_f3_data_out => data_f3_data_out,
490 data_f3_data_out_valid => data_f3_data_out_valid_s,
490 data_f3_data_out_valid => data_f3_data_out_valid_s,
491 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
491 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
492 data_f3_data_out_ren => data_f3_data_out_ren --,
492 data_f3_data_out_ren => data_f3_data_out_ren ,
493
493
494 -------------------------------------------------------------------------
494 -------------------------------------------------------------------------
495 observation_reg => observation_reg
495 observation_reg => observation_reg
496 ---- debug SNAPSHOT_OUT
496 ---- debug SNAPSHOT_OUT
497 --debug_f0_data => debug_f0_data,
497 --debug_f0_data => debug_f0_data,
498 --debug_f0_data_valid => debug_f0_data_valid ,
498 --debug_f0_data_valid => debug_f0_data_valid ,
499 --debug_f1_data => debug_f1_data ,
499 --debug_f1_data => debug_f1_data ,
500 --debug_f1_data_valid => debug_f1_data_valid,
500 --debug_f1_data_valid => debug_f1_data_valid,
501 --debug_f2_data => debug_f2_data ,
501 --debug_f2_data => debug_f2_data ,
502 --debug_f2_data_valid => debug_f2_data_valid ,
502 --debug_f2_data_valid => debug_f2_data_valid ,
503 --debug_f3_data => debug_f3_data ,
503 --debug_f3_data => debug_f3_data ,
504 --debug_f3_data_valid => debug_f3_data_valid,
504 --debug_f3_data_valid => debug_f3_data_valid,
505
505
506 ---- debug FIFO_IN
506 ---- debug FIFO_IN
507 --debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
507 --debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
508 --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
508 --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
509 --debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
509 --debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
510 --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
510 --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
511 --debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
511 --debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
512 --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
512 --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
513 --debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
513 --debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
514 --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
514 --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
515
515
516 );
516 );
517
517
518
518
519 -----------------------------------------------------------------------------
519 -----------------------------------------------------------------------------
520 -- DEBUG -- WFP OUT
520 -- DEBUG -- WFP OUT
521 --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
521 --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
522 --debug_f0_data_fifo_out <= data_f0_data_out;
522 --debug_f0_data_fifo_out <= data_f0_data_out;
523 --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
523 --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
524 --debug_f1_data_fifo_out <= data_f1_data_out;
524 --debug_f1_data_fifo_out <= data_f1_data_out;
525 --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
525 --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
526 --debug_f2_data_fifo_out <= data_f2_data_out;
526 --debug_f2_data_fifo_out <= data_f2_data_out;
527 --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
527 --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
528 --debug_f3_data_fifo_out <= data_f3_data_out;
528 --debug_f3_data_fifo_out <= data_f3_data_out;
529 -----------------------------------------------------------------------------
529 -----------------------------------------------------------------------------
530
530
531
531
532 -----------------------------------------------------------------------------
532 -----------------------------------------------------------------------------
533 -- TEMP
533 -- TEMP
534 -----------------------------------------------------------------------------
534 -----------------------------------------------------------------------------
535
535
536 PROCESS (clk, rstn)
536 PROCESS (clk, rstn)
537 BEGIN -- PROCESS
537 BEGIN -- PROCESS
538 IF rstn = '0' THEN -- asynchronous reset (active low)
538 IF rstn = '0' THEN -- asynchronous reset (active low)
539 data_f0_data_out_valid <= '0';
539 data_f0_data_out_valid <= '0';
540 data_f0_data_out_valid_burst <= '0';
540 data_f0_data_out_valid_burst <= '0';
541 data_f1_data_out_valid <= '0';
541 data_f1_data_out_valid <= '0';
542 data_f1_data_out_valid_burst <= '0';
542 data_f1_data_out_valid_burst <= '0';
543 data_f2_data_out_valid <= '0';
543 data_f2_data_out_valid <= '0';
544 data_f2_data_out_valid_burst <= '0';
544 data_f2_data_out_valid_burst <= '0';
545 data_f3_data_out_valid <= '0';
545 data_f3_data_out_valid <= '0';
546 data_f3_data_out_valid_burst <= '0';
546 data_f3_data_out_valid_burst <= '0';
547 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
547 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
548 data_f0_data_out_valid <= data_f0_data_out_valid_s;
548 data_f0_data_out_valid <= data_f0_data_out_valid_s;
549 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
549 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
550 data_f1_data_out_valid <= data_f1_data_out_valid_s;
550 data_f1_data_out_valid <= data_f1_data_out_valid_s;
551 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
551 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
552 data_f2_data_out_valid <= data_f2_data_out_valid_s;
552 data_f2_data_out_valid <= data_f2_data_out_valid_s;
553 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
553 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
554 data_f3_data_out_valid <= data_f3_data_out_valid_s;
554 data_f3_data_out_valid <= data_f3_data_out_valid_s;
555 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
555 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
556 END IF;
556 END IF;
557 END PROCESS;
557 END PROCESS;
558
558
559 data_f0_addr_out <= data_f0_addr_out_s;
559 data_f0_addr_out <= data_f0_addr_out_s;
560 data_f1_addr_out <= data_f1_addr_out_s;
560 data_f1_addr_out <= data_f1_addr_out_s;
561 data_f2_addr_out <= data_f2_addr_out_s;
561 data_f2_addr_out <= data_f2_addr_out_s;
562 data_f3_addr_out <= data_f3_addr_out_s;
562 data_f3_addr_out <= data_f3_addr_out_s;
563
563
564 -----------------------------------------------------------------------------
564 -----------------------------------------------------------------------------
565 -- RoundRobin Selection For DMA
565 -- RoundRobin Selection For DMA
566 -----------------------------------------------------------------------------
566 -----------------------------------------------------------------------------
567
567
568 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
568 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
569 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
569 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
570 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
570 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
571 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
571 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
572
572
573 RR_Arbiter_4_1 : RR_Arbiter_4
573 RR_Arbiter_4_1 : RR_Arbiter_4
574 PORT MAP (
574 PORT MAP (
575 clk => clk,
575 clk => clk,
576 rstn => rstn,
576 rstn => rstn,
577 in_valid => dma_rr_valid,
577 in_valid => dma_rr_valid,
578 out_grant => dma_rr_grant_s);
578 out_grant => dma_rr_grant_s);
579
579
580 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
580 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
581 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
581 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
582 dma_rr_valid_ms(2) <= '0';
582 dma_rr_valid_ms(2) <= '0';
583 dma_rr_valid_ms(3) <= '0';
583 dma_rr_valid_ms(3) <= '0';
584
584
585 RR_Arbiter_4_2 : RR_Arbiter_4
585 RR_Arbiter_4_2 : RR_Arbiter_4
586 PORT MAP (
586 PORT MAP (
587 clk => clk,
587 clk => clk,
588 rstn => rstn,
588 rstn => rstn,
589 in_valid => dma_rr_valid_ms,
589 in_valid => dma_rr_valid_ms,
590 out_grant => dma_rr_grant_ms);
590 out_grant => dma_rr_grant_ms);
591
591
592 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
592 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
593
593
594
594
595 -----------------------------------------------------------------------------
595 -----------------------------------------------------------------------------
596 -- in : dma_rr_grant
596 -- in : dma_rr_grant
597 -- send
597 -- send
598 -- out : dma_sel
598 -- out : dma_sel
599 -- dma_valid_burst
599 -- dma_valid_burst
600 -- dma_sel_valid
600 -- dma_sel_valid
601 -----------------------------------------------------------------------------
601 -----------------------------------------------------------------------------
602 PROCESS (clk, rstn)
602 PROCESS (clk, rstn)
603 BEGIN -- PROCESS
603 BEGIN -- PROCESS
604 IF rstn = '0' THEN -- asynchronous reset (active low)
604 IF rstn = '0' THEN -- asynchronous reset (active low)
605 dma_sel <= (OTHERS => '0');
605 dma_sel <= (OTHERS => '0');
606 dma_send <= '0';
606 dma_send <= '0';
607 dma_valid_burst <= '0';
607 dma_valid_burst <= '0';
608 data_ms_done <= '0';
608 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
609 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
609 IF run = '1' THEN
610 IF run = '1' THEN
611 data_ms_done <= '0';
610 IF dma_sel = "00000" OR dma_done = '1' THEN
612 IF dma_sel = "00000" OR dma_done = '1' THEN
611 dma_sel <= dma_rr_grant;
613 dma_sel <= dma_rr_grant;
612 IF dma_rr_grant(0) = '1' THEN
614 IF dma_rr_grant(0) = '1' THEN
613 dma_send <= '1';
615 dma_send <= '1';
614 dma_valid_burst <= data_f0_data_out_valid_burst;
616 dma_valid_burst <= data_f0_data_out_valid_burst;
615 dma_sel_valid <= data_f0_data_out_valid;
617 dma_sel_valid <= data_f0_data_out_valid;
616 ELSIF dma_rr_grant(1) = '1' THEN
618 ELSIF dma_rr_grant(1) = '1' THEN
617 dma_send <= '1';
619 dma_send <= '1';
618 dma_valid_burst <= data_f1_data_out_valid_burst;
620 dma_valid_burst <= data_f1_data_out_valid_burst;
619 dma_sel_valid <= data_f1_data_out_valid;
621 dma_sel_valid <= data_f1_data_out_valid;
620 ELSIF dma_rr_grant(2) = '1' THEN
622 ELSIF dma_rr_grant(2) = '1' THEN
621 dma_send <= '1';
623 dma_send <= '1';
622 dma_valid_burst <= data_f2_data_out_valid_burst;
624 dma_valid_burst <= data_f2_data_out_valid_burst;
623 dma_sel_valid <= data_f2_data_out_valid;
625 dma_sel_valid <= data_f2_data_out_valid;
624 ELSIF dma_rr_grant(3) = '1' THEN
626 ELSIF dma_rr_grant(3) = '1' THEN
625 dma_send <= '1';
627 dma_send <= '1';
626 dma_valid_burst <= data_f3_data_out_valid_burst;
628 dma_valid_burst <= data_f3_data_out_valid_burst;
627 dma_sel_valid <= data_f3_data_out_valid;
629 dma_sel_valid <= data_f3_data_out_valid;
628 ELSIF dma_rr_grant(4) = '1' THEN
630 ELSIF dma_rr_grant(4) = '1' THEN
629 dma_send <= '1';
631 dma_send <= '1';
630 dma_valid_burst <= data_ms_valid_burst;
632 dma_valid_burst <= data_ms_valid_burst;
631 dma_sel_valid <= data_ms_valid;
633 dma_sel_valid <= data_ms_valid;
632 END IF;
634 END IF;
633
635
634 IF dma_sel(4) = '1' THEN
636 IF dma_sel(4) = '1' THEN
635 data_ms_done <= '1';
637 data_ms_done <= '1';
636 END IF;
638 END IF;
637 ELSE
639 ELSE
638 dma_sel <= dma_sel;
640 dma_sel <= dma_sel;
639 dma_send <= '0';
641 dma_send <= '0';
640 END IF;
642 END IF;
641 ELSE
643 ELSE
644 data_ms_done <= '0';
642 dma_sel <= (OTHERS => '0');
645 dma_sel <= (OTHERS => '0');
643 dma_send <= '0';
646 dma_send <= '0';
644 dma_valid_burst <= '0';
647 dma_valid_burst <= '0';
645 END IF;
648 END IF;
646 END IF;
649 END IF;
647 END PROCESS;
650 END PROCESS;
648
651
649
652
650 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
653 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
651 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
654 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
652 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
655 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
653 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
656 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
654 data_ms_addr;
657 data_ms_addr;
655
658
656 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
659 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
657 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
660 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
658 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
661 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
659 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
662 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
660 data_ms_data;
663 data_ms_data;
661
664
662 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
665 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
663 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
666 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
664 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
667 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
665 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
668 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
666 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
669 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
667
670
668 dma_data_2 <= dma_data;
671 dma_data_2 <= dma_data;
669
672
670
673
671
674
672
675
673
676
674 -----------------------------------------------------------------------------
677 -----------------------------------------------------------------------------
675 -- DEBUG -- DMA IN
678 -- DEBUG -- DMA IN
676 --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
679 --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
677 --debug_f0_data_dma_in <= dma_data;
680 --debug_f0_data_dma_in <= dma_data;
678 --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
681 --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
679 --debug_f1_data_dma_in <= dma_data;
682 --debug_f1_data_dma_in <= dma_data;
680 --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
683 --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
681 --debug_f2_data_dma_in <= dma_data;
684 --debug_f2_data_dma_in <= dma_data;
682 --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
685 --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
683 --debug_f3_data_dma_in <= dma_data;
686 --debug_f3_data_dma_in <= dma_data;
684 -----------------------------------------------------------------------------
687 -----------------------------------------------------------------------------
685
688
686 -----------------------------------------------------------------------------
689 -----------------------------------------------------------------------------
687 -- DMA
690 -- DMA
688 -----------------------------------------------------------------------------
691 -----------------------------------------------------------------------------
689 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
692 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
690 GENERIC MAP (
693 GENERIC MAP (
691 tech => inferred,
694 tech => inferred,
692 hindex => hindex)
695 hindex => hindex)
693 PORT MAP (
696 PORT MAP (
694 HCLK => clk,
697 HCLK => clk,
695 HRESETn => rstn,
698 HRESETn => rstn,
696 run => run,
699 run => run,
697 AHB_Master_In => ahbi,
700 AHB_Master_In => ahbi,
698 AHB_Master_Out => ahbo,
701 AHB_Master_Out => ahbo,
699
702
700 send => dma_send,
703 send => dma_send,
701 valid_burst => dma_valid_burst,
704 valid_burst => dma_valid_burst,
702 done => dma_done,
705 done => dma_done,
703 ren => dma_ren,
706 ren => dma_ren,
704 address => dma_address,
707 address => dma_address,
705 data => dma_data_2);
708 data => dma_data_2);
706
709
707 -----------------------------------------------------------------------------
710 -----------------------------------------------------------------------------
708 -- Matrix Spectral
711 -- Matrix Spectral
709 -----------------------------------------------------------------------------
712 -----------------------------------------------------------------------------
710 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
713 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
711 NOT(sample_f0_val) & NOT(sample_f0_val) ;
714 NOT(sample_f0_val) & NOT(sample_f0_val) ;
712 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
715 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
713 NOT(sample_f1_val) & NOT(sample_f1_val) ;
716 NOT(sample_f1_val) & NOT(sample_f1_val) ;
714 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
717 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
715 NOT(sample_f3_val) & NOT(sample_f3_val) ;
718 NOT(sample_f3_val) & NOT(sample_f3_val) ;
716
719
717 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
720 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
718 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
721 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
719 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
722 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
723
720 -------------------------------------------------------------------------------
724 -------------------------------------------------------------------------------
721 lpp_lfr_ms_1: lpp_lfr_ms
725 lpp_lfr_ms_1: lpp_lfr_ms
722 GENERIC MAP (
726 GENERIC MAP (
723 Mem_use => Mem_use )
727 Mem_use => Mem_use )
724 PORT MAP (
728 PORT MAP (
725 clk => clk,
729 clk => clk,
726 rstn => rstn,
730 rstn => rstn,
727
731
732 coarse_time => coarse_time,
733 fine_time => fine_time,
734
728 sample_f0_wen => sample_f0_wen,
735 sample_f0_wen => sample_f0_wen,
729 sample_f0_wdata => sample_f0_wdata,
736 sample_f0_wdata => sample_f0_wdata,
730 sample_f1_wen => sample_f1_wen,
737 sample_f1_wen => sample_f1_wen,
731 sample_f1_wdata => sample_f1_wdata,
738 sample_f1_wdata => sample_f1_wdata,
732 sample_f3_wen => sample_f3_wen,
739 sample_f3_wen => sample_f3_wen,
733 sample_f3_wdata => sample_f3_wdata,
740 sample_f3_wdata => sample_f3_wdata,
734
741
735 dma_addr => data_ms_addr, --
742 dma_addr => data_ms_addr, --
736 dma_data => data_ms_data, --
743 dma_data => data_ms_data, --
737 dma_valid => data_ms_valid, --
744 dma_valid => data_ms_valid, --
738 dma_valid_burst => data_ms_valid_burst, --
745 dma_valid_burst => data_ms_valid_burst, --
739 dma_ren => data_ms_ren, --
746 dma_ren => data_ms_ren, --
740 dma_done => data_ms_done, --
747 dma_done => data_ms_done, --
741
748
742 ready_matrix_f0_0 => ready_matrix_f0_0,
749 ready_matrix_f0_0 => ready_matrix_f0_0,
743 ready_matrix_f0_1 => ready_matrix_f0_1,
750 ready_matrix_f0_1 => ready_matrix_f0_1,
744 ready_matrix_f1 => ready_matrix_f1,
751 ready_matrix_f1 => ready_matrix_f1,
745 ready_matrix_f2 => ready_matrix_f2,
752 ready_matrix_f2 => ready_matrix_f2,
746 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
753 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
747 error_bad_component_error => error_bad_component_error,
754 error_bad_component_error => error_bad_component_error,
748 debug_reg => debug_reg,
755 debug_reg => debug_reg,
749 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
756 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
750 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
757 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
751 status_ready_matrix_f1 => status_ready_matrix_f1,
758 status_ready_matrix_f1 => status_ready_matrix_f1,
752 status_ready_matrix_f2 => status_ready_matrix_f2,
759 status_ready_matrix_f2 => status_ready_matrix_f2,
753 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
760 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
754 status_error_bad_component_error => status_error_bad_component_error,
761 status_error_bad_component_error => status_error_bad_component_error,
755 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
762 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
756 config_active_interruption_onError => config_active_interruption_onError,
763 config_active_interruption_onError => config_active_interruption_onError,
757 addr_matrix_f0_0 => addr_matrix_f0_0,
764 addr_matrix_f0_0 => addr_matrix_f0_0,
758 addr_matrix_f0_1 => addr_matrix_f0_1,
765 addr_matrix_f0_1 => addr_matrix_f0_1,
759 addr_matrix_f1 => addr_matrix_f1,
766 addr_matrix_f1 => addr_matrix_f1,
760 addr_matrix_f2 => addr_matrix_f2);
767 addr_matrix_f2 => addr_matrix_f2);
761
768
762 END beh;
769 END beh;
Show file before | Show file after | Hide comments
@@ -1,393 +1,402
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY lpp;
4 LIBRARY lpp;
5 USE lpp.lpp_amba.ALL;
5 USE lpp.lpp_amba.ALL;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 --USE lpp.lpp_uart.ALL;
7 --USE lpp.lpp_uart.ALL;
8 USE lpp.lpp_matrix.ALL;
8 USE lpp.lpp_matrix.ALL;
9 --USE lpp.lpp_delay.ALL;
9 --USE lpp.lpp_delay.ALL;
10 USE lpp.lpp_fft.ALL;
10 USE lpp.lpp_fft.ALL;
11 USE lpp.fft_components.ALL;
11 USE lpp.fft_components.ALL;
12 USE lpp.lpp_ad_conv.ALL;
12 USE lpp.lpp_ad_conv.ALL;
13 USE lpp.iir_filter.ALL;
13 USE lpp.iir_filter.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15 USE lpp.Filtercfg.ALL;
15 USE lpp.Filtercfg.ALL;
16 USE lpp.lpp_demux.ALL;
16 USE lpp.lpp_demux.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
19 USE lpp.lpp_Header.ALL;
19 USE lpp.lpp_Header.ALL;
20 USE lpp.lpp_lfr_pkg.ALL;
20 USE lpp.lpp_lfr_pkg.ALL;
21
21
22 LIBRARY grlib;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
25 USE grlib.devices.ALL;
26 USE GRLIB.DMA2AHB_Package.ALL;
26 USE GRLIB.DMA2AHB_Package.ALL;
27
27
28
28
29 ENTITY lpp_lfr_ms IS
29 ENTITY lpp_lfr_ms IS
30 GENERIC (
30 GENERIC (
31 Mem_use : INTEGER
31 Mem_use : INTEGER
32 );
32 );
33 PORT (
33 PORT (
34 clk : IN STD_LOGIC;
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36
36
37 ---------------------------------------------------------------------------
37 ---------------------------------------------------------------------------
38 -- DATA INPUT
38 -- DATA INPUT
39 ---------------------------------------------------------------------------
39 ---------------------------------------------------------------------------
40 -- TIME
41 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
42 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
40 --
43 --
41 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
45 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
43 --
46 --
44 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
45 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
46 --
49 --
47 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
50 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
51 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
52
50 ---------------------------------------------------------------------------
53 ---------------------------------------------------------------------------
51 -- DMA
54 -- DMA
52 ---------------------------------------------------------------------------
55 ---------------------------------------------------------------------------
53 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
54 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
57 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
55 dma_valid : OUT STD_LOGIC;
58 dma_valid : OUT STD_LOGIC;
56 dma_valid_burst : OUT STD_LOGIC;
59 dma_valid_burst : OUT STD_LOGIC;
57 dma_ren : IN STD_LOGIC;
60 dma_ren : IN STD_LOGIC;
58 dma_done : IN STD_LOGIC;
61 dma_done : IN STD_LOGIC;
59
62
60 -- Reg out
63 -- Reg out
61 ready_matrix_f0_0 : OUT STD_LOGIC;
64 ready_matrix_f0_0 : OUT STD_LOGIC;
62 ready_matrix_f0_1 : OUT STD_LOGIC;
65 ready_matrix_f0_1 : OUT STD_LOGIC;
63 ready_matrix_f1 : OUT STD_LOGIC;
66 ready_matrix_f1 : OUT STD_LOGIC;
64 ready_matrix_f2 : OUT STD_LOGIC;
67 ready_matrix_f2 : OUT STD_LOGIC;
65 error_anticipating_empty_fifo : OUT STD_LOGIC;
68 error_anticipating_empty_fifo : OUT STD_LOGIC;
66 error_bad_component_error : OUT STD_LOGIC;
69 error_bad_component_error : OUT STD_LOGIC;
67 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
70 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68
71
69 -- Reg In
72 -- Reg In
70 status_ready_matrix_f0_0 :IN STD_LOGIC;
73 status_ready_matrix_f0_0 :IN STD_LOGIC;
71 status_ready_matrix_f0_1 :IN STD_LOGIC;
74 status_ready_matrix_f0_1 :IN STD_LOGIC;
72 status_ready_matrix_f1 :IN STD_LOGIC;
75 status_ready_matrix_f1 :IN STD_LOGIC;
73 status_ready_matrix_f2 :IN STD_LOGIC;
76 status_ready_matrix_f2 :IN STD_LOGIC;
74 status_error_anticipating_empty_fifo :IN STD_LOGIC;
77 status_error_anticipating_empty_fifo :IN STD_LOGIC;
75 status_error_bad_component_error :IN STD_LOGIC;
78 status_error_bad_component_error :IN STD_LOGIC;
76
79
77 config_active_interruption_onNewMatrix : IN STD_LOGIC;
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
78 config_active_interruption_onError : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
79 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
85 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
83 );
86 );
84 END;
87 END;
85
88
86 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
89 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
87 -----------------------------------------------------------------------------
90 -----------------------------------------------------------------------------
88 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
94 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
92 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
95 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
93 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
96 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
94
97
95 -----------------------------------------------------------------------------
98 -----------------------------------------------------------------------------
96 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
99 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
97 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
101 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
99 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
102 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
100
103
101 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
102 SIGNAL FFT_Load : STD_LOGIC;
105 SIGNAL FFT_Load : STD_LOGIC;
103 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
108 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
109 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
107
110
108 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
109 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
112 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
113 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
111
114
112 -----------------------------------------------------------------------------
115 -----------------------------------------------------------------------------
113 SIGNAL SM_FlagError : STD_LOGIC;
116 SIGNAL SM_FlagError : STD_LOGIC;
114 -- SIGNAL SM_Pong : STD_LOGIC;
117 -- SIGNAL SM_Pong : STD_LOGIC;
115 SIGNAL SM_Wen : STD_LOGIC;
118 SIGNAL SM_Wen : STD_LOGIC;
116 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
121 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
122 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
120 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
123 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
121
124
122 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
123 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
124 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
128 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
126
129
127 -----------------------------------------------------------------------------
130 -----------------------------------------------------------------------------
128 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
131 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 SIGNAL Head_Empty : STD_LOGIC;
133 SIGNAL Head_Empty : STD_LOGIC;
131 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
134 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL Head_Valid : STD_LOGIC;
135 SIGNAL Head_Valid : STD_LOGIC;
133 SIGNAL Head_Val : STD_LOGIC;
136 SIGNAL Head_Val : STD_LOGIC;
134
137
135 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
136 SIGNAL DMA_Read : STD_LOGIC;
139 SIGNAL DMA_Read : STD_LOGIC;
137 SIGNAL DMA_ack : STD_LOGIC;
140 SIGNAL DMA_ack : STD_LOGIC;
138
141
142 -----------------------------------------------------------------------------
143 SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
144
139 BEGIN
145 BEGIN
140
146
141 -----------------------------------------------------------------------------
147 -----------------------------------------------------------------------------
142 Memf0: lppFIFOxN
148 Memf0: lppFIFOxN
143 GENERIC MAP (
149 GENERIC MAP (
144 tech => 0, Mem_use => Mem_use, Data_sz => 16,
150 tech => 0, Mem_use => Mem_use, Data_sz => 16,
145 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
151 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
146 PORT MAP (
152 PORT MAP (
147 rstn => rstn, wclk => clk, rclk => clk,
153 rstn => rstn, wclk => clk, rclk => clk,
148 ReUse => (OTHERS => '0'),
154 ReUse => (OTHERS => '0'),
149 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
155 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
150 wdata => sample_f0_wdata, rdata => FifoF0_Data,
156 wdata => sample_f0_wdata, rdata => FifoF0_Data,
151 full => OPEN, empty => FifoF0_Empty);
157 full => OPEN, empty => FifoF0_Empty);
152
158
153 Memf1: lppFIFOxN
159 Memf1: lppFIFOxN
154 GENERIC MAP (
160 GENERIC MAP (
155 tech => 0, Mem_use => Mem_use, Data_sz => 16,
161 tech => 0, Mem_use => Mem_use, Data_sz => 16,
156 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
162 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
157 PORT MAP (
163 PORT MAP (
158 rstn => rstn, wclk => clk, rclk => clk,
164 rstn => rstn, wclk => clk, rclk => clk,
159 ReUse => (OTHERS => '0'),
165 ReUse => (OTHERS => '0'),
160 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
166 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
161 wdata => sample_f1_wdata, rdata => FifoF1_Data,
167 wdata => sample_f1_wdata, rdata => FifoF1_Data,
162 full => OPEN, empty => FifoF1_Empty);
168 full => OPEN, empty => FifoF1_Empty);
163
169
164
170
165 Memf2: lppFIFOxN
171 Memf2: lppFIFOxN
166 GENERIC MAP (
172 GENERIC MAP (
167 tech => 0, Mem_use => Mem_use, Data_sz => 16,
173 tech => 0, Mem_use => Mem_use, Data_sz => 16,
168 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
174 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
169 PORT MAP (
175 PORT MAP (
170 rstn => rstn, wclk => clk, rclk => clk,
176 rstn => rstn, wclk => clk, rclk => clk,
171 ReUse => (OTHERS => '0'),
177 ReUse => (OTHERS => '0'),
172 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
178 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
173 wdata => sample_f3_wdata, rdata => FifoF3_Data,
179 wdata => sample_f3_wdata, rdata => FifoF3_Data,
174 full => OPEN, empty => FifoF3_Empty);
180 full => OPEN, empty => FifoF3_Empty);
175 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
176
182
177
183
178 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
179 DMUX0 : DEMUX
185 DMUX0 : DEMUX
180 GENERIC MAP (
186 GENERIC MAP (
181 Data_sz => 16)
187 Data_sz => 16)
182 PORT MAP (
188 PORT MAP (
183 clk => clk,
189 clk => clk,
184 rstn => rstn,
190 rstn => rstn,
185 Read => FFT_Read,
191 Read => FFT_Read,
186 Load => FFT_Load,
192 Load => FFT_Load,
187 EmptyF0 => FifoF0_Empty,
193 EmptyF0 => FifoF0_Empty,
188 EmptyF1 => FifoF1_Empty,
194 EmptyF1 => FifoF1_Empty,
189 EmptyF2 => FifoF3_Empty,
195 EmptyF2 => FifoF3_Empty,
190 DataF0 => FifoF0_Data,
196 DataF0 => FifoF0_Data,
191 DataF1 => FifoF1_Data,
197 DataF1 => FifoF1_Data,
192 DataF2 => FifoF3_Data,
198 DataF2 => FifoF3_Data,
193 WorkFreq => DMUX_WorkFreq,
199 WorkFreq => DMUX_WorkFreq,
194 Read_DEMUX => DMUX_Read,
200 Read_DEMUX => DMUX_Read,
195 Empty => DMUX_Empty,
201 Empty => DMUX_Empty,
196 Data => DMUX_Data);
202 Data => DMUX_Data);
197 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
198
204
199
205
200 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
201 FFT0: FFT
207 FFT0: FFT
202 GENERIC MAP (
208 GENERIC MAP (
203 Data_sz => 16,
209 Data_sz => 16,
204 NbData => 256)
210 NbData => 256)
205 PORT MAP (
211 PORT MAP (
206 clkm => clk,
212 clkm => clk,
207 rstn => rstn,
213 rstn => rstn,
208 FifoIN_Empty => DMUX_Empty,
214 FifoIN_Empty => DMUX_Empty,
209 FifoIN_Data => DMUX_Data,
215 FifoIN_Data => DMUX_Data,
210 FifoOUT_Full => FifoINT_Full,
216 FifoOUT_Full => FifoINT_Full,
211 Load => FFT_Load,
217 Load => FFT_Load,
212 Read => FFT_Read,
218 Read => FFT_Read,
213 Write => FFT_Write,
219 Write => FFT_Write,
214 ReUse => FFT_ReUse,
220 ReUse => FFT_ReUse,
215 Data => FFT_Data);
221 Data => FFT_Data);
216 -----------------------------------------------------------------------------
222 -----------------------------------------------------------------------------
217
223
218
224
219 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
220 MemInt : lppFIFOxN
226 MemInt : lppFIFOxN
221 GENERIC MAP (
227 GENERIC MAP (
222 tech => 0,
228 tech => 0,
223 Mem_use => Mem_use,
229 Mem_use => Mem_use,
224 Data_sz => 16,
230 Data_sz => 16,
225 Addr_sz => 8,
231 Addr_sz => 8,
226 FifoCnt => 5,
232 FifoCnt => 5,
227 Enable_ReUse => '1')
233 Enable_ReUse => '1')
228 PORT MAP (
234 PORT MAP (
229 rstn => rstn,
235 rstn => rstn,
230 wclk => clk,
236 wclk => clk,
231 rclk => clk,
237 rclk => clk,
232 ReUse => SM_ReUse,
238 ReUse => SM_ReUse,
233 wen => FFT_Write,
239 wen => FFT_Write,
234 ren => SM_Read,
240 ren => SM_Read,
235 wdata => FFT_Data,
241 wdata => FFT_Data,
236 rdata => FifoINT_Data,
242 rdata => FifoINT_Data,
237 full => FifoINT_Full,
243 full => FifoINT_Full,
238 empty => OPEN);
244 empty => OPEN);
239 -----------------------------------------------------------------------------
245 -----------------------------------------------------------------------------
240
246
241 -----------------------------------------------------------------------------
247 -----------------------------------------------------------------------------
242 SM0 : MatriceSpectrale
248 SM0 : MatriceSpectrale
243 GENERIC MAP (
249 GENERIC MAP (
244 Input_SZ => 16,
250 Input_SZ => 16,
245 Result_SZ => 32)
251 Result_SZ => 32)
246 PORT MAP (
252 PORT MAP (
247 clkm => clk,
253 clkm => clk,
248 rstn => rstn,
254 rstn => rstn,
249 FifoIN_Full => FifoINT_Full,
255 FifoIN_Full => FifoINT_Full,
250 SetReUse => FFT_ReUse,
256 SetReUse => FFT_ReUse,
251 Valid => Head_Valid,
257 Valid => Head_Valid,
252 Data_IN => FifoINT_Data,
258 Data_IN => FifoINT_Data,
253 ACK => DMA_ack,
259 ACK => DMA_ack,
254 SM_Write => SM_Wen,
260 SM_Write => SM_Wen,
255 FlagError => SM_FlagError,
261 FlagError => SM_FlagError,
256 -- Pong => SM_Pong,
262 -- Pong => SM_Pong,
257 Statu => SM_Param,
263 Statu => SM_Param,
258 Write => SM_Write,
264 Write => SM_Write,
259 Read => SM_Read,
265 Read => SM_Read,
260 ReUse => SM_ReUse,
266 ReUse => SM_ReUse,
261 Data_OUT => SM_Data);
267 Data_OUT => SM_Data);
262 -----------------------------------------------------------------------------
268 -----------------------------------------------------------------------------
263
269
264 -----------------------------------------------------------------------------
270 -----------------------------------------------------------------------------
265 MemOut : lppFIFOxN
271 MemOut : lppFIFOxN
266 GENERIC MAP (
272 GENERIC MAP (
267 tech => 0,
273 tech => 0,
268 Mem_use => Mem_use,
274 Mem_use => Mem_use,
269 Data_sz => 32,
275 Data_sz => 32,
270 Addr_sz => 8,
276 Addr_sz => 8,
271 FifoCnt => 2,
277 FifoCnt => 2,
272 Enable_ReUse => '0')
278 Enable_ReUse => '0')
273 PORT MAP (
279 PORT MAP (
274 rstn => rstn,
280 rstn => rstn,
275 wclk => clk,
281 wclk => clk,
276 rclk => clk,
282 rclk => clk,
277 ReUse => (OTHERS => '0'),
283 ReUse => (OTHERS => '0'),
278 wen => SM_Write,
284 wen => SM_Write,
279 ren => Head_Read,
285 ren => Head_Read,
280 wdata => SM_Data,
286 wdata => SM_Data,
281 rdata => FifoOUT_Data,
287 rdata => FifoOUT_Data,
282 full => FifoOUT_Full,
288 full => FifoOUT_Full,
283 empty => FifoOUT_Empty);
289 empty => FifoOUT_Empty);
284 -----------------------------------------------------------------------------
290 -----------------------------------------------------------------------------
285
291
286 -----------------------------------------------------------------------------
292 -----------------------------------------------------------------------------
287 Head0 : HeaderBuilder
293 Head0 : HeaderBuilder
288 GENERIC MAP (
294 GENERIC MAP (
289 Data_sz => 32)
295 Data_sz => 32)
290 PORT MAP (
296 PORT MAP (
291 clkm => clk,
297 clkm => clk,
292 rstn => rstn,
298 rstn => rstn,
293 -- pong => SM_Pong,
299 -- pong => SM_Pong,
294 Statu => SM_Param,
300 Statu => SM_Param,
295 Matrix_Type => DMUX_WorkFreq,
301 Matrix_Type => DMUX_WorkFreq,
296 Matrix_Write => SM_Wen,
302 Matrix_Write => SM_Wen,
297 Valid => Head_Valid,
303 Valid => Head_Valid,
298 dataIN => FifoOUT_Data,
304 dataIN => FifoOUT_Data,
299 emptyIN => FifoOUT_Empty,
305 emptyIN => FifoOUT_Empty,
300 RenOUT => Head_Read,
306 RenOUT => Head_Read,
301 dataOUT => Head_Data,
307 dataOUT => Head_Data,
302 emptyOUT => Head_Empty,
308 emptyOUT => Head_Empty,
303 RenIN => DMA_Read,
309 RenIN => DMA_Read,
304 header => Head_Header,
310 header => Head_Header,
305 header_val => Head_Val,
311 header_val => Head_Val,
306 header_ack => DMA_ack );
312 header_ack => DMA_ack );
307 -----------------------------------------------------------------------------
313 -----------------------------------------------------------------------------
308
314 data_time(31 DOWNTO 0) <= coarse_time;
315 data_time(47 DOWNTO 32) <= fine_time;
309
316
310 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
317 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
311 PORT MAP (
318 PORT MAP (
312 HCLK => clk,
319 HCLK => clk,
313 HRESETn => rstn,
320 HRESETn => rstn,
314
321
322 data_time => data_time,
323
315 fifo_data => Head_Data,
324 fifo_data => Head_Data,
316 fifo_empty => Head_Empty,
325 fifo_empty => Head_Empty,
317 fifo_ren => DMA_Read,
326 fifo_ren => DMA_Read,
318
327
319 header => Head_Header,
328 header => Head_Header,
320 header_val => Head_Val,
329 header_val => Head_Val,
321 header_ack => DMA_ack,
330 header_ack => DMA_ack,
322
331
323 dma_addr => dma_addr,
332 dma_addr => dma_addr,
324 dma_data => dma_data,
333 dma_data => dma_data,
325 dma_valid => dma_valid,
334 dma_valid => dma_valid,
326 dma_valid_burst => dma_valid_burst,
335 dma_valid_burst => dma_valid_burst,
327 dma_ren => dma_ren,
336 dma_ren => dma_ren,
328 dma_done => dma_done,
337 dma_done => dma_done,
329
338
330 ready_matrix_f0_0 => ready_matrix_f0_0,
339 ready_matrix_f0_0 => ready_matrix_f0_0,
331 ready_matrix_f0_1 => ready_matrix_f0_1,
340 ready_matrix_f0_1 => ready_matrix_f0_1,
332 ready_matrix_f1 => ready_matrix_f1,
341 ready_matrix_f1 => ready_matrix_f1,
333 ready_matrix_f2 => ready_matrix_f2,
342 ready_matrix_f2 => ready_matrix_f2,
334 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
343 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
335 error_bad_component_error => error_bad_component_error,
344 error_bad_component_error => error_bad_component_error,
336 debug_reg => debug_reg,
345 debug_reg => debug_reg,
337 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
346 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
338 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
347 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
339 status_ready_matrix_f1 => status_ready_matrix_f1,
348 status_ready_matrix_f1 => status_ready_matrix_f1,
340 status_ready_matrix_f2 => status_ready_matrix_f2,
349 status_ready_matrix_f2 => status_ready_matrix_f2,
341 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
350 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
342 status_error_bad_component_error => status_error_bad_component_error,
351 status_error_bad_component_error => status_error_bad_component_error,
343 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
352 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
344 config_active_interruption_onError => config_active_interruption_onError,
353 config_active_interruption_onError => config_active_interruption_onError,
345 addr_matrix_f0_0 => addr_matrix_f0_0,
354 addr_matrix_f0_0 => addr_matrix_f0_0,
346 addr_matrix_f0_1 => addr_matrix_f0_1,
355 addr_matrix_f0_1 => addr_matrix_f0_1,
347 addr_matrix_f1 => addr_matrix_f1,
356 addr_matrix_f1 => addr_matrix_f1,
348 addr_matrix_f2 => addr_matrix_f2);
357 addr_matrix_f2 => addr_matrix_f2);
349
358
350
359
351
360
352
361
353 -----------------------------------------------------------------------------
362 -----------------------------------------------------------------------------
354 --lpp_dma_ip_1: lpp_dma_ip
363 --lpp_dma_ip_1: lpp_dma_ip
355 -- GENERIC MAP (
364 -- GENERIC MAP (
356 -- tech => 0,
365 -- tech => 0,
357 -- hindex => hindex)
366 -- hindex => hindex)
358 -- PORT MAP (
367 -- PORT MAP (
359 -- HCLK => clk,
368 -- HCLK => clk,
360 -- HRESETn => rstn,
369 -- HRESETn => rstn,
361 -- AHB_Master_In => AHB_Master_In,
370 -- AHB_Master_In => AHB_Master_In,
362 -- AHB_Master_Out => AHB_Master_Out,
371 -- AHB_Master_Out => AHB_Master_Out,
363
372
364 -- fifo_data => Head_Data,
373 -- fifo_data => Head_Data,
365 -- fifo_empty => Head_Empty,
374 -- fifo_empty => Head_Empty,
366 -- fifo_ren => DMA_Read,
375 -- fifo_ren => DMA_Read,
367
376
368 -- header => Head_Header,
377 -- header => Head_Header,
369 -- header_val => Head_Val,
378 -- header_val => Head_Val,
370 -- header_ack => DMA_ack,
379 -- header_ack => DMA_ack,
371
380
372 -- ready_matrix_f0_0 => ready_matrix_f0_0,
381 -- ready_matrix_f0_0 => ready_matrix_f0_0,
373 -- ready_matrix_f0_1 => ready_matrix_f0_1,
382 -- ready_matrix_f0_1 => ready_matrix_f0_1,
374 -- ready_matrix_f1 => ready_matrix_f1,
383 -- ready_matrix_f1 => ready_matrix_f1,
375 -- ready_matrix_f2 => ready_matrix_f2,
384 -- ready_matrix_f2 => ready_matrix_f2,
376 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
385 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
377 -- error_bad_component_error => error_bad_component_error,
386 -- error_bad_component_error => error_bad_component_error,
378 -- debug_reg => debug_reg,
387 -- debug_reg => debug_reg,
379 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
388 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
380 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
389 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
381 -- status_ready_matrix_f1 => status_ready_matrix_f1,
390 -- status_ready_matrix_f1 => status_ready_matrix_f1,
382 -- status_ready_matrix_f2 => status_ready_matrix_f2,
391 -- status_ready_matrix_f2 => status_ready_matrix_f2,
383 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
392 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
384 -- status_error_bad_component_error => status_error_bad_component_error,
393 -- status_error_bad_component_error => status_error_bad_component_error,
385 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
394 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
386 -- config_active_interruption_onError => config_active_interruption_onError,
395 -- config_active_interruption_onError => config_active_interruption_onError,
387 -- addr_matrix_f0_0 => addr_matrix_f0_0,
396 -- addr_matrix_f0_0 => addr_matrix_f0_0,
388 -- addr_matrix_f0_1 => addr_matrix_f0_1,
397 -- addr_matrix_f0_1 => addr_matrix_f0_1,
389 -- addr_matrix_f1 => addr_matrix_f1,
398 -- addr_matrix_f1 => addr_matrix_f1,
390 -- addr_matrix_f2 => addr_matrix_f2);
399 -- addr_matrix_f2 => addr_matrix_f2);
391 -------------------------------------------------------------------------------
400 -------------------------------------------------------------------------------
392
401
393 END Behavioral;
402 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,258 +1,263
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16
16
17 COMPONENT lpp_lfr_ms
17 COMPONENT lpp_lfr_ms
18 GENERIC (
18 GENERIC (
19 Mem_use : INTEGER
19 Mem_use : INTEGER
20 );
20 );
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
25 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
26 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
27
24 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
25 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
26 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
28 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30
34
31 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
35 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
32 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
36 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
33 dma_valid : OUT STD_LOGIC;
37 dma_valid : OUT STD_LOGIC;
34 dma_valid_burst : OUT STD_LOGIC;
38 dma_valid_burst : OUT STD_LOGIC;
35 dma_ren : IN STD_LOGIC;
39 dma_ren : IN STD_LOGIC;
36 dma_done : IN STD_LOGIC;
40 dma_done : IN STD_LOGIC;
37
41
38 ready_matrix_f0_0 : OUT STD_LOGIC;
42 ready_matrix_f0_0 : OUT STD_LOGIC;
39 ready_matrix_f0_1 : OUT STD_LOGIC;
43 ready_matrix_f0_1 : OUT STD_LOGIC;
40 ready_matrix_f1 : OUT STD_LOGIC;
44 ready_matrix_f1 : OUT STD_LOGIC;
41 ready_matrix_f2 : OUT STD_LOGIC;
45 ready_matrix_f2 : OUT STD_LOGIC;
42 error_anticipating_empty_fifo : OUT STD_LOGIC;
46 error_anticipating_empty_fifo : OUT STD_LOGIC;
43 error_bad_component_error : OUT STD_LOGIC;
47 error_bad_component_error : OUT STD_LOGIC;
44 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
48 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 status_ready_matrix_f0_0 : IN STD_LOGIC;
49 status_ready_matrix_f0_0 : IN STD_LOGIC;
46 status_ready_matrix_f0_1 : IN STD_LOGIC;
50 status_ready_matrix_f0_1 : IN STD_LOGIC;
47 status_ready_matrix_f1 : IN STD_LOGIC;
51 status_ready_matrix_f1 : IN STD_LOGIC;
48 status_ready_matrix_f2 : IN STD_LOGIC;
52 status_ready_matrix_f2 : IN STD_LOGIC;
49 status_error_anticipating_empty_fifo : IN STD_LOGIC;
53 status_error_anticipating_empty_fifo : IN STD_LOGIC;
50 status_error_bad_component_error : IN STD_LOGIC;
54 status_error_bad_component_error : IN STD_LOGIC;
51 config_active_interruption_onNewMatrix : IN STD_LOGIC;
55 config_active_interruption_onNewMatrix : IN STD_LOGIC;
52 config_active_interruption_onError : IN STD_LOGIC;
56 config_active_interruption_onError : IN STD_LOGIC;
53 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
55 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
56 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
60 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
57 END COMPONENT;
61 END COMPONENT;
58
62
59 COMPONENT lpp_lfr_ms_fsmdma
63 COMPONENT lpp_lfr_ms_fsmdma
60 PORT (
64 PORT (
61 HCLK : IN STD_ULOGIC;
65 HCLK : IN STD_ULOGIC;
62 HRESETn : IN STD_ULOGIC;
66 HRESETn : IN STD_ULOGIC;
67 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
63 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 fifo_empty : IN STD_LOGIC;
69 fifo_empty : IN STD_LOGIC;
65 fifo_ren : OUT STD_LOGIC;
70 fifo_ren : OUT STD_LOGIC;
66 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
67 header_val : IN STD_LOGIC;
72 header_val : IN STD_LOGIC;
68 header_ack : OUT STD_LOGIC;
73 header_ack : OUT STD_LOGIC;
69 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
70 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
75 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
71 dma_valid : OUT STD_LOGIC;
76 dma_valid : OUT STD_LOGIC;
72 dma_valid_burst : OUT STD_LOGIC;
77 dma_valid_burst : OUT STD_LOGIC;
73 dma_ren : IN STD_LOGIC;
78 dma_ren : IN STD_LOGIC;
74 dma_done : IN STD_LOGIC;
79 dma_done : IN STD_LOGIC;
75 ready_matrix_f0_0 : OUT STD_LOGIC;
80 ready_matrix_f0_0 : OUT STD_LOGIC;
76 ready_matrix_f0_1 : OUT STD_LOGIC;
81 ready_matrix_f0_1 : OUT STD_LOGIC;
77 ready_matrix_f1 : OUT STD_LOGIC;
82 ready_matrix_f1 : OUT STD_LOGIC;
78 ready_matrix_f2 : OUT STD_LOGIC;
83 ready_matrix_f2 : OUT STD_LOGIC;
79 error_anticipating_empty_fifo : OUT STD_LOGIC;
84 error_anticipating_empty_fifo : OUT STD_LOGIC;
80 error_bad_component_error : OUT STD_LOGIC;
85 error_bad_component_error : OUT STD_LOGIC;
81 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 status_ready_matrix_f0_0 : IN STD_LOGIC;
87 status_ready_matrix_f0_0 : IN STD_LOGIC;
83 status_ready_matrix_f0_1 : IN STD_LOGIC;
88 status_ready_matrix_f0_1 : IN STD_LOGIC;
84 status_ready_matrix_f1 : IN STD_LOGIC;
89 status_ready_matrix_f1 : IN STD_LOGIC;
85 status_ready_matrix_f2 : IN STD_LOGIC;
90 status_ready_matrix_f2 : IN STD_LOGIC;
86 status_error_anticipating_empty_fifo : IN STD_LOGIC;
91 status_error_anticipating_empty_fifo : IN STD_LOGIC;
87 status_error_bad_component_error : IN STD_LOGIC;
92 status_error_bad_component_error : IN STD_LOGIC;
88 config_active_interruption_onNewMatrix : IN STD_LOGIC;
93 config_active_interruption_onNewMatrix : IN STD_LOGIC;
89 config_active_interruption_onError : IN STD_LOGIC;
94 config_active_interruption_onError : IN STD_LOGIC;
90 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
95 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
98 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
94 END COMPONENT;
99 END COMPONENT;
95
100
96
101
97 COMPONENT lpp_lfr_filter
102 COMPONENT lpp_lfr_filter
98 GENERIC (
103 GENERIC (
99 Mem_use : INTEGER);
104 Mem_use : INTEGER);
100 PORT (
105 PORT (
101 sample : IN Samples(7 DOWNTO 0);
106 sample : IN Samples(7 DOWNTO 0);
102 sample_val : IN STD_LOGIC;
107 sample_val : IN STD_LOGIC;
103 clk : IN STD_LOGIC;
108 clk : IN STD_LOGIC;
104 rstn : IN STD_LOGIC;
109 rstn : IN STD_LOGIC;
105 data_shaping_SP0 : IN STD_LOGIC;
110 data_shaping_SP0 : IN STD_LOGIC;
106 data_shaping_SP1 : IN STD_LOGIC;
111 data_shaping_SP1 : IN STD_LOGIC;
107 data_shaping_R0 : IN STD_LOGIC;
112 data_shaping_R0 : IN STD_LOGIC;
108 data_shaping_R1 : IN STD_LOGIC;
113 data_shaping_R1 : IN STD_LOGIC;
109 sample_f0_val : OUT STD_LOGIC;
114 sample_f0_val : OUT STD_LOGIC;
110 sample_f1_val : OUT STD_LOGIC;
115 sample_f1_val : OUT STD_LOGIC;
111 sample_f2_val : OUT STD_LOGIC;
116 sample_f2_val : OUT STD_LOGIC;
112 sample_f3_val : OUT STD_LOGIC;
117 sample_f3_val : OUT STD_LOGIC;
113 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
114 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
115 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
121 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
117 END COMPONENT;
122 END COMPONENT;
118
123
119 COMPONENT lpp_lfr
124 COMPONENT lpp_lfr
120 GENERIC (
125 GENERIC (
121 Mem_use : INTEGER;
126 Mem_use : INTEGER;
122 nb_data_by_buffer_size : INTEGER;
127 nb_data_by_buffer_size : INTEGER;
123 nb_word_by_buffer_size : INTEGER;
128 nb_word_by_buffer_size : INTEGER;
124 nb_snapshot_param_size : INTEGER;
129 nb_snapshot_param_size : INTEGER;
125 delta_vector_size : INTEGER;
130 delta_vector_size : INTEGER;
126 delta_vector_size_f0_2 : INTEGER;
131 delta_vector_size_f0_2 : INTEGER;
127 pindex : INTEGER;
132 pindex : INTEGER;
128 paddr : INTEGER;
133 paddr : INTEGER;
129 pmask : INTEGER;
134 pmask : INTEGER;
130 pirq_ms : INTEGER;
135 pirq_ms : INTEGER;
131 pirq_wfp : INTEGER;
136 pirq_wfp : INTEGER;
132 hindex : INTEGER;
137 hindex : INTEGER;
133 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
138 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
134 );
139 );
135 PORT (
140 PORT (
136 clk : IN STD_LOGIC;
141 clk : IN STD_LOGIC;
137 rstn : IN STD_LOGIC;
142 rstn : IN STD_LOGIC;
138 sample_B : IN Samples14v(2 DOWNTO 0);
143 sample_B : IN Samples14v(2 DOWNTO 0);
139 sample_E : IN Samples14v(4 DOWNTO 0);
144 sample_E : IN Samples14v(4 DOWNTO 0);
140 sample_val : IN STD_LOGIC;
145 sample_val : IN STD_LOGIC;
141 apbi : IN apb_slv_in_type;
146 apbi : IN apb_slv_in_type;
142 apbo : OUT apb_slv_out_type;
147 apbo : OUT apb_slv_out_type;
143 ahbi : IN AHB_Mst_In_Type;
148 ahbi : IN AHB_Mst_In_Type;
144 ahbo : OUT AHB_Mst_Out_Type;
149 ahbo : OUT AHB_Mst_Out_Type;
145 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
150 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
151 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
147 data_shaping_BW : OUT STD_LOGIC
152 data_shaping_BW : OUT STD_LOGIC;
148 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
153 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
149 );
154 );
150 END COMPONENT;
155 END COMPONENT;
151
156
152 COMPONENT lpp_lfr_apbreg
157 COMPONENT lpp_lfr_apbreg
153 GENERIC (
158 GENERIC (
154 nb_data_by_buffer_size : INTEGER;
159 nb_data_by_buffer_size : INTEGER;
155 nb_word_by_buffer_size : INTEGER;
160 nb_word_by_buffer_size : INTEGER;
156 nb_snapshot_param_size : INTEGER;
161 nb_snapshot_param_size : INTEGER;
157 delta_vector_size : INTEGER;
162 delta_vector_size : INTEGER;
158 delta_vector_size_f0_2 : INTEGER;
163 delta_vector_size_f0_2 : INTEGER;
159 pindex : INTEGER;
164 pindex : INTEGER;
160 paddr : INTEGER;
165 paddr : INTEGER;
161 pmask : INTEGER;
166 pmask : INTEGER;
162 pirq_ms : INTEGER;
167 pirq_ms : INTEGER;
163 pirq_wfp : INTEGER;
168 pirq_wfp : INTEGER;
164 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
169 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
165 PORT (
170 PORT (
166 HCLK : IN STD_ULOGIC;
171 HCLK : IN STD_ULOGIC;
167 HRESETn : IN STD_ULOGIC;
172 HRESETn : IN STD_ULOGIC;
168 apbi : IN apb_slv_in_type;
173 apbi : IN apb_slv_in_type;
169 apbo : OUT apb_slv_out_type;
174 apbo : OUT apb_slv_out_type;
170 ready_matrix_f0_0 : IN STD_LOGIC;
175 ready_matrix_f0_0 : IN STD_LOGIC;
171 ready_matrix_f0_1 : IN STD_LOGIC;
176 ready_matrix_f0_1 : IN STD_LOGIC;
172 ready_matrix_f1 : IN STD_LOGIC;
177 ready_matrix_f1 : IN STD_LOGIC;
173 ready_matrix_f2 : IN STD_LOGIC;
178 ready_matrix_f2 : IN STD_LOGIC;
174 error_anticipating_empty_fifo : IN STD_LOGIC;
179 error_anticipating_empty_fifo : IN STD_LOGIC;
175 error_bad_component_error : IN STD_LOGIC;
180 error_bad_component_error : IN STD_LOGIC;
176 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
181 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
177 status_ready_matrix_f0_0 : OUT STD_LOGIC;
182 status_ready_matrix_f0_0 : OUT STD_LOGIC;
178 status_ready_matrix_f0_1 : OUT STD_LOGIC;
183 status_ready_matrix_f0_1 : OUT STD_LOGIC;
179 status_ready_matrix_f1 : OUT STD_LOGIC;
184 status_ready_matrix_f1 : OUT STD_LOGIC;
180 status_ready_matrix_f2 : OUT STD_LOGIC;
185 status_ready_matrix_f2 : OUT STD_LOGIC;
181 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
186 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
182 status_error_bad_component_error : OUT STD_LOGIC;
187 status_error_bad_component_error : OUT STD_LOGIC;
183 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
188 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
184 config_active_interruption_onError : OUT STD_LOGIC;
189 config_active_interruption_onError : OUT STD_LOGIC;
185 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
190 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
191 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
192 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
188 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
193 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
194 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
190 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
195 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
191 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
196 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
192 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
197 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
193 data_shaping_BW : OUT STD_LOGIC;
198 data_shaping_BW : OUT STD_LOGIC;
194 data_shaping_SP0 : OUT STD_LOGIC;
199 data_shaping_SP0 : OUT STD_LOGIC;
195 data_shaping_SP1 : OUT STD_LOGIC;
200 data_shaping_SP1 : OUT STD_LOGIC;
196 data_shaping_R0 : OUT STD_LOGIC;
201 data_shaping_R0 : OUT STD_LOGIC;
197 data_shaping_R1 : OUT STD_LOGIC;
202 data_shaping_R1 : OUT STD_LOGIC;
198 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
203 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
199 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
204 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
200 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
205 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
201 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
206 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
202 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
207 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
203 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
208 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
204 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
209 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
205 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
210 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
206 enable_f0 : OUT STD_LOGIC;
211 enable_f0 : OUT STD_LOGIC;
207 enable_f1 : OUT STD_LOGIC;
212 enable_f1 : OUT STD_LOGIC;
208 enable_f2 : OUT STD_LOGIC;
213 enable_f2 : OUT STD_LOGIC;
209 enable_f3 : OUT STD_LOGIC;
214 enable_f3 : OUT STD_LOGIC;
210 burst_f0 : OUT STD_LOGIC;
215 burst_f0 : OUT STD_LOGIC;
211 burst_f1 : OUT STD_LOGIC;
216 burst_f1 : OUT STD_LOGIC;
212 burst_f2 : OUT STD_LOGIC;
217 burst_f2 : OUT STD_LOGIC;
213 run : OUT STD_LOGIC;
218 run : OUT STD_LOGIC;
214 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
219 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
215 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
220 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
216 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
221 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
217 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
222 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
218 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
223 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
219 ---------------------------------------------------------------------------
224 ---------------------------------------------------------------------------
220 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
225 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
221 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
226 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
222 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
227 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
223 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
228 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
224 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
229 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
225 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
230 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
226 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
231 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
227 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
232 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
228 END COMPONENT;
233 END COMPONENT;
229
234
230 COMPONENT lpp_top_ms
235 COMPONENT lpp_top_ms
231 GENERIC (
236 GENERIC (
232 Mem_use : INTEGER;
237 Mem_use : INTEGER;
233 nb_burst_available_size : INTEGER;
238 nb_burst_available_size : INTEGER;
234 nb_snapshot_param_size : INTEGER;
239 nb_snapshot_param_size : INTEGER;
235 delta_snapshot_size : INTEGER;
240 delta_snapshot_size : INTEGER;
236 delta_f2_f0_size : INTEGER;
241 delta_f2_f0_size : INTEGER;
237 delta_f2_f1_size : INTEGER;
242 delta_f2_f1_size : INTEGER;
238 pindex : INTEGER;
243 pindex : INTEGER;
239 paddr : INTEGER;
244 paddr : INTEGER;
240 pmask : INTEGER;
245 pmask : INTEGER;
241 pirq_ms : INTEGER;
246 pirq_ms : INTEGER;
242 pirq_wfp : INTEGER;
247 pirq_wfp : INTEGER;
243 hindex_wfp : INTEGER;
248 hindex_wfp : INTEGER;
244 hindex_ms : INTEGER);
249 hindex_ms : INTEGER);
245 PORT (
250 PORT (
246 clk : IN STD_LOGIC;
251 clk : IN STD_LOGIC;
247 rstn : IN STD_LOGIC;
252 rstn : IN STD_LOGIC;
248 sample_B : IN Samples14v(2 DOWNTO 0);
253 sample_B : IN Samples14v(2 DOWNTO 0);
249 sample_E : IN Samples14v(4 DOWNTO 0);
254 sample_E : IN Samples14v(4 DOWNTO 0);
250 sample_val : IN STD_LOGIC;
255 sample_val : IN STD_LOGIC;
251 apbi : IN apb_slv_in_type;
256 apbi : IN apb_slv_in_type;
252 apbo : OUT apb_slv_out_type;
257 apbo : OUT apb_slv_out_type;
253 ahbi_ms : IN AHB_Mst_In_Type;
258 ahbi_ms : IN AHB_Mst_In_Type;
254 ahbo_ms : OUT AHB_Mst_Out_Type;
259 ahbo_ms : OUT AHB_Mst_Out_Type;
255 data_shaping_BW : OUT STD_LOGIC);
260 data_shaping_BW : OUT STD_LOGIC);
256 END COMPONENT;
261 END COMPONENT;
257
262
258 END lpp_lfr_pkg;
263 END lpp_lfr_pkg;
General Comments 0
You need to be logged in to leave comments. Login now