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TOP_LFR with MS and WFP
pellion -
r305:daa615f43a86 (MINI-LFR) WFP_MS-0-1-1 JC
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY MINI_LFR_top IS
49
50 PORT (
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
111
112 END MINI_LFR_top;
113
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
132 SIGNAL I00_s : STD_LOGIC;
133
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
163
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
173 -----------------------------------------------------------------------------
174
175 BEGIN -- beh
176
177 -----------------------------------------------------------------------------
178 -- CLK
179 -----------------------------------------------------------------------------
180
181 PROCESS(clk_50)
182 BEGIN
183 IF clk_50'EVENT AND clk_50 = '1' THEN
184 clk_50_s <= NOT clk_50_s;
185 END IF;
186 END PROCESS;
187
188 PROCESS(clk_50_s)
189 BEGIN
190 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
191 clk_25 <= NOT clk_25;
192 END IF;
193 END PROCESS;
194
195 PROCESS(clk_49)
196 BEGIN
197 IF clk_49'EVENT AND clk_49 = '1' THEN
198 clk_24 <= NOT clk_24;
199 END IF;
200 END PROCESS;
201
202 -----------------------------------------------------------------------------
203
204 PROCESS (clk_25, reset)
205 BEGIN -- PROCESS
206 IF reset = '0' THEN -- asynchronous reset (active low)
207 LED0 <= '0';
208 LED1 <= '0';
209 LED2 <= '0';
210 --IO1 <= '0';
211 --IO2 <= '1';
212 --IO3 <= '0';
213 --IO4 <= '0';
214 --IO5 <= '0';
215 --IO6 <= '0';
216 --IO7 <= '0';
217 --IO8 <= '0';
218 --IO9 <= '0';
219 --IO10 <= '0';
220 --IO11 <= '0';
221 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 LED0 <= '0';
223 LED1 <= '1';
224 LED2 <= BP0;
225 --IO1 <= '1';
226 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO3 <= ADC_SDO(0);
228 --IO4 <= ADC_SDO(1);
229 --IO5 <= ADC_SDO(2);
230 --IO6 <= ADC_SDO(3);
231 --IO7 <= ADC_SDO(4);
232 --IO8 <= ADC_SDO(5);
233 --IO9 <= ADC_SDO(6);
234 --IO10 <= ADC_SDO(7);
235 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 END IF;
237 END PROCESS;
238
239 PROCESS (clk_24, reset)
240 BEGIN -- PROCESS
241 IF reset = '0' THEN -- asynchronous reset (active low)
242 I00_s <= '0';
243 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 I00_s <= NOT I00_s;
245 END IF;
246 END PROCESS;
247 -- IO0 <= I00_s;
248
249 --UARTs
250 nCTS1 <= '1';
251 nCTS2 <= '1';
252 nDCD2 <= '1';
253
254 --EXT CONNECTOR
255
256 --SPACE WIRE
257
258 leon3_soc_1 : leon3_soc
259 GENERIC MAP (
260 fabtech => apa3e,
261 memtech => apa3e,
262 padtech => inferred,
263 clktech => inferred,
264 disas => 0,
265 dbguart => 0,
266 pclow => 2,
267 clk_freq => 25000,
268 NB_CPU => 1,
269 ENABLE_FPU => 1,
270 FPU_NETLIST => 0,
271 ENABLE_DSU => 1,
272 ENABLE_AHB_UART => 1,
273 ENABLE_APB_UART => 1,
274 ENABLE_IRQMP => 1,
275 ENABLE_GPT => 1,
276 NB_AHB_MASTER => NB_AHB_MASTER,
277 NB_AHB_SLAVE => NB_AHB_SLAVE,
278 NB_APB_SLAVE => NB_APB_SLAVE)
279 PORT MAP (
280 clk => clk_25,
281 reset => reset,
282 errorn => errorn,
283 ahbrxd => TXD1,
284 ahbtxd => RXD1,
285 urxd1 => TXD2,
286 utxd1 => RXD2,
287 address => SRAM_A,
288 data => SRAM_DQ,
289 nSRAM_BE0 => SRAM_nBE(0),
290 nSRAM_BE1 => SRAM_nBE(1),
291 nSRAM_BE2 => SRAM_nBE(2),
292 nSRAM_BE3 => SRAM_nBE(3),
293 nSRAM_WE => SRAM_nWE,
294 nSRAM_CE => SRAM_CE,
295 nSRAM_OE => SRAM_nOE,
296
297 apbi_ext => apbi_ext,
298 apbo_ext => apbo_ext,
299 ahbi_s_ext => ahbi_s_ext,
300 ahbo_s_ext => ahbo_s_ext,
301 ahbi_m_ext => ahbi_m_ext,
302 ahbo_m_ext => ahbo_m_ext);
303
304 -------------------------------------------------------------------------------
305 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 -------------------------------------------------------------------------------
307 apb_lfr_time_management_1 : apb_lfr_time_management
308 GENERIC MAP (
309 pindex => 6,
310 paddr => 6,
311 pmask => 16#fff#,
312 pirq => 12,
313 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
314 PORT MAP (
315 clk25MHz => clk_25,
316 clk49_152MHz => clk_24, -- 49.152MHz/2
317 resetn => reset,
318 grspw_tick => swno.tickout,
319 apbi => apbi_ext,
320 apbo => apbo_ext(6),
321 coarse_time => coarse_time,
322 fine_time => fine_time);
323
324 -----------------------------------------------------------------------
325 --- SpaceWire --------------------------------------------------------
326 -----------------------------------------------------------------------
327
328 SPW_EN <= '1';
329
330 spw_clk <= clk_50_s;
331 spw_rxtxclk <= spw_clk;
332 spw_rxclkn <= NOT spw_rxtxclk;
333
334 -- PADS for SPW1
335 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
336 PORT MAP (SPW_NOM_DIN, dtmp(0));
337 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
338 PORT MAP (SPW_NOM_SIN, stmp(0));
339 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_DOUT, swno.d(0));
341 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_SOUT, swno.s(0));
343 -- PADS FOR SPW2
344 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 PORT MAP (SPW_RED_SIN, dtmp(1));
346 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 PORT MAP (SPW_RED_DIN, stmp(1));
348 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
349 PORT MAP (SPW_RED_DOUT, swno.d(1));
350 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
351 PORT MAP (SPW_RED_SOUT, swno.s(1));
352
353 -- GRSPW PHY
354 --spw1_input: if CFG_SPW_GRSPW = 1 generate
355 spw_inputloop : FOR j IN 0 TO 1 GENERATE
356 spw_phy0 : grspw_phy
357 GENERIC MAP(
358 tech => apa3e,
359 rxclkbuftype => 1,
360 scantest => 0)
361 PORT MAP(
362 rxrst => swno.rxrst,
363 di => dtmp(j),
364 si => stmp(j),
365 rxclko => spw_rxclk(j),
366 do => swni.d(j),
367 ndo => swni.nd(j*5+4 DOWNTO j*5),
368 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
369 END GENERATE spw_inputloop;
370
371 -- SPW core
372 sw0 : grspwm GENERIC MAP(
373 tech => apa3e,
374 hindex => 1,
375 pindex => 5,
376 paddr => 5,
377 pirq => 11,
378 sysfreq => 25000, -- CPU_FREQ
379 rmap => 1,
380 rmapcrc => 1,
381 fifosize1 => 16,
382 fifosize2 => 16,
383 rxclkbuftype => 1,
384 rxunaligned => 0,
385 rmapbufs => 4,
386 ft => 0,
387 netlist => 0,
388 ports => 2,
389 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
390 memtech => apa3e,
391 destkey => 2,
392 spwcore => 1
393 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
394 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
395 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
396 )
397 PORT MAP(reset, clk_25, spw_rxclk(0),
398 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
399 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
400 swni, swno);
401
402 swni.tickin <= '0';
403 swni.rmapen <= '1';
404 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
405 swni.tickinraw <= '0';
406 swni.timein <= (OTHERS => '0');
407 swni.dcrstval <= (OTHERS => '0');
408 swni.timerrstval <= (OTHERS => '0');
409
410 -------------------------------------------------------------------------------
411 -- LFR ------------------------------------------------------------------------
412 -------------------------------------------------------------------------------
413 lpp_lfr_1 : lpp_lfr
414 GENERIC MAP (
415 Mem_use => use_RAM,
416 nb_data_by_buffer_size => 32,
417 nb_word_by_buffer_size => 30,
418 nb_snapshot_param_size => 32,
419 delta_vector_size => 32,
420 delta_vector_size_f0_2 => 7, -- log2(96)
421 pindex => 15,
422 paddr => 15,
423 pmask => 16#fff#,
424 pirq_ms => 6,
425 pirq_wfp => 14,
426 hindex => 2,
427 top_lfr_version => X"000101") -- aa.bb.cc version
428 PORT MAP (
429 clk => clk_25,
430 rstn => reset,
431 sample_B => sample(2 DOWNTO 0),
432 sample_E => sample(7 DOWNTO 3),
433 sample_val => sample_val,
434 apbi => apbi_ext,
435 apbo => apbo_ext(15),
436 ahbi => ahbi_m_ext,
437 ahbo => ahbo_m_ext(2),
438 coarse_time => coarse_time,
439 fine_time => fine_time,
440 data_shaping_BW => bias_fail_sw_sig);
441
442 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
443 GENERIC MAP(
444 ChannelCount => 8,
445 SampleNbBits => 14,
446 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
447 ncycle_cnv => 250) -- 49 152 000 / 98304 /2
448 PORT MAP (
449 -- CONV
450 cnv_clk => clk_24,
451 cnv_rstn => reset,
452 cnv => ADC_nCS_sig,
453 -- DATA
454 clk => clk_25,
455 rstn => reset,
456 sck => ADC_CLK_sig,
457 sdo => ADC_SDO_sig,
458 -- SAMPLE
459 sample => sample,
460 sample_val => sample_val);
461
462 IO10 <= ADC_SDO_sig(5);
463 IO9 <= ADC_SDO_sig(4);
464 IO8 <= ADC_SDO_sig(3);
465
466 ADC_nCS <= ADC_nCS_sig;
467 ADC_CLK <= ADC_CLK_sig;
468 ADC_SDO_sig <= ADC_SDO;
469
470 ----------------------------------------------------------------------
471 --- GPIO -----------------------------------------------------------
472 ----------------------------------------------------------------------
473
474 grgpio0 : grgpio
475 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
476 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
477
478 pio_pad_0 : iopad
479 GENERIC MAP (tech => CFG_PADTECH)
480 PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
481 pio_pad_1 : iopad
482 GENERIC MAP (tech => CFG_PADTECH)
483 PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
484 pio_pad_2 : iopad
485 GENERIC MAP (tech => CFG_PADTECH)
486 PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
487 pio_pad_3 : iopad
488 GENERIC MAP (tech => CFG_PADTECH)
489 PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
490 pio_pad_4 : iopad
491 GENERIC MAP (tech => CFG_PADTECH)
492 PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
493 pio_pad_5 : iopad
494 GENERIC MAP (tech => CFG_PADTECH)
495 PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
496 pio_pad_6 : iopad
497 GENERIC MAP (tech => CFG_PADTECH)
498 PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
499 pio_pad_7 : iopad
500 GENERIC MAP (tech => CFG_PADTECH)
501 PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
502
503 END beh;
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@@ -0,0 +1,46
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd
14
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 CLEAN=soft-clean
18
19 TECHLIBS = proasic3e
20
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
23
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 ./amba_lcd_16x2_ctrlr \
27 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_delay \
30 ./lpp_bootloader \
31 ./lpp_cna \
32 ./lpp_uart \
33 ./lpp_usb \
34 ./lpp_sim/CY7C1061DV33 \
35
36 FILESKIP =i2cmst.vhd \
37 APB_MULTI_DIODE.vhd \
38 APB_SIMPLE_DIODE.vhd \
39 Top_MatrixSpec.vhd \
40 APB_FFT.vhd
41
42 include $(GRLIB)/bin/Makefile
43 include $(GRLIB)/software/leon3/Makefile
44
45 ################## project specific targets ##########################
46
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@@ -8,6 +8,8 vcom -quiet -93 -work lpp ../../../grl
8
8
9 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
9 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
10
10
11 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd
12 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd
11 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd
13 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd
12 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
14 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
13
15
@@ -21,6 +23,6 vsim work.testbench
21
23
22 log -r *
24 log -r *
23
25
24 do wave_waveform_longsim.do
26 do wave_ms.do
25
27
26 run 40 ms
28 run 2 ms
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@@ -314,24 +314,24 BEGIN
314 ahb0 : ahbctrl -- AHB arbiter/multiplexer
314 ahb0 : ahbctrl -- AHB arbiter/multiplexer
315 GENERIC MAP (defmast => 0, split => 0,
315 GENERIC MAP (defmast => 0, split => 0,
316 rrobin => 1, ioaddr => 16#FFF#,
316 rrobin => 1, ioaddr => 16#FFF#,
317 ioen => 0, nahbm => 2, nahbs => 1)
317 ioen => 0, nahbm => 2, nahbs => 4)
318 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
318 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
319
319
320
320
321
321
322 --- AHB RAM ----------------------------------------------------------
322 --- AHB RAM ----------------------------------------------------------
323 --ahbram0 : ahbram
323 ahbram0 : ahbram
324 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
324 GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
325 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
325 PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
326 --ahbram1 : ahbram
326 ahbram1 : ahbram
327 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
327 GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
328 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
328 PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
329 --ahbram2 : ahbram
329 ahbram2 : ahbram
330 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
330 GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
331 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
331 PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
332 --ahbram3 : ahbram
332 ahbram3 : ahbram
333 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
333 GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
334 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
334 PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
335
335
336 -----------------------------------------------------------------------------
336 -----------------------------------------------------------------------------
337 ----------------------------------------------------------------------
337 ----------------------------------------------------------------------
@@ -501,7 +501,7 BEGIN
501 -----------------------------------------------------------------------------
501 -----------------------------------------------------------------------------
502 -- IRQ
502 -- IRQ
503 -----------------------------------------------------------------------------
503 -----------------------------------------------------------------------------
504 PROCESS
504 PROCESS (clk25MHz, rstn)
505 BEGIN -- PROCESS
505 BEGIN -- PROCESS
506 IF rstn = '0' THEN -- asynchronous reset (active low)
506 IF rstn = '0' THEN -- asynchronous reset (active low)
507
507
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@@ -17,6 +17,7 SYNC_FF.vhd
17 Shifter.vhd
17 Shifter.vhd
18 TwoComplementer.vhd
18 TwoComplementer.vhd
19 Clock_Divider.vhd
19 Clock_Divider.vhd
20 lpp_front_to_level.vhd
20 lpp_front_detection.vhd
21 lpp_front_detection.vhd
21 lpp_front_positive_detection.vhd
22 lpp_front_positive_detection.vhd
22 SYNC_VALID_BIT.vhd
23 SYNC_VALID_BIT.vhd
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@@ -40,7 +40,7 PACKAGE apb_devices_list IS
40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
41
41
42 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
42 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
43 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A1#;
43 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
44
44
45 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
45 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
46
46
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@@ -59,7 +59,7 ENTITY lpp_lfr IS
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC--;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65
65
@@ -489,7 +489,7 BEGIN
489 data_f3_data_out => data_f3_data_out,
489 data_f3_data_out => data_f3_data_out,
490 data_f3_data_out_valid => data_f3_data_out_valid_s,
490 data_f3_data_out_valid => data_f3_data_out_valid_s,
491 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
491 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
492 data_f3_data_out_ren => data_f3_data_out_ren --,
492 data_f3_data_out_ren => data_f3_data_out_ren ,
493
493
494 -------------------------------------------------------------------------
494 -------------------------------------------------------------------------
495 observation_reg => observation_reg
495 observation_reg => observation_reg
@@ -605,8 +605,10 BEGIN
605 dma_sel <= (OTHERS => '0');
605 dma_sel <= (OTHERS => '0');
606 dma_send <= '0';
606 dma_send <= '0';
607 dma_valid_burst <= '0';
607 dma_valid_burst <= '0';
608 data_ms_done <= '0';
608 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
609 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
609 IF run = '1' THEN
610 IF run = '1' THEN
611 data_ms_done <= '0';
610 IF dma_sel = "00000" OR dma_done = '1' THEN
612 IF dma_sel = "00000" OR dma_done = '1' THEN
611 dma_sel <= dma_rr_grant;
613 dma_sel <= dma_rr_grant;
612 IF dma_rr_grant(0) = '1' THEN
614 IF dma_rr_grant(0) = '1' THEN
@@ -639,6 +641,7 BEGIN
639 dma_send <= '0';
641 dma_send <= '0';
640 END IF;
642 END IF;
641 ELSE
643 ELSE
644 data_ms_done <= '0';
642 dma_sel <= (OTHERS => '0');
645 dma_sel <= (OTHERS => '0');
643 dma_send <= '0';
646 dma_send <= '0';
644 dma_valid_burst <= '0';
647 dma_valid_burst <= '0';
@@ -717,6 +720,7 BEGIN
717 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
720 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
718 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
721 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
719 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
722 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
723
720 -------------------------------------------------------------------------------
724 -------------------------------------------------------------------------------
721 lpp_lfr_ms_1: lpp_lfr_ms
725 lpp_lfr_ms_1: lpp_lfr_ms
722 GENERIC MAP (
726 GENERIC MAP (
@@ -725,6 +729,9 BEGIN
725 clk => clk,
729 clk => clk,
726 rstn => rstn,
730 rstn => rstn,
727
731
732 coarse_time => coarse_time,
733 fine_time => fine_time,
734
728 sample_f0_wen => sample_f0_wen,
735 sample_f0_wen => sample_f0_wen,
729 sample_f0_wdata => sample_f0_wdata,
736 sample_f0_wdata => sample_f0_wdata,
730 sample_f1_wen => sample_f1_wen,
737 sample_f1_wen => sample_f1_wen,
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@@ -37,6 +37,9 ENTITY lpp_lfr_ms IS
37 ---------------------------------------------------------------------------
37 ---------------------------------------------------------------------------
38 -- DATA INPUT
38 -- DATA INPUT
39 ---------------------------------------------------------------------------
39 ---------------------------------------------------------------------------
40 -- TIME
41 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
42 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
40 --
43 --
41 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
45 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
@@ -136,6 +139,9 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
136 SIGNAL DMA_Read : STD_LOGIC;
139 SIGNAL DMA_Read : STD_LOGIC;
137 SIGNAL DMA_ack : STD_LOGIC;
140 SIGNAL DMA_ack : STD_LOGIC;
138
141
142 -----------------------------------------------------------------------------
143 SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
144
139 BEGIN
145 BEGIN
140
146
141 -----------------------------------------------------------------------------
147 -----------------------------------------------------------------------------
@@ -305,13 +311,16 BEGIN
305 header_val => Head_Val,
311 header_val => Head_Val,
306 header_ack => DMA_ack );
312 header_ack => DMA_ack );
307 -----------------------------------------------------------------------------
313 -----------------------------------------------------------------------------
308
314 data_time(31 DOWNTO 0) <= coarse_time;
315 data_time(47 DOWNTO 32) <= fine_time;
309
316
310 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
317 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
311 PORT MAP (
318 PORT MAP (
312 HCLK => clk,
319 HCLK => clk,
313 HRESETn => rstn,
320 HRESETn => rstn,
314
321
322 data_time => data_time,
323
315 fifo_data => Head_Data,
324 fifo_data => Head_Data,
316 fifo_empty => Head_Empty,
325 fifo_empty => Head_Empty,
317 fifo_ren => DMA_Read,
326 fifo_ren => DMA_Read,
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@@ -21,6 +21,10 PACKAGE lpp_lfr_pkg IS
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
25 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
26 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
27
24 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
25 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
26 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -60,6 +64,7 PACKAGE lpp_lfr_pkg IS
60 PORT (
64 PORT (
61 HCLK : IN STD_ULOGIC;
65 HCLK : IN STD_ULOGIC;
62 HRESETn : IN STD_ULOGIC;
66 HRESETn : IN STD_ULOGIC;
67 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
63 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 fifo_empty : IN STD_LOGIC;
69 fifo_empty : IN STD_LOGIC;
65 fifo_ren : OUT STD_LOGIC;
70 fifo_ren : OUT STD_LOGIC;
@@ -144,7 +149,7 PACKAGE lpp_lfr_pkg IS
144 ahbo : OUT AHB_Mst_Out_Type;
149 ahbo : OUT AHB_Mst_Out_Type;
145 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
150 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
151 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
147 data_shaping_BW : OUT STD_LOGIC
152 data_shaping_BW : OUT STD_LOGIC;
148 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
153 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
149 );
154 );
150 END COMPONENT;
155 END COMPONENT;
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