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Change on MS_F2 the data at 16Hz by the data at 256Hz
pellion -
r394:d544c8db0c81 (MINI-LFR) WFP_MS-0-1-23 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 BEGIN -- beh
180 180
181 181 -----------------------------------------------------------------------------
182 182 -- CLK
183 183 -----------------------------------------------------------------------------
184 184
185 185 PROCESS(clk_50)
186 186 BEGIN
187 187 IF clk_50'EVENT AND clk_50 = '1' THEN
188 188 clk_50_s <= NOT clk_50_s;
189 189 END IF;
190 190 END PROCESS;
191 191
192 192 PROCESS(clk_50_s)
193 193 BEGIN
194 194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 195 clk_25 <= NOT clk_25;
196 196 END IF;
197 197 END PROCESS;
198 198
199 199 PROCESS(clk_49)
200 200 BEGIN
201 201 IF clk_49'EVENT AND clk_49 = '1' THEN
202 202 clk_24 <= NOT clk_24;
203 203 END IF;
204 204 END PROCESS;
205 205
206 206 -----------------------------------------------------------------------------
207 207
208 208 PROCESS (clk_25, reset)
209 209 BEGIN -- PROCESS
210 210 IF reset = '0' THEN -- asynchronous reset (active low)
211 211 LED0 <= '0';
212 212 LED1 <= '0';
213 213 LED2 <= '0';
214 214 --IO1 <= '0';
215 215 --IO2 <= '1';
216 216 --IO3 <= '0';
217 217 --IO4 <= '0';
218 218 --IO5 <= '0';
219 219 --IO6 <= '0';
220 220 --IO7 <= '0';
221 221 --IO8 <= '0';
222 222 --IO9 <= '0';
223 223 --IO10 <= '0';
224 224 --IO11 <= '0';
225 225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 226 LED0 <= '0';
227 227 LED1 <= '1';
228 228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 229 --IO1 <= '1';
230 230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 231 --IO3 <= ADC_SDO(0);
232 232 --IO4 <= ADC_SDO(1);
233 233 --IO5 <= ADC_SDO(2);
234 234 --IO6 <= ADC_SDO(3);
235 235 --IO7 <= ADC_SDO(4);
236 236 --IO8 <= ADC_SDO(5);
237 237 --IO9 <= ADC_SDO(6);
238 238 --IO10 <= ADC_SDO(7);
239 239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 240 END IF;
241 241 END PROCESS;
242 242
243 243 PROCESS (clk_24, reset)
244 244 BEGIN -- PROCESS
245 245 IF reset = '0' THEN -- asynchronous reset (active low)
246 246 I00_s <= '0';
247 247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 248 I00_s <= NOT I00_s ;
249 249 END IF;
250 250 END PROCESS;
251 251 -- IO0 <= I00_s;
252 252
253 253 --UARTs
254 254 nCTS1 <= '1';
255 255 nCTS2 <= '1';
256 256 nDCD2 <= '1';
257 257
258 258 --EXT CONNECTOR
259 259
260 260 --SPACE WIRE
261 261
262 262 leon3_soc_1 : leon3_soc
263 263 GENERIC MAP (
264 264 fabtech => apa3e,
265 265 memtech => apa3e,
266 266 padtech => inferred,
267 267 clktech => inferred,
268 268 disas => 0,
269 269 dbguart => 0,
270 270 pclow => 2,
271 271 clk_freq => 25000,
272 272 NB_CPU => 1,
273 273 ENABLE_FPU => 1,
274 274 FPU_NETLIST => 0,
275 275 ENABLE_DSU => 1,
276 276 ENABLE_AHB_UART => 1,
277 277 ENABLE_APB_UART => 1,
278 278 ENABLE_IRQMP => 1,
279 279 ENABLE_GPT => 1,
280 280 NB_AHB_MASTER => NB_AHB_MASTER,
281 281 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 282 NB_APB_SLAVE => NB_APB_SLAVE)
283 283 PORT MAP (
284 284 clk => clk_25,
285 285 reset => reset,
286 286 errorn => errorn,
287 287 ahbrxd => TXD1,
288 288 ahbtxd => RXD1,
289 289 urxd1 => TXD2,
290 290 utxd1 => RXD2,
291 291 address => SRAM_A,
292 292 data => SRAM_DQ,
293 293 nSRAM_BE0 => SRAM_nBE(0),
294 294 nSRAM_BE1 => SRAM_nBE(1),
295 295 nSRAM_BE2 => SRAM_nBE(2),
296 296 nSRAM_BE3 => SRAM_nBE(3),
297 297 nSRAM_WE => SRAM_nWE,
298 298 nSRAM_CE => SRAM_CE,
299 299 nSRAM_OE => SRAM_nOE,
300 300
301 301 apbi_ext => apbi_ext,
302 302 apbo_ext => apbo_ext,
303 303 ahbi_s_ext => ahbi_s_ext,
304 304 ahbo_s_ext => ahbo_s_ext,
305 305 ahbi_m_ext => ahbi_m_ext,
306 306 ahbo_m_ext => ahbo_m_ext);
307 307
308 308 -------------------------------------------------------------------------------
309 309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 310 -------------------------------------------------------------------------------
311 311 apb_lfr_time_management_1 : apb_lfr_time_management
312 312 GENERIC MAP (
313 313 pindex => 6,
314 314 paddr => 6,
315 315 pmask => 16#fff#,
316 316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 318 PORT MAP (
319 319 clk25MHz => clk_25,
320 320 clk24_576MHz => clk_24, -- 49.152MHz/2
321 321 resetn => reset,
322 322 grspw_tick => swno.tickout,
323 323 apbi => apbi_ext,
324 324 apbo => apbo_ext(6),
325 325 coarse_time => coarse_time,
326 326 fine_time => fine_time);
327 327
328 328 -----------------------------------------------------------------------
329 329 --- SpaceWire --------------------------------------------------------
330 330 -----------------------------------------------------------------------
331 331
332 332 SPW_EN <= '1';
333 333
334 334 spw_clk <= clk_50_s;
335 335 spw_rxtxclk <= spw_clk;
336 336 spw_rxclkn <= NOT spw_rxtxclk;
337 337
338 338 -- PADS for SPW1
339 339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 340 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 342 PORT MAP (SPW_NOM_SIN, stmp(0));
343 343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 347 -- PADS FOR SPW2
348 348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 349 PORT MAP (SPW_RED_SIN, dtmp(1));
350 350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 351 PORT MAP (SPW_RED_DIN, stmp(1));
352 352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 353 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 355 PORT MAP (SPW_RED_SOUT, swno.s(1));
356 356
357 357 -- GRSPW PHY
358 358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 360 spw_phy0 : grspw_phy
361 361 GENERIC MAP(
362 362 tech => apa3e,
363 363 rxclkbuftype => 1,
364 364 scantest => 0)
365 365 PORT MAP(
366 366 rxrst => swno.rxrst,
367 367 di => dtmp(j),
368 368 si => stmp(j),
369 369 rxclko => spw_rxclk(j),
370 370 do => swni.d(j),
371 371 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 373 END GENERATE spw_inputloop;
374 374
375 375 -- SPW core
376 376 sw0 : grspwm GENERIC MAP(
377 377 tech => apa3e,
378 378 hindex => 1,
379 379 pindex => 5,
380 380 paddr => 5,
381 381 pirq => 11,
382 382 sysfreq => 25000, -- CPU_FREQ
383 383 rmap => 1,
384 384 rmapcrc => 1,
385 385 fifosize1 => 16,
386 386 fifosize2 => 16,
387 387 rxclkbuftype => 1,
388 388 rxunaligned => 0,
389 389 rmapbufs => 4,
390 390 ft => 0,
391 391 netlist => 0,
392 392 ports => 2,
393 393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 394 memtech => apa3e,
395 395 destkey => 2,
396 396 spwcore => 1
397 397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 400 )
401 401 PORT MAP(reset, clk_25, spw_rxclk(0),
402 402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 404 swni, swno);
405 405
406 406 swni.tickin <= '0';
407 407 swni.rmapen <= '1';
408 408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 409 swni.tickinraw <= '0';
410 410 swni.timein <= (OTHERS => '0');
411 411 swni.dcrstval <= (OTHERS => '0');
412 412 swni.timerrstval <= (OTHERS => '0');
413 413
414 414 -------------------------------------------------------------------------------
415 415 -- LFR ------------------------------------------------------------------------
416 416 -------------------------------------------------------------------------------
417 417 lpp_lfr_1 : lpp_lfr
418 418 GENERIC MAP (
419 419 Mem_use => use_RAM,
420 420 nb_data_by_buffer_size => 32,
421 421 nb_word_by_buffer_size => 30,
422 422 nb_snapshot_param_size => 32,
423 423 delta_vector_size => 32,
424 424 delta_vector_size_f0_2 => 7, -- log2(96)
425 425 pindex => 15,
426 426 paddr => 15,
427 427 pmask => 16#fff#,
428 428 pirq_ms => 6,
429 429 pirq_wfp => 14,
430 430 hindex => 2,
431 top_lfr_version => X"000116") -- aa.bb.cc version
431 top_lfr_version => X"000117") -- aa.bb.cc version
432 432 PORT MAP (
433 433 clk => clk_25,
434 434 rstn => reset,
435 435 sample_B => sample_s(2 DOWNTO 0),
436 436 sample_E => sample_s(7 DOWNTO 3),
437 437 sample_val => sample_val,
438 438 apbi => apbi_ext,
439 439 apbo => apbo_ext(15),
440 440 ahbi => ahbi_m_ext,
441 441 ahbo => ahbo_m_ext(2),
442 442 coarse_time => coarse_time,
443 443 fine_time => fine_time,
444 444 data_shaping_BW => bias_fail_sw_sig,
445 445 observation_vector_0=> observation_vector_0,
446 446 observation_vector_1 => observation_vector_1,
447 447 observation_reg => observation_reg);
448 448
449 449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
450 450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
451 451 END GENERATE all_sample;
452 452
453 453
454 454
455 455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
456 456 GENERIC MAP(
457 457 ChannelCount => 8,
458 458 SampleNbBits => 14,
459 459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
460 460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
461 461 PORT MAP (
462 462 -- CONV
463 463 cnv_clk => clk_24,
464 464 cnv_rstn => reset,
465 465 cnv => ADC_nCS_sig,
466 466 -- DATA
467 467 clk => clk_25,
468 468 rstn => reset,
469 469 sck => ADC_CLK_sig,
470 470 sdo => ADC_SDO_sig,
471 471 -- SAMPLE
472 472 sample => sample,
473 473 sample_val => sample_val);
474 474
475 475 --IO10 <= ADC_SDO_sig(5);
476 476 --IO9 <= ADC_SDO_sig(4);
477 477 --IO8 <= ADC_SDO_sig(3);
478 478
479 479 ADC_nCS <= ADC_nCS_sig;
480 480 ADC_CLK <= ADC_CLK_sig;
481 481 ADC_SDO_sig <= ADC_SDO;
482 482
483 483 ----------------------------------------------------------------------
484 484 --- GPIO -----------------------------------------------------------
485 485 ----------------------------------------------------------------------
486 486
487 487 grgpio0 : grgpio
488 488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
489 489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
490 490
491 491 --pio_pad_0 : iopad
492 492 -- GENERIC MAP (tech => CFG_PADTECH)
493 493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
494 494 --pio_pad_1 : iopad
495 495 -- GENERIC MAP (tech => CFG_PADTECH)
496 496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
497 497 --pio_pad_2 : iopad
498 498 -- GENERIC MAP (tech => CFG_PADTECH)
499 499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
500 500 --pio_pad_3 : iopad
501 501 -- GENERIC MAP (tech => CFG_PADTECH)
502 502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
503 503 --pio_pad_4 : iopad
504 504 -- GENERIC MAP (tech => CFG_PADTECH)
505 505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
506 506 --pio_pad_5 : iopad
507 507 -- GENERIC MAP (tech => CFG_PADTECH)
508 508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
509 509 --pio_pad_6 : iopad
510 510 -- GENERIC MAP (tech => CFG_PADTECH)
511 511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
512 512 --pio_pad_7 : iopad
513 513 -- GENERIC MAP (tech => CFG_PADTECH)
514 514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
515 515
516 516 PROCESS (clk_25, reset)
517 517 BEGIN -- PROCESS
518 518 IF reset = '0' THEN -- asynchronous reset (active low)
519 519 IO0 <= '0';
520 520 IO1 <= '0';
521 521 IO2 <= '0';
522 522 IO3 <= '0';
523 523 IO4 <= '0';
524 524 IO5 <= '0';
525 525 IO6 <= '0';
526 526 IO7 <= '0';
527 527 IO8 <= '0';
528 528 IO9 <= '0';
529 529 IO10 <= '0';
530 530 IO11 <= '0';
531 531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
532 532 CASE gpioo.dout(2 DOWNTO 0) IS
533 533 WHEN "011" =>
534 534 IO0 <= observation_reg(0 );
535 535 IO1 <= observation_reg(1 );
536 536 IO2 <= observation_reg(2 );
537 537 IO3 <= observation_reg(3 );
538 538 IO4 <= observation_reg(4 );
539 539 IO5 <= observation_reg(5 );
540 540 IO6 <= observation_reg(6 );
541 541 IO7 <= observation_reg(7 );
542 542 IO8 <= observation_reg(8 );
543 543 IO9 <= observation_reg(9 );
544 544 IO10 <= observation_reg(10);
545 545 IO11 <= observation_reg(11);
546 546 WHEN "001" =>
547 547 IO0 <= observation_reg(0 + 12);
548 548 IO1 <= observation_reg(1 + 12);
549 549 IO2 <= observation_reg(2 + 12);
550 550 IO3 <= observation_reg(3 + 12);
551 551 IO4 <= observation_reg(4 + 12);
552 552 IO5 <= observation_reg(5 + 12);
553 553 IO6 <= observation_reg(6 + 12);
554 554 IO7 <= observation_reg(7 + 12);
555 555 IO8 <= observation_reg(8 + 12);
556 556 IO9 <= observation_reg(9 + 12);
557 557 IO10 <= observation_reg(10 + 12);
558 558 IO11 <= observation_reg(11 + 12);
559 559 WHEN "010" =>
560 560 IO0 <= observation_reg(0 + 12 + 12);
561 561 IO1 <= observation_reg(1 + 12 + 12);
562 562 IO2 <= observation_reg(2 + 12 + 12);
563 563 IO3 <= observation_reg(3 + 12 + 12);
564 564 IO4 <= observation_reg(4 + 12 + 12);
565 565 IO5 <= observation_reg(5 + 12 + 12);
566 566 IO6 <= observation_reg(6 + 12 + 12);
567 567 IO7 <= observation_reg(7 + 12 + 12);
568 568 IO8 <= '0';
569 569 IO9 <= '0';
570 570 IO10 <= '0';
571 571 IO11 <= '0';
572 572 WHEN "000" =>
573 573 IO0 <= observation_vector_0(0 );
574 574 IO1 <= observation_vector_0(1 );
575 575 IO2 <= observation_vector_0(2 );
576 576 IO3 <= observation_vector_0(3 );
577 577 IO4 <= observation_vector_0(4 );
578 578 IO5 <= observation_vector_0(5 );
579 579 IO6 <= observation_vector_0(6 );
580 580 IO7 <= observation_vector_0(7 );
581 581 IO8 <= observation_vector_0(8 );
582 582 IO9 <= observation_vector_0(9 );
583 583 IO10 <= observation_vector_0(10);
584 584 IO11 <= observation_vector_0(11);
585 585 WHEN "100" =>
586 586 IO0 <= observation_vector_1(0 );
587 587 IO1 <= observation_vector_1(1 );
588 588 IO2 <= observation_vector_1(2 );
589 589 IO3 <= observation_vector_1(3 );
590 590 IO4 <= observation_vector_1(4 );
591 591 IO5 <= observation_vector_1(5 );
592 592 IO6 <= observation_vector_1(6 );
593 593 IO7 <= observation_vector_1(7 );
594 594 IO8 <= observation_vector_1(8 );
595 595 IO9 <= observation_vector_1(9 );
596 596 IO10 <= observation_vector_1(10);
597 597 IO11 <= observation_vector_1(11);
598 598 WHEN OTHERS => NULL;
599 599 END CASE;
600 600
601 601 END IF;
602 602 END PROCESS;
603 603
604 604 END beh;
Show file before | Show file after | Hide comments
@@ -1,748 +1,748
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 29 nb_word_by_buffer_size : INTEGER := 11;
30 30 nb_snapshot_param_size : INTEGER := 11;
31 31 delta_vector_size : INTEGER := 20;
32 32 delta_vector_size_f0_2 : INTEGER := 7;
33 33
34 34 pindex : INTEGER := 4;
35 35 paddr : INTEGER := 4;
36 36 pmask : INTEGER := 16#fff#;
37 37 pirq_ms : INTEGER := 0;
38 38 pirq_wfp : INTEGER := 1;
39 39
40 40 hindex : INTEGER := 2;
41 41
42 42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43 43
44 44 );
45 45 PORT (
46 46 clk : IN STD_LOGIC;
47 47 rstn : IN STD_LOGIC;
48 48 -- SAMPLE
49 49 sample_B : IN Samples(2 DOWNTO 0);
50 50 sample_E : IN Samples(4 DOWNTO 0);
51 51 sample_val : IN STD_LOGIC;
52 52 -- APB
53 53 apbi : IN apb_slv_in_type;
54 54 apbo : OUT apb_slv_out_type;
55 55 -- AHB
56 56 ahbi : IN AHB_Mst_In_Type;
57 57 ahbo : OUT AHB_Mst_Out_Type;
58 58 -- TIME
59 59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 61 --
62 62 data_shaping_BW : OUT STD_LOGIC;
63 63 --
64 64 --
65 65 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 66 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67 67
68 68 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
69 69
70 70 --debug
71 71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 72 --debug_f0_data_valid : OUT STD_LOGIC;
73 73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 74 --debug_f1_data_valid : OUT STD_LOGIC;
75 75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
76 76 --debug_f2_data_valid : OUT STD_LOGIC;
77 77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
78 78 --debug_f3_data_valid : OUT STD_LOGIC;
79 79
80 80 ---- debug FIFO_IN
81 81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
83 83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
85 85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
87 87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
89 89
90 90 ----debug FIFO OUT
91 91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
93 93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
95 95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
97 97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
99 99
100 100 ----debug DMA IN
101 101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
103 103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
105 105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
107 107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
109 109 );
110 110 END lpp_lfr;
111 111
112 112 ARCHITECTURE beh OF lpp_lfr IS
113 113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
114 114 SIGNAL sample_s : Samples(7 DOWNTO 0);
115 115 --
116 116 SIGNAL data_shaping_SP0 : STD_LOGIC;
117 117 SIGNAL data_shaping_SP1 : STD_LOGIC;
118 118 SIGNAL data_shaping_R0 : STD_LOGIC;
119 119 SIGNAL data_shaping_R1 : STD_LOGIC;
120 120 --
121 121 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 122 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 124 --
125 125 SIGNAL sample_f0_val : STD_LOGIC;
126 126 SIGNAL sample_f1_val : STD_LOGIC;
127 127 SIGNAL sample_f2_val : STD_LOGIC;
128 128 SIGNAL sample_f3_val : STD_LOGIC;
129 129 --
130 130 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 131 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 132 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 133 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 134 --
135 135 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
136 136 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138 138
139 139 -- SM
140 140 SIGNAL ready_matrix_f0 : STD_LOGIC;
141 141 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
142 142 SIGNAL ready_matrix_f1 : STD_LOGIC;
143 143 SIGNAL ready_matrix_f2 : STD_LOGIC;
144 144 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
145 145 SIGNAL error_bad_component_error : STD_LOGIC;
146 146 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 147 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
148 148 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
149 149 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
150 150 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
151 151 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
152 152 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
153 153 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
154 154 SIGNAL config_active_interruption_onError : STD_LOGIC;
155 155 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 156 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 159
160 160 -- WFP
161 161 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 162 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 163 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 164 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 165 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 166 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
167 167 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
168 168 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 169 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
170 170
171 171 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
172 172 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
173 173 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
174 174 SIGNAL enable_f0 : STD_LOGIC;
175 175 SIGNAL enable_f1 : STD_LOGIC;
176 176 SIGNAL enable_f2 : STD_LOGIC;
177 177 SIGNAL enable_f3 : STD_LOGIC;
178 178 SIGNAL burst_f0 : STD_LOGIC;
179 179 SIGNAL burst_f1 : STD_LOGIC;
180 180 SIGNAL burst_f2 : STD_LOGIC;
181 181 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 182 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 183 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 184 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 185
186 186 SIGNAL run : STD_LOGIC;
187 187 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
188 188
189 189 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 190 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 191 SIGNAL data_f0_data_out_valid : STD_LOGIC;
192 192 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
193 193 SIGNAL data_f0_data_out_ren : STD_LOGIC;
194 194 --f1
195 195 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 196 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 197 SIGNAL data_f1_data_out_valid : STD_LOGIC;
198 198 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
199 199 SIGNAL data_f1_data_out_ren : STD_LOGIC;
200 200 --f2
201 201 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 202 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 203 SIGNAL data_f2_data_out_valid : STD_LOGIC;
204 204 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
205 205 SIGNAL data_f2_data_out_ren : STD_LOGIC;
206 206 --f3
207 207 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 208 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 209 SIGNAL data_f3_data_out_valid : STD_LOGIC;
210 210 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
211 211 SIGNAL data_f3_data_out_ren : STD_LOGIC;
212 212
213 213 -----------------------------------------------------------------------------
214 214 --
215 215 -----------------------------------------------------------------------------
216 216 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
218 218 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
219 219 --f1
220 220 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 221 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
222 222 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
223 223 --f2
224 224 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 225 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
226 226 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
227 227 --f3
228 228 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
229 229 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
230 230 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
231 231
232 232 -----------------------------------------------------------------------------
233 233 -- DMA RR
234 234 -----------------------------------------------------------------------------
235 235 SIGNAL dma_sel_valid : STD_LOGIC;
236 236 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
237 237 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
238 238 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
239 239 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
240 240
241 241 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
242 242 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
243 243
244 244 -----------------------------------------------------------------------------
245 245 -- DMA_REG
246 246 -----------------------------------------------------------------------------
247 247 SIGNAL ongoing_reg : STD_LOGIC;
248 248 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
249 249 SIGNAL dma_send_reg : STD_LOGIC;
250 250 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
251 251 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 252 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
253 253
254 254
255 255 -----------------------------------------------------------------------------
256 256 -- DMA
257 257 -----------------------------------------------------------------------------
258 258 SIGNAL dma_send : STD_LOGIC;
259 259 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
260 260 SIGNAL dma_done : STD_LOGIC;
261 261 SIGNAL dma_ren : STD_LOGIC;
262 262 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
263 263 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
264 264 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
265 265
266 266 -----------------------------------------------------------------------------
267 267 -- MS
268 268 -----------------------------------------------------------------------------
269 269
270 270 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 271 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 272 SIGNAL data_ms_valid : STD_LOGIC;
273 273 SIGNAL data_ms_valid_burst : STD_LOGIC;
274 274 SIGNAL data_ms_ren : STD_LOGIC;
275 275 SIGNAL data_ms_done : STD_LOGIC;
276 276 SIGNAL dma_ms_ongoing : STD_LOGIC;
277 277
278 278 SIGNAL run_ms : STD_LOGIC;
279 279 SIGNAL ms_softandhard_rstn : STD_LOGIC;
280 280
281 281 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
282 282 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
283 283 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
284 284 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
285 285
286 286
287 287 SIGNAL error_buffer_full : STD_LOGIC;
288 288 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
289 289
290 290 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
291 291 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
292 292
293 293 BEGIN
294 294
295 295 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
296 296 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
297 297
298 298 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
299 299 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
300 300 --END GENERATE all_channel;
301 301
302 302 -----------------------------------------------------------------------------
303 303 lpp_lfr_filter_1 : lpp_lfr_filter
304 304 GENERIC MAP (
305 305 Mem_use => Mem_use)
306 306 PORT MAP (
307 307 sample => sample_s,
308 308 sample_val => sample_val,
309 309 clk => clk,
310 310 rstn => rstn,
311 311 data_shaping_SP0 => data_shaping_SP0,
312 312 data_shaping_SP1 => data_shaping_SP1,
313 313 data_shaping_R0 => data_shaping_R0,
314 314 data_shaping_R1 => data_shaping_R1,
315 315 sample_f0_val => sample_f0_val,
316 316 sample_f1_val => sample_f1_val,
317 317 sample_f2_val => sample_f2_val,
318 318 sample_f3_val => sample_f3_val,
319 319 sample_f0_wdata => sample_f0_data,
320 320 sample_f1_wdata => sample_f1_data,
321 321 sample_f2_wdata => sample_f2_data,
322 322 sample_f3_wdata => sample_f3_data);
323 323
324 324 -----------------------------------------------------------------------------
325 325 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
326 326 GENERIC MAP (
327 327 nb_data_by_buffer_size => nb_data_by_buffer_size,
328 328 nb_word_by_buffer_size => nb_word_by_buffer_size,
329 329 nb_snapshot_param_size => nb_snapshot_param_size,
330 330 delta_vector_size => delta_vector_size,
331 331 delta_vector_size_f0_2 => delta_vector_size_f0_2,
332 332 pindex => pindex,
333 333 paddr => paddr,
334 334 pmask => pmask,
335 335 pirq_ms => pirq_ms,
336 336 pirq_wfp => pirq_wfp,
337 337 top_lfr_version => top_lfr_version)
338 338 PORT MAP (
339 339 HCLK => clk,
340 340 HRESETn => rstn,
341 341 apbi => apbi,
342 342 apbo => apbo,
343 343
344 344 run_ms => run_ms,
345 345
346 346 ready_matrix_f0 => ready_matrix_f0,
347 347 -- ready_matrix_f0_1 => ready_matrix_f0_1,
348 348 ready_matrix_f1 => ready_matrix_f1,
349 349 ready_matrix_f2 => ready_matrix_f2,
350 350 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
351 351 error_bad_component_error => error_bad_component_error,
352 352 error_buffer_full => error_buffer_full, -- TODO
353 353 error_input_fifo_write => error_input_fifo_write, -- TODO
354 354 -- debug_reg => debug_reg,
355 355 status_ready_matrix_f0 => status_ready_matrix_f0,
356 356 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
357 357 status_ready_matrix_f1 => status_ready_matrix_f1,
358 358 status_ready_matrix_f2 => status_ready_matrix_f2,
359 359 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
360 360 -- status_error_bad_component_error => status_error_bad_component_error,
361 361 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
362 362 config_active_interruption_onError => config_active_interruption_onError,
363 363
364 364 matrix_time_f0 => matrix_time_f0,
365 365 -- matrix_time_f0_1 => matrix_time_f0_1,
366 366 matrix_time_f1 => matrix_time_f1,
367 367 matrix_time_f2 => matrix_time_f2,
368 368
369 369 addr_matrix_f0 => addr_matrix_f0,
370 370 -- addr_matrix_f0_1 => addr_matrix_f0_1,
371 371 addr_matrix_f1 => addr_matrix_f1,
372 372 addr_matrix_f2 => addr_matrix_f2,
373 373 -------------------------------------------------------------------------
374 374 status_full => status_full,
375 375 status_full_ack => status_full_ack,
376 376 status_full_err => status_full_err,
377 377 status_new_err => status_new_err,
378 378 data_shaping_BW => data_shaping_BW,
379 379 data_shaping_SP0 => data_shaping_SP0,
380 380 data_shaping_SP1 => data_shaping_SP1,
381 381 data_shaping_R0 => data_shaping_R0,
382 382 data_shaping_R1 => data_shaping_R1,
383 383 delta_snapshot => delta_snapshot,
384 384 delta_f0 => delta_f0,
385 385 delta_f0_2 => delta_f0_2,
386 386 delta_f1 => delta_f1,
387 387 delta_f2 => delta_f2,
388 388 nb_data_by_buffer => nb_data_by_buffer,
389 389 nb_word_by_buffer => nb_word_by_buffer,
390 390 nb_snapshot_param => nb_snapshot_param,
391 391 enable_f0 => enable_f0,
392 392 enable_f1 => enable_f1,
393 393 enable_f2 => enable_f2,
394 394 enable_f3 => enable_f3,
395 395 burst_f0 => burst_f0,
396 396 burst_f1 => burst_f1,
397 397 burst_f2 => burst_f2,
398 398 run => run,
399 399 addr_data_f0 => addr_data_f0,
400 400 addr_data_f1 => addr_data_f1,
401 401 addr_data_f2 => addr_data_f2,
402 402 addr_data_f3 => addr_data_f3,
403 403 start_date => start_date,
404 404 debug_signal => debug_signal);
405 405
406 406 -----------------------------------------------------------------------------
407 407 -----------------------------------------------------------------------------
408 408 lpp_waveform_1 : lpp_waveform
409 409 GENERIC MAP (
410 410 tech => inferred,
411 411 data_size => 6*16,
412 412 nb_data_by_buffer_size => nb_data_by_buffer_size,
413 413 nb_word_by_buffer_size => nb_word_by_buffer_size,
414 414 nb_snapshot_param_size => nb_snapshot_param_size,
415 415 delta_vector_size => delta_vector_size,
416 416 delta_vector_size_f0_2 => delta_vector_size_f0_2
417 417 )
418 418 PORT MAP (
419 419 clk => clk,
420 420 rstn => rstn,
421 421
422 422 reg_run => run,
423 423 reg_start_date => start_date,
424 424 reg_delta_snapshot => delta_snapshot,
425 425 reg_delta_f0 => delta_f0,
426 426 reg_delta_f0_2 => delta_f0_2,
427 427 reg_delta_f1 => delta_f1,
428 428 reg_delta_f2 => delta_f2,
429 429
430 430 enable_f0 => enable_f0,
431 431 enable_f1 => enable_f1,
432 432 enable_f2 => enable_f2,
433 433 enable_f3 => enable_f3,
434 434 burst_f0 => burst_f0,
435 435 burst_f1 => burst_f1,
436 436 burst_f2 => burst_f2,
437 437
438 438 nb_data_by_buffer => nb_data_by_buffer,
439 439 nb_word_by_buffer => nb_word_by_buffer,
440 440 nb_snapshot_param => nb_snapshot_param,
441 441 status_full => status_full,
442 442 status_full_ack => status_full_ack,
443 443 status_full_err => status_full_err,
444 444 status_new_err => status_new_err,
445 445
446 446 coarse_time => coarse_time,
447 447 fine_time => fine_time,
448 448
449 449 --f0
450 450 addr_data_f0 => addr_data_f0,
451 451 data_f0_in_valid => sample_f0_val,
452 452 data_f0_in => sample_f0_data,
453 453 --f1
454 454 addr_data_f1 => addr_data_f1,
455 455 data_f1_in_valid => sample_f1_val,
456 456 data_f1_in => sample_f1_data,
457 457 --f2
458 458 addr_data_f2 => addr_data_f2,
459 459 data_f2_in_valid => sample_f2_val,
460 460 data_f2_in => sample_f2_data,
461 461 --f3
462 462 addr_data_f3 => addr_data_f3,
463 463 data_f3_in_valid => sample_f3_val,
464 464 data_f3_in => sample_f3_data,
465 465 -- OUTPUT -- DMA interface
466 466 --f0
467 467 data_f0_addr_out => data_f0_addr_out_s,
468 468 data_f0_data_out => data_f0_data_out,
469 469 data_f0_data_out_valid => data_f0_data_out_valid_s,
470 470 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
471 471 data_f0_data_out_ren => data_f0_data_out_ren,
472 472 --f1
473 473 data_f1_addr_out => data_f1_addr_out_s,
474 474 data_f1_data_out => data_f1_data_out,
475 475 data_f1_data_out_valid => data_f1_data_out_valid_s,
476 476 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
477 477 data_f1_data_out_ren => data_f1_data_out_ren,
478 478 --f2
479 479 data_f2_addr_out => data_f2_addr_out_s,
480 480 data_f2_data_out => data_f2_data_out,
481 481 data_f2_data_out_valid => data_f2_data_out_valid_s,
482 482 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
483 483 data_f2_data_out_ren => data_f2_data_out_ren,
484 484 --f3
485 485 data_f3_addr_out => data_f3_addr_out_s,
486 486 data_f3_data_out => data_f3_data_out,
487 487 data_f3_data_out_valid => data_f3_data_out_valid_s,
488 488 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
489 489 data_f3_data_out_ren => data_f3_data_out_ren ,
490 490
491 491 -------------------------------------------------------------------------
492 492 observation_reg => OPEN
493 493
494 494 );
495 495
496 496
497 497 -----------------------------------------------------------------------------
498 498 -- TEMP
499 499 -----------------------------------------------------------------------------
500 500
501 501 PROCESS (clk, rstn)
502 502 BEGIN -- PROCESS
503 503 IF rstn = '0' THEN -- asynchronous reset (active low)
504 504 data_f0_data_out_valid <= '0';
505 505 data_f0_data_out_valid_burst <= '0';
506 506 data_f1_data_out_valid <= '0';
507 507 data_f1_data_out_valid_burst <= '0';
508 508 data_f2_data_out_valid <= '0';
509 509 data_f2_data_out_valid_burst <= '0';
510 510 data_f3_data_out_valid <= '0';
511 511 data_f3_data_out_valid_burst <= '0';
512 512 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
513 513 data_f0_data_out_valid <= data_f0_data_out_valid_s;
514 514 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
515 515 data_f1_data_out_valid <= data_f1_data_out_valid_s;
516 516 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
517 517 data_f2_data_out_valid <= data_f2_data_out_valid_s;
518 518 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
519 519 data_f3_data_out_valid <= data_f3_data_out_valid_s;
520 520 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
521 521 END IF;
522 522 END PROCESS;
523 523
524 524 data_f0_addr_out <= data_f0_addr_out_s;
525 525 data_f1_addr_out <= data_f1_addr_out_s;
526 526 data_f2_addr_out <= data_f2_addr_out_s;
527 527 data_f3_addr_out <= data_f3_addr_out_s;
528 528
529 529 -----------------------------------------------------------------------------
530 530 -- RoundRobin Selection For DMA
531 531 -----------------------------------------------------------------------------
532 532
533 533 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
534 534 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
535 535 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
536 536 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
537 537
538 538 RR_Arbiter_4_1 : RR_Arbiter_4
539 539 PORT MAP (
540 540 clk => clk,
541 541 rstn => rstn,
542 542 in_valid => dma_rr_valid,
543 543 out_grant => dma_rr_grant_s);
544 544
545 545 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
546 546 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
547 547 dma_rr_valid_ms(2) <= '0';
548 548 dma_rr_valid_ms(3) <= '0';
549 549
550 550 RR_Arbiter_4_2 : RR_Arbiter_4
551 551 PORT MAP (
552 552 clk => clk,
553 553 rstn => rstn,
554 554 in_valid => dma_rr_valid_ms,
555 555 out_grant => dma_rr_grant_ms);
556 556
557 557 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
558 558
559 559
560 560 -----------------------------------------------------------------------------
561 561 -- in : dma_rr_grant
562 562 -- send
563 563 -- out : dma_sel
564 564 -- dma_valid_burst
565 565 -- dma_sel_valid
566 566 -----------------------------------------------------------------------------
567 567 PROCESS (clk, rstn)
568 568 BEGIN -- PROCESS
569 569 IF rstn = '0' THEN -- asynchronous reset (active low)
570 570 dma_sel <= (OTHERS => '0');
571 571 dma_send <= '0';
572 572 dma_valid_burst <= '0';
573 573 data_ms_done <= '0';
574 574 dma_ms_ongoing <= '0';
575 575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
576 576 IF run = '1' THEN
577 577 data_ms_done <= '0';
578 578 IF dma_sel = "00000" OR dma_done = '1' THEN
579 579 dma_sel <= dma_rr_grant;
580 580 IF dma_rr_grant(0) = '1' THEN
581 581 dma_ms_ongoing <= '0';
582 582 dma_send <= '1';
583 583 dma_valid_burst <= data_f0_data_out_valid_burst;
584 584 dma_sel_valid <= data_f0_data_out_valid;
585 585 ELSIF dma_rr_grant(1) = '1' THEN
586 586 dma_ms_ongoing <= '0';
587 587 dma_send <= '1';
588 588 dma_valid_burst <= data_f1_data_out_valid_burst;
589 589 dma_sel_valid <= data_f1_data_out_valid;
590 590 ELSIF dma_rr_grant(2) = '1' THEN
591 591 dma_ms_ongoing <= '0';
592 592 dma_send <= '1';
593 593 dma_valid_burst <= data_f2_data_out_valid_burst;
594 594 dma_sel_valid <= data_f2_data_out_valid;
595 595 ELSIF dma_rr_grant(3) = '1' THEN
596 596 dma_ms_ongoing <= '0';
597 597 dma_send <= '1';
598 598 dma_valid_burst <= data_f3_data_out_valid_burst;
599 599 dma_sel_valid <= data_f3_data_out_valid;
600 600 ELSIF dma_rr_grant(4) = '1' THEN
601 601 dma_ms_ongoing <= '1';
602 602 dma_send <= '1';
603 603 dma_valid_burst <= data_ms_valid_burst;
604 604 dma_sel_valid <= data_ms_valid;
605 605 --ELSE
606 606 --dma_ms_ongoing <= '0';
607 607 END IF;
608 608
609 609 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
610 610 data_ms_done <= '1';
611 611 END IF;
612 612 ELSE
613 613 dma_sel <= dma_sel;
614 614 dma_send <= '0';
615 615 END IF;
616 616 ELSE
617 617 data_ms_done <= '0';
618 618 dma_sel <= (OTHERS => '0');
619 619 dma_send <= '0';
620 620 dma_valid_burst <= '0';
621 621 END IF;
622 622 END IF;
623 623 END PROCESS;
624 624
625 625
626 626 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
627 627 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
628 628 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
629 629 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
630 630 data_ms_addr;
631 631
632 632 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
633 633 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
634 634 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
635 635 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
636 636 data_ms_data;
637 637
638 638 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
639 639 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
640 640 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
641 641 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
642 642 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
643 643
644 644 dma_data_2 <= dma_data;
645 645
646 646
647 647 -----------------------------------------------------------------------------
648 648 -- DMA
649 649 -----------------------------------------------------------------------------
650 650 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
651 651 GENERIC MAP (
652 652 tech => inferred,
653 653 hindex => hindex)
654 654 PORT MAP (
655 655 HCLK => clk,
656 656 HRESETn => rstn,
657 657 run => run,
658 658 AHB_Master_In => ahbi,
659 659 AHB_Master_Out => ahbo,
660 660
661 661 send => dma_send,
662 662 valid_burst => dma_valid_burst,
663 663 done => dma_done,
664 664 ren => dma_ren,
665 665 address => dma_address,
666 666 data => dma_data_2);
667 667
668 668 -----------------------------------------------------------------------------
669 669 -- Matrix Spectral
670 670 -----------------------------------------------------------------------------
671 671 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
672 672 NOT(sample_f0_val) & NOT(sample_f0_val);
673 673 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
674 674 NOT(sample_f1_val) & NOT(sample_f1_val);
675 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
676 NOT(sample_f3_val) & NOT(sample_f3_val);
675 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
676 NOT(sample_f2_val) & NOT(sample_f2_val);
677 677
678 678 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
679 679 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
680 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
680 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
681 681
682 682 -------------------------------------------------------------------------------
683 683
684 684 ms_softandhard_rstn <= rstn AND run_ms AND run;
685 685
686 686 -----------------------------------------------------------------------------
687 687 lpp_lfr_ms_1 : lpp_lfr_ms
688 688 GENERIC MAP (
689 689 Mem_use => Mem_use)
690 690 PORT MAP (
691 691 clk => clk,
692 692 rstn => ms_softandhard_rstn, --rstn,
693 693
694 694 coarse_time => coarse_time,
695 695 fine_time => fine_time,
696 696
697 697 sample_f0_wen => sample_f0_wen,
698 698 sample_f0_wdata => sample_f0_wdata,
699 699 sample_f1_wen => sample_f1_wen,
700 700 sample_f1_wdata => sample_f1_wdata,
701 701 sample_f2_wen => sample_f2_wen, -- TODO
702 702 sample_f2_wdata => sample_f2_wdata,-- TODO
703 703
704 704 dma_addr => data_ms_addr, --
705 705 dma_data => data_ms_data, --
706 706 dma_valid => data_ms_valid, --
707 707 dma_valid_burst => data_ms_valid_burst, --
708 708 dma_ren => data_ms_ren, --
709 709 dma_done => data_ms_done, --
710 710
711 711 ready_matrix_f0 => ready_matrix_f0,
712 712 ready_matrix_f1 => ready_matrix_f1,
713 713 ready_matrix_f2 => ready_matrix_f2,
714 714 error_bad_component_error => error_bad_component_error,
715 715 error_buffer_full => error_buffer_full,
716 716 error_input_fifo_write => error_input_fifo_write,
717 717
718 718 debug_reg => debug_ms,--observation_reg,
719 719 observation_vector_0 => observation_vector_0,
720 720 observation_vector_1 => observation_vector_1,
721 721
722 722 status_ready_matrix_f0 => status_ready_matrix_f0,
723 723 status_ready_matrix_f1 => status_ready_matrix_f1,
724 724 status_ready_matrix_f2 => status_ready_matrix_f2,
725 725 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
726 726 config_active_interruption_onError => config_active_interruption_onError,
727 727 addr_matrix_f0 => addr_matrix_f0,
728 728 addr_matrix_f1 => addr_matrix_f1,
729 729 addr_matrix_f2 => addr_matrix_f2,
730 730
731 731 matrix_time_f0 => matrix_time_f0,
732 732 matrix_time_f1 => matrix_time_f1,
733 733 matrix_time_f2 => matrix_time_f2);
734 734
735 735 -----------------------------------------------------------------------------
736 736
737 737
738 738 observation_reg(31 DOWNTO 0) <=
739 739 dma_sel(4) & -- 31
740 740 dma_ms_ongoing & -- 30
741 741 data_ms_done & -- 29
742 742 dma_done & -- 28
743 743 ms_softandhard_rstn & --27
744 744 debug_ms(14 DOWNTO 12) & -- 26 .. 24
745 745 debug_ms(11 DOWNTO 0) & -- 23 .. 12
746 746 debug_signal(11 DOWNTO 0); -- 11 .. 0
747 747
748 END beh;
748 END beh; No newline at end of file
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