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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
36
37 ENTITY lpp_top_apbreg IS
38 GENERIC (
39 pindex : INTEGER := 4;
40 paddr : INTEGER := 4;
41 pmask : INTEGER := 16#fff#;
42 pirq : INTEGER := 0);
43 PORT (
44 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
47
48 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51
52 -- IN
53 ready_matrix_f0_0 : IN STD_LOGIC;
54 ready_matrix_f0_1 : IN STD_LOGIC;
55 ready_matrix_f1 : IN STD_LOGIC;
56 ready_matrix_f2 : IN STD_LOGIC;
57 error_anticipating_empty_fifo : IN STD_LOGIC;
58 error_bad_component_error : IN STD_LOGIC;
59 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60
61 -- OUT
62 status_ready_matrix_f0_0 : OUT STD_LOGIC;
63 status_ready_matrix_f0_1 : OUT STD_LOGIC;
64 status_ready_matrix_f1 : OUT STD_LOGIC;
65 status_ready_matrix_f2 : OUT STD_LOGIC;
66 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
67 status_error_bad_component_error : OUT STD_LOGIC;
68
69 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
70 config_active_interruption_onError : OUT STD_LOGIC;
71 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
75 );
76
77 END lpp_top_apbreg;
78
79 ARCHITECTURE beh OF lpp_top_apbreg IS
80
81 CONSTANT REVISION : INTEGER := 1;
82
83 CONSTANT pconfig : apb_config_type := (
84 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
85 1 => apb_iobar(paddr, pmask));
86
87 TYPE lpp_dma_regs IS RECORD
88 config_active_interruption_onNewMatrix : STD_LOGIC;
89 config_active_interruption_onError : STD_LOGIC;
90 status_ready_matrix_f0_0 : STD_LOGIC;
91 status_ready_matrix_f0_1 : STD_LOGIC;
92 status_ready_matrix_f1 : STD_LOGIC;
93 status_ready_matrix_f2 : STD_LOGIC;
94 status_error_anticipating_empty_fifo : STD_LOGIC;
95 status_error_bad_component_error : STD_LOGIC;
96 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 END RECORD;
101
102 SIGNAL reg : lpp_dma_regs;
103
104 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
105
106 BEGIN -- beh
107
108 status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0;
109 status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1;
110 status_ready_matrix_f1 <= reg.status_ready_matrix_f1;
111 status_ready_matrix_f2 <= reg.status_ready_matrix_f2;
112 status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo;
113 status_error_bad_component_error <= reg.status_error_bad_component_error;
114
115 config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix;
116 config_active_interruption_onError <= reg.config_active_interruption_onError;
117 addr_matrix_f0_0 <= reg.addr_matrix_f0_0;
118 addr_matrix_f0_1 <= reg.addr_matrix_f0_1;
119 addr_matrix_f1 <= reg.addr_matrix_f1;
120 addr_matrix_f2 <= reg.addr_matrix_f2;
121
122 lpp_top_apbreg : PROCESS (HCLK, HRESETn)
123 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
124 BEGIN -- PROCESS lpp_dma_top
125 IF HRESETn = '0' THEN -- asynchronous reset (active low)
126 reg.config_active_interruption_onNewMatrix <= '0';
127 reg.config_active_interruption_onError <= '0';
128 reg.status_ready_matrix_f0_0 <= '0';
129 reg.status_ready_matrix_f0_1 <= '0';
130 reg.status_ready_matrix_f1 <= '0';
131 reg.status_ready_matrix_f2 <= '0';
132 reg.status_error_anticipating_empty_fifo <= '0';
133 reg.status_error_bad_component_error <= '0';
134 reg.addr_matrix_f0_0 <= (OTHERS => '0');
135 reg.addr_matrix_f0_1 <= (OTHERS => '0');
136 reg.addr_matrix_f1 <= (OTHERS => '0');
137 reg.addr_matrix_f2 <= (OTHERS => '0');
138 prdata <= (OTHERS => '0');
139 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
140
141 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
142 reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
143 reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1;
144 reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2;
145
146 reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
147 reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error;
148
149 paddr := "000000";
150 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
151 prdata <= (OTHERS => '0');
152 IF apbi.psel(pindex) = '1' THEN
153 -- APB DMA READ --
154 CASE paddr(7 DOWNTO 2) IS
155 WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix;
156 prdata(1) <= reg.config_active_interruption_onError;
157 WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0;
158 prdata(1) <= reg.status_ready_matrix_f0_1;
159 prdata(2) <= reg.status_ready_matrix_f1;
160 prdata(3) <= reg.status_ready_matrix_f2;
161 prdata(4) <= reg.status_error_anticipating_empty_fifo;
162 prdata(5) <= reg.status_error_bad_component_error;
163 WHEN "000010" => prdata <= reg.addr_matrix_f0_0;
164 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
165 WHEN "000100" => prdata <= reg.addr_matrix_f1;
166 WHEN "000101" => prdata <= reg.addr_matrix_f2;
167 WHEN "000110" => prdata <= debug_reg;
168 WHEN OTHERS => NULL;
169 END CASE;
170 IF (apbi.pwrite AND apbi.penable) = '1' THEN
171 -- APB DMA WRITE --
172 CASE paddr(7 DOWNTO 2) IS
173 WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
174 reg.config_active_interruption_onError <= apbi.pwdata(1);
175 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
176 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
177 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
178 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
179 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
180 reg.status_error_bad_component_error <= apbi.pwdata(5);
181 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
182 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
183 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
184 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
185 WHEN OTHERS => NULL;
186 END CASE;
187 END IF;
188 END IF;
189 END IF;
190 END PROCESS lpp_top_apbreg;
191
192 apbo.pirq <= (OTHERS => '0');
193 apbo.pindex <= pindex;
194 apbo.pconfig <= pconfig;
195 apbo.prdata <= prdata;
196
197
198 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY grlib;
4 USE grlib.amba.ALL;
5 USE grlib.stdlib.ALL;
6 USE grlib.devices.ALL;
7 USE GRLIB.DMA2AHB_Package.ALL;
8 LIBRARY lpp;
9 USE lpp.lpp_ad_conv.ALL;
10 USE lpp.iir_filter.ALL;
11 USE lpp.FILTERcfg.ALL;
12 USE lpp.lpp_memory.ALL;
13 USE lpp.lpp_top_lfr_pkg.ALL;
14 USE lpp.lpp_dma_pkg.ALL;
15 LIBRARY techmap;
16 USE techmap.gencomp.ALL;
17
18 ENTITY lpp_top_lfr IS
19 GENERIC(
20 tech : INTEGER := 0;
21 hindex_SpectralMatrix : INTEGER := 2;
22 pindex : INTEGER := 4;
23 paddr : INTEGER := 4;
24 pmask : INTEGER := 16#fff#;
25 pirq : INTEGER := 0
26 );
27 PORT (
28 -- ADS7886
29 cnv_run : IN STD_LOGIC;
30 cnv : OUT STD_LOGIC;
31 sck : OUT STD_LOGIC;
32 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
33 --
34 cnv_clk : IN STD_LOGIC; -- 49 MHz
35 cnv_rstn : IN STD_LOGIC;
36 --
37 clk : IN STD_LOGIC; -- 25 MHz
38 rstn : IN STD_LOGIC;
39 --
40 apbi : IN apb_slv_in_type;
41 apbo : OUT apb_slv_out_type;
42
43 -- AMBA AHB Master Interface
44 AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type;
45 AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type
46 );
47 END lpp_top_lfr;
48
49 ARCHITECTURE tb OF lpp_top_lfr IS
50
51 -----------------------------------------------------------------------------
52 -- f0
53 SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
54 SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
55 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
56 --
57 SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
58 SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
59 SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
60 SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
61 --
62 SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
63 SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
64 SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
66 -----------------------------------------------------------------------------
67 -- f1
68 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
69 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
70 --
71 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
72 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
73 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 -----------------------------------------------------------------------------
76 -- f2
77 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
79 -----------------------------------------------------------------------------
80 -- f3
81 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
83 --
84 SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
86 SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 -----------------------------------------------------------------------------
89
90 -----------------------------------------------------------------------------
91 -- SPECTRAL MATRIX
92 -----------------------------------------------------------------------------
93 SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
94 SIGNAL fifo_empty : STD_LOGIC;
95 SIGNAL fifo_ren : STD_LOGIC;
96 SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL header_val : STD_LOGIC;
98 SIGNAL header_ack : STD_LOGIC;
99
100 -----------------------------------------------------------------------------
101 -- APB REG
102 -----------------------------------------------------------------------------
103 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
104 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
105 SIGNAL ready_matrix_f1 : STD_LOGIC;
106 SIGNAL ready_matrix_f2 : STD_LOGIC;
107 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
108 SIGNAL error_bad_component_error : STD_LOGIC;
109 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
111 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
113 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
114 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
115 SIGNAL status_error_bad_component_error : STD_LOGIC;
116 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
117 SIGNAL config_active_interruption_onError : STD_LOGIC;
118 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
122
123 BEGIN
124
125 -----------------------------------------------------------------------------
126 -- CNA + FILTER
127 -----------------------------------------------------------------------------
128 lpp_top_acq_1 : lpp_top_acq
129 GENERIC MAP (
130 tech => tech)
131 PORT MAP (
132 cnv_run => cnv_run,
133 cnv => cnv,
134 sck => sck,
135 sdo => sdo,
136 cnv_clk => cnv_clk,
137 cnv_rstn => cnv_rstn,
138 clk => clk,
139 rstn => rstn,
140
141 sample_f0_0_wen => sample_f0_0_wen,
142 sample_f0_1_wen => sample_f0_1_wen,
143 sample_f0_wdata => sample_f0_wdata,
144 sample_f1_wen => sample_f1_wen,
145 sample_f1_wdata => sample_f1_wdata,
146 sample_f2_wen => sample_f2_wen,
147 sample_f2_wdata => sample_f2_wdata,
148 sample_f3_wen => sample_f3_wen,
149 sample_f3_wdata => sample_f3_wdata);
150
151 -----------------------------------------------------------------------------
152 -- FIFO
153 -----------------------------------------------------------------------------
154
155 lppFIFO_f0_0 : lppFIFOxN
156 GENERIC MAP (
157 tech => tech,
158 Data_sz => 18,
159 FifoCnt => 5,
160 Enable_ReUse => '0')
161 PORT MAP (
162 rst => rstn,
163 wclk => clk,
164 rclk => clk,
165 ReUse => (OTHERS => '0'),
166
167 wen => sample_f0_0_wen,
168 ren => sample_f0_0_ren,
169 wdata => sample_f0_wdata,
170 rdata => sample_f0_0_rdata,
171 full => sample_f0_0_full,
172 empty => sample_f0_0_empty);
173
174 lppFIFO_f0_1 : lppFIFOxN
175 GENERIC MAP (
176 tech => tech,
177 Data_sz => 18,
178 FifoCnt => 5,
179 Enable_ReUse => '0')
180 PORT MAP (
181 rst => rstn,
182 wclk => clk,
183 rclk => clk,
184 ReUse => (OTHERS => '0'),
185
186 wen => sample_f0_1_wen,
187 ren => sample_f0_1_ren,
188 wdata => sample_f0_wdata,
189 rdata => sample_f0_1_rdata,
190 full => sample_f0_1_full,
191 empty => sample_f0_1_empty);
192
193 lppFIFO_f1 : lppFIFOxN
194 GENERIC MAP (
195 tech => tech,
196 Data_sz => 18,
197 FifoCnt => 5,
198 Enable_ReUse => '0')
199 PORT MAP (
200 rst => rstn,
201 wclk => clk,
202 rclk => clk,
203 ReUse => (OTHERS => '0'),
204
205 wen => sample_f1_wen,
206 ren => sample_f1_ren,
207 wdata => sample_f1_wdata,
208 rdata => sample_f1_rdata,
209 full => sample_f1_full,
210 empty => sample_f1_empty);
211
212 lppFIFO_f3 : lppFIFOxN
213 GENERIC MAP (
214 tech => tech,
215 Data_sz => 18,
216 FifoCnt => 5,
217 Enable_ReUse => '0')
218 PORT MAP (
219 rst => rstn,
220 wclk => clk,
221 rclk => clk,
222 ReUse => (OTHERS => '0'),
223
224 wen => sample_f3_wen,
225 ren => sample_f3_ren,
226 wdata => sample_f3_wdata,
227 rdata => sample_f3_rdata,
228 full => sample_f3_full,
229 empty => sample_f3_empty);
230
231 -----------------------------------------------------------------------------
232 -- SPECTRAL MATRIX
233 -----------------------------------------------------------------------------
234
235 -----------------------------------------------------------------------------
236 -- DMA SPECTRAL MATRIX
237 -----------------------------------------------------------------------------
238 lpp_dma_ip_1 : lpp_dma_ip
239 GENERIC MAP (
240 tech => tech,
241 hindex => hindex_SpectralMatrix)
242 PORT MAP (
243 HCLK => clk,
244 HRESETn => rstn,
245 AHB_Master_In => AHB_DMA_SpectralMatrix_In,
246 AHB_Master_Out => AHB_DMA_SpectralMatrix_Out,
247
248 -- Connect to Spectral Matrix --
249 fifo_data => fifo_data,
250 fifo_empty => fifo_empty,
251 fifo_ren => fifo_ren,
252 header => header,
253 header_val => header_val,
254 header_ack => header_ack,
255
256 -- APB REG
257
258 ready_matrix_f0_0 => ready_matrix_f0_0,
259 ready_matrix_f0_1 => ready_matrix_f0_1,
260 ready_matrix_f1 => ready_matrix_f1,
261 ready_matrix_f2 => ready_matrix_f2,
262 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
263 error_bad_component_error => error_bad_component_error,
264 debug_reg => debug_reg,
265 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
266 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
267 status_ready_matrix_f1 => status_ready_matrix_f1,
268 status_ready_matrix_f2 => status_ready_matrix_f2,
269 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
270 status_error_bad_component_error => status_error_bad_component_error,
271 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
272 config_active_interruption_onError => config_active_interruption_onError,
273 addr_matrix_f0_0 => addr_matrix_f0_0,
274 addr_matrix_f0_1 => addr_matrix_f0_1,
275 addr_matrix_f1 => addr_matrix_f1,
276 addr_matrix_f2 => addr_matrix_f2);
277
278 lpp_top_apbreg_1 : lpp_top_apbreg
279 GENERIC MAP (
280 pindex => pindex,
281 paddr => paddr,
282 pmask => pmask,
283 pirq => pirq)
284 PORT MAP (
285 HCLK => clk,
286 HRESETn => rstn,
287 apbi => apbi,
288 apbo => apbo,
289
290 ready_matrix_f0_0 => ready_matrix_f0_0,
291 ready_matrix_f0_1 => ready_matrix_f0_1,
292 ready_matrix_f1 => ready_matrix_f1,
293 ready_matrix_f2 => ready_matrix_f2,
294 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
295 error_bad_component_error => error_bad_component_error,
296 debug_reg => debug_reg,
297 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
298 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
299 status_ready_matrix_f1 => status_ready_matrix_f1,
300 status_ready_matrix_f2 => status_ready_matrix_f2,
301 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
302 status_error_bad_component_error => status_error_bad_component_error,
303 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
304 config_active_interruption_onError => config_active_interruption_onError,
305 addr_matrix_f0_0 => addr_matrix_f0_0,
306 addr_matrix_f0_1 => addr_matrix_f0_1,
307 addr_matrix_f1 => addr_matrix_f1,
308 addr_matrix_f2 => addr_matrix_f2);
309
310
311 --TODO : add the irq alert for DMA matrix transfert ending
312 --TODO : add 5 bit register into APB to control the DATA SHIPING
313 --TODO : add Spectral Matrix (FFT + SP)
314 --TODO : add DMA for WaveForms Picker
315 --TODO : add APB Reg to control WaveForms Picker
316 --TODO : add WaveForms Picker
317
318 END tb;
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@@ -1,80 +1,80
1 SCRIPTSDIR=scripts/
1 SCRIPTSDIR=scripts/
2 LIBDIR=lib/
2 LIBDIR=lib/
3 BOARDSDIR=boards/
3 BOARDSDIR=boards/
4 DESIGNSDIR=designs/
4 DESIGNSDIR=designs/
5
5
6
6
7
8 .PHONY:doc
7 .PHONY:doc
9
8
10
9
11 all: help
10 all: help
12
11
13 help:
12 help:
14 @echo
13 @echo
15 @echo " batch targets:"
14 @echo " batch targets:"
16 @echo
15 @echo
17 @echo " make link : link lpp library to GRLIB at : $(GRLIB)"
16 @echo " make link : link lpp library to GRLIB at : $(GRLIB)"
18 @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)"
17 @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)"
19 @echo " make dist : create a tar file for using into an other computer"
18 @echo " make dist : create a tar file for using into an other computer"
20 @echo " make Patched-dist : create a tar file for with a patched grlib for using"
19 @echo " make Patched-dist : create a tar file for with a patched grlib for using"
21 @echo " into an other computer"
20 @echo " into an other computer"
22 @echo " make allGPL : add a GPL HEADER in all vhdl Files"
21 @echo " make allGPL : add a GPL HEADER in all vhdl Files"
23 @echo " make init : add a GPL HEADER in all vhdl Files, init all files"
22 @echo " make init : add a GPL HEADER in all vhdl Files, init all files"
24 @echo " make doc : make documentation for VHDL IPs"
23 @echo " make doc : make documentation for VHDL IPs"
25 @echo " make pdf : make pdf documentation for VHDL IPs"
24 @echo " make pdf : make pdf documentation for VHDL IPs"
26 @echo " make C-libs : make C drivers for APB devices"
25 @echo " make C-libs : make C drivers for APB devices"
27 @echo " binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes"
26 @echo " binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes"
28 @echo
27 @echo
29
28
30
29
31
30
32 allGPL:
31 allGPL:
33 @echo "Scanning VHDL files ..."
32 @echo "Scanning VHDL files ..."
34 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib
33 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib
35 @echo "Scanning C files ..."
34 @echo "Scanning C files ..."
36 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers
35 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers
37 @echo "Scanning H files ..."
36 @echo "Scanning H files ..."
38 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers
37 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers
39
38
40 init: C-libs
39 init: C-libs
41 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
40 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
42 sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp
41 sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp
43
42
44 C-libs:APB_devs
43 C-libs:APB_devs
45 make -C LPP_drivers
44 make -C LPP_drivers
46
45
47
46
48 APB_devs:
47 APB_devs:
49 sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh
48 sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh
50
49
51
50
52 Patch-GRLIB: init doc
51 Patch-GRLIB: init doc
53 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
52 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
54
53
55 link:
54 link:
56 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
55 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
56 sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB)
57
57
58 dist: init
58 dist: init
59 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
59 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
60
60
61
61
62 Patched-dist: Patch-GRLIB
62 Patched-dist: Patch-GRLIB
63 tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
63 tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
64
64
65
65
66 doc:
66 doc:
67 mkdir -p doc/html
67 mkdir -p doc/html
68 cp doc/ressources/*.jpg doc/html/
68 cp doc/ressources/*.jpg doc/html/
69 cp doc/ressources/doxygen.css doc/html/
69 cp doc/ressources/doxygen.css doc/html/
70 make -C lib/lpp doc
70 make -C lib/lpp doc
71 make -C LPP_drivers doc
71 make -C LPP_drivers doc
72
72
73
73
74 pdf: doc
74 pdf: doc
75 sh $(SCRIPTSDIR)/doc.sh
75 sh $(SCRIPTSDIR)/doc.sh
76
76
77
77
78
78
79
79
80
80
Show file before | Show file after | Hide comments
@@ -1,48 +1,49
1
1
2 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd
2 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd
8 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd
8 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd
9 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd
9 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd
10 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd
10 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd
11 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd
11 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd
13 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd
13 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd
14 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd
14 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd
15 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd
15 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd
16 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd
16 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd
17
17
18 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd
18 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd
19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
22 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
22 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
23
23
24 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
24 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
26 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
26 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
27 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
27 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
28
28
29 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd
29 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
32
32
33
33 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
34
34
35 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
35 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
36 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
36
37
37 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
38 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
38 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
39 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
39 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd
40 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd
40
41
41 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
42 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
42 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
43 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
43
44
44 vsim work.TB_Data_Acquisition
45 #vsim work.TB_Data_Acquisition
45
46
46 log -r *
47 #log -r *
47 do wave_data_acquisition.do
48 #do wave_data_acquisition.do
48 run 5 ms No newline at end of file
49 #run 5 ms No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,190 +1,186
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
23 -- 1.0 - initial version
24 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
24 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -------------------------------------------------------------------------------
25 -------------------------------------------------------------------------------
26 LIBRARY ieee;
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
28 USE ieee.numeric_std.ALL;
29 LIBRARY grlib;
29 LIBRARY grlib;
30 USE grlib.amba.ALL;
30 USE grlib.amba.ALL;
31 USE grlib.stdlib.ALL;
31 USE grlib.stdlib.ALL;
32 USE grlib.devices.ALL;
32 USE grlib.devices.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
34 --USE GRLIB.DMA2AHB_TestPackage.ALL;
34 --USE GRLIB.DMA2AHB_TestPackage.ALL;
35 LIBRARY lpp;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 LIBRARY techmap;
40 LIBRARY techmap;
41 USE techmap.gencomp.ALL;
41 USE techmap.gencomp.ALL;
42
42
43
43
44 ENTITY lpp_dma IS
44 ENTITY lpp_dma IS
45 GENERIC (
45 GENERIC (
46 tech : INTEGER := inferred;
46 tech : INTEGER := inferred;
47 hindex : INTEGER := 2;
47 hindex : INTEGER := 2;
48 pindex : INTEGER := 4;
48 pindex : INTEGER := 4;
49 paddr : INTEGER := 4;
49 paddr : INTEGER := 4;
50 pmask : INTEGER := 16#fff#;
50 pmask : INTEGER := 16#fff#;
51 pirq : INTEGER := 0);
51 pirq : INTEGER := 0);
52 PORT (
52 PORT (
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56
56
57 -- AMBA APB Slave Interface
57 -- AMBA APB Slave Interface
58 apbi : IN apb_slv_in_type;
58 apbi : IN apb_slv_in_type;
59 apbo : OUT apb_slv_out_type;
59 apbo : OUT apb_slv_out_type;
60
60
61 -- AMBA AHB Master Interface
61 -- AMBA AHB Master Interface
62 AHB_Master_In : IN AHB_Mst_In_Type;
62 AHB_Master_In : IN AHB_Mst_In_Type;
63 AHB_Master_Out : OUT AHB_Mst_Out_Type;
63 AHB_Master_Out : OUT AHB_Mst_Out_Type;
64
64
65 -- fifo interface
65 -- fifo interface
66 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
67 fifo_empty : IN STD_LOGIC;
67 fifo_empty : IN STD_LOGIC;
68 fifo_ren : OUT STD_LOGIC;
68 fifo_ren : OUT STD_LOGIC;
69
69
70 -- header
70 -- header
71 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 header_val : IN STD_LOGIC;
72 header_val : IN STD_LOGIC;
73 header_ack : OUT STD_LOGIC
73 header_ack : OUT STD_LOGIC
74 );
74 );
75 END;
75 END;
76
76
77 ARCHITECTURE Behavioral OF lpp_dma IS
77 ARCHITECTURE Behavioral OF lpp_dma IS
78
78
79 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
79 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
80 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
80 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
81 SIGNAL ready_matrix_f1 : STD_LOGIC;
81 SIGNAL ready_matrix_f1 : STD_LOGIC;
82 SIGNAL ready_matrix_f2 : STD_LOGIC;
82 SIGNAL ready_matrix_f2 : STD_LOGIC;
83 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
83 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
84 SIGNAL error_bad_component_error : STD_LOGIC;
84 SIGNAL error_bad_component_error : STD_LOGIC;
85
85
86 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
87
87
88 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
88 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
89 SIGNAL config_active_interruption_onError : STD_LOGIC;
89 SIGNAL config_active_interruption_onError : STD_LOGIC;
90 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
90 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
91 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
91 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
92 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
92 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
93 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
93 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
94 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
94 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
95 SIGNAL status_error_bad_component_error : STD_LOGIC;
95 SIGNAL status_error_bad_component_error : STD_LOGIC;
96 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
96 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100
100
101 BEGIN
101 BEGIN
102
102
103 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
104 -- LPP DMA IP
104 -- LPP DMA IP
105 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
106
106
107 lpp_dma_ip_1: ENTITY work.lpp_dma_ip
107 lpp_dma_ip_1: lpp_dma_ip
108 GENERIC MAP (
108 GENERIC MAP (
109 tech => tech,
109 tech => tech,
110 hindex => hindex,
110 hindex => hindex)
111 pindex => pindex,
112 paddr => paddr,
113 pmask => pmask,
114 pirq => pirq)
115 PORT MAP (
111 PORT MAP (
116 HCLK => HCLK,
112 HCLK => HCLK,
117 HRESETn => HRESETn,
113 HRESETn => HRESETn,
118 AHB_Master_In => AHB_Master_In,
114 AHB_Master_In => AHB_Master_In,
119 AHB_Master_Out => AHB_Master_Out,
115 AHB_Master_Out => AHB_Master_Out,
120 fifo_data => fifo_data,
116 fifo_data => fifo_data,
121 fifo_empty => fifo_empty,
117 fifo_empty => fifo_empty,
122 fifo_ren => fifo_ren,
118 fifo_ren => fifo_ren,
123 header => header,
119 header => header,
124 header_val => header_val,
120 header_val => header_val,
125 header_ack => header_ack,
121 header_ack => header_ack,
126 -------------------------------------------------------------------------
122 -------------------------------------------------------------------------
127 -- REG
123 -- REG
128 ready_matrix_f0_0 => ready_matrix_f0_0,
124 ready_matrix_f0_0 => ready_matrix_f0_0,
129 ready_matrix_f0_1 => ready_matrix_f0_1,
125 ready_matrix_f0_1 => ready_matrix_f0_1,
130 ready_matrix_f1 => ready_matrix_f1,
126 ready_matrix_f1 => ready_matrix_f1,
131 ready_matrix_f2 => ready_matrix_f2,
127 ready_matrix_f2 => ready_matrix_f2,
132 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
128 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
133 error_bad_component_error => error_bad_component_error,
129 error_bad_component_error => error_bad_component_error,
134
130
135 debug_reg => debug_reg,
131 debug_reg => debug_reg,
136
132
137 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
133 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
138 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
134 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
139 status_ready_matrix_f1 => status_ready_matrix_f1,
135 status_ready_matrix_f1 => status_ready_matrix_f1,
140 status_ready_matrix_f2 => status_ready_matrix_f2,
136 status_ready_matrix_f2 => status_ready_matrix_f2,
141 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
137 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
142 status_error_bad_component_error => status_error_bad_component_error,
138 status_error_bad_component_error => status_error_bad_component_error,
143 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
139 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
144 config_active_interruption_onError => config_active_interruption_onError,
140 config_active_interruption_onError => config_active_interruption_onError,
145 addr_matrix_f0_0 => addr_matrix_f0_0,
141 addr_matrix_f0_0 => addr_matrix_f0_0,
146 addr_matrix_f0_1 => addr_matrix_f0_1,
142 addr_matrix_f0_1 => addr_matrix_f0_1,
147 addr_matrix_f1 => addr_matrix_f1,
143 addr_matrix_f1 => addr_matrix_f1,
148 addr_matrix_f2 => addr_matrix_f2);
144 addr_matrix_f2 => addr_matrix_f2);
149
145
150 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
151 -- APB REGISTER
147 -- APB REGISTER
152 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
153
149
154 lpp_dma_apbreg_1 : lpp_dma_apbreg
150 lpp_dma_apbreg_1 : lpp_dma_apbreg
155 GENERIC MAP (
151 GENERIC MAP (
156 pindex => pindex,
152 pindex => pindex,
157 paddr => paddr,
153 paddr => paddr,
158 pmask => pmask,
154 pmask => pmask,
159 pirq => pirq)
155 pirq => pirq)
160 PORT MAP (
156 PORT MAP (
161 HCLK => HCLK,
157 HCLK => HCLK,
162 HRESETn => HRESETn,
158 HRESETn => HRESETn,
163 apbi => apbi,
159 apbi => apbi,
164 apbo => apbo,
160 apbo => apbo,
165 -- IN
161 -- IN
166 ready_matrix_f0_0 => ready_matrix_f0_0,
162 ready_matrix_f0_0 => ready_matrix_f0_0,
167 ready_matrix_f0_1 => ready_matrix_f0_1,
163 ready_matrix_f0_1 => ready_matrix_f0_1,
168 ready_matrix_f1 => ready_matrix_f1,
164 ready_matrix_f1 => ready_matrix_f1,
169 ready_matrix_f2 => ready_matrix_f2,
165 ready_matrix_f2 => ready_matrix_f2,
170 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
166 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
171 error_bad_component_error => error_bad_component_error,
167 error_bad_component_error => error_bad_component_error,
172 --
168 --
173 debug_reg => debug_reg,
169 debug_reg => debug_reg,
174 -- OUT
170 -- OUT
175 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
171 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
176 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
172 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
177 status_ready_matrix_f1 => status_ready_matrix_f1,
173 status_ready_matrix_f1 => status_ready_matrix_f1,
178 status_ready_matrix_f2 => status_ready_matrix_f2,
174 status_ready_matrix_f2 => status_ready_matrix_f2,
179 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
175 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
180 status_error_bad_component_error => status_error_bad_component_error,
176 status_error_bad_component_error => status_error_bad_component_error,
181 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, -- TODO
177 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, -- TODO
182 config_active_interruption_onError => config_active_interruption_onError, -- TODO
178 config_active_interruption_onError => config_active_interruption_onError, -- TODO
183 addr_matrix_f0_0 => addr_matrix_f0_0,
179 addr_matrix_f0_0 => addr_matrix_f0_0,
184 addr_matrix_f0_1 => addr_matrix_f0_1,
180 addr_matrix_f0_1 => addr_matrix_f0_1,
185 addr_matrix_f1 => addr_matrix_f1,
181 addr_matrix_f1 => addr_matrix_f1,
186 addr_matrix_f2 => addr_matrix_f2);
182 addr_matrix_f2 => addr_matrix_f2);
187
183
188 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
189
185
190 END Behavioral;
186 END Behavioral;
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@@ -1,355 +1,352
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_amba.ALL;
37 USE lpp.lpp_amba.ALL;
38 USE lpp.apb_devices_list.ALL;
38 USE lpp.apb_devices_list.ALL;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_dma_pkg.ALL;
41 LIBRARY techmap;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
43
43
44
44
45 ENTITY lpp_dma_ip IS
45 ENTITY lpp_dma_ip IS
46 GENERIC (
46 GENERIC (
47 tech : INTEGER := inferred;
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2;
48 hindex : INTEGER := 2
49 pindex : INTEGER := 4;
49 );
50 paddr : INTEGER := 4;
51 pmask : INTEGER := 16#fff#;
52 pirq : INTEGER := 0);
53 PORT (
50 PORT (
54 -- AMBA AHB system signals
51 -- AMBA AHB system signals
55 HCLK : IN STD_ULOGIC;
52 HCLK : IN STD_ULOGIC;
56 HRESETn : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
57
54
58 -- AMBA AHB Master Interface
55 -- AMBA AHB Master Interface
59 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_In : IN AHB_Mst_In_Type;
60 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
61
58
62 -- fifo interface
59 -- fifo interface
63 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 fifo_empty : IN STD_LOGIC;
61 fifo_empty : IN STD_LOGIC;
65 fifo_ren : OUT STD_LOGIC;
62 fifo_ren : OUT STD_LOGIC;
66
63
67 -- header
64 -- header
68 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 header_val : IN STD_LOGIC;
66 header_val : IN STD_LOGIC;
70 header_ack : OUT STD_LOGIC;
67 header_ack : OUT STD_LOGIC;
71
68
72 -- Reg out
69 -- Reg out
73 ready_matrix_f0_0 : OUT STD_LOGIC;
70 ready_matrix_f0_0 : OUT STD_LOGIC;
74 ready_matrix_f0_1 : OUT STD_LOGIC;
71 ready_matrix_f0_1 : OUT STD_LOGIC;
75 ready_matrix_f1 : OUT STD_LOGIC;
72 ready_matrix_f1 : OUT STD_LOGIC;
76 ready_matrix_f2 : OUT STD_LOGIC;
73 ready_matrix_f2 : OUT STD_LOGIC;
77 error_anticipating_empty_fifo : OUT STD_LOGIC;
74 error_anticipating_empty_fifo : OUT STD_LOGIC;
78 error_bad_component_error : OUT STD_LOGIC;
75 error_bad_component_error : OUT STD_LOGIC;
79 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80
77
81 -- Reg In
78 -- Reg In
82 status_ready_matrix_f0_0 :IN STD_LOGIC;
79 status_ready_matrix_f0_0 :IN STD_LOGIC;
83 status_ready_matrix_f0_1 :IN STD_LOGIC;
80 status_ready_matrix_f0_1 :IN STD_LOGIC;
84 status_ready_matrix_f1 :IN STD_LOGIC;
81 status_ready_matrix_f1 :IN STD_LOGIC;
85 status_ready_matrix_f2 :IN STD_LOGIC;
82 status_ready_matrix_f2 :IN STD_LOGIC;
86 status_error_anticipating_empty_fifo :IN STD_LOGIC;
83 status_error_anticipating_empty_fifo :IN STD_LOGIC;
87 status_error_bad_component_error :IN STD_LOGIC;
84 status_error_bad_component_error :IN STD_LOGIC;
88
85
89 config_active_interruption_onNewMatrix : IN STD_LOGIC;
86 config_active_interruption_onNewMatrix : IN STD_LOGIC;
90 config_active_interruption_onError : IN STD_LOGIC;
87 config_active_interruption_onError : IN STD_LOGIC;
91 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
91 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
95 );
92 );
96 END;
93 END;
97
94
98 ARCHITECTURE Behavioral OF lpp_dma_ip IS
95 ARCHITECTURE Behavioral OF lpp_dma_ip IS
99 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
100 SIGNAL DMAIn : DMA_In_Type;
97 SIGNAL DMAIn : DMA_In_Type;
101 SIGNAL header_dmai : DMA_In_Type;
98 SIGNAL header_dmai : DMA_In_Type;
102 SIGNAL component_dmai : DMA_In_Type;
99 SIGNAL component_dmai : DMA_In_Type;
103 SIGNAL DMAOut : DMA_OUt_Type;
100 SIGNAL DMAOut : DMA_OUt_Type;
104 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
105
102
106 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
107 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
108 TYPE state_DMAWriteBurst IS (IDLE,
105 TYPE state_DMAWriteBurst IS (IDLE,
109 TRASH_FIFO,
106 TRASH_FIFO,
110 WAIT_HEADER_ACK,
107 WAIT_HEADER_ACK,
111 SEND_DATA,
108 SEND_DATA,
112 WAIT_DATA_ACK,
109 WAIT_DATA_ACK,
113 CHECK_LENGTH
110 CHECK_LENGTH
114 );
111 );
115 SIGNAL state : state_DMAWriteBurst := IDLE;
112 SIGNAL state : state_DMAWriteBurst := IDLE;
116
113
117 SIGNAL nbSend : INTEGER;
114 SIGNAL nbSend : INTEGER;
118 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
119 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
120 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
121 SIGNAL header_check_ok : STD_LOGIC;
118 SIGNAL header_check_ok : STD_LOGIC;
122 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
123 SIGNAL send_matrix : STD_LOGIC;
120 SIGNAL send_matrix : STD_LOGIC;
124 SIGNAL request : STD_LOGIC;
121 SIGNAL request : STD_LOGIC;
125 SIGNAL remaining_data_request : INTEGER;
122 SIGNAL remaining_data_request : INTEGER;
126 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
123 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
128 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
129 SIGNAL header_select : STD_LOGIC;
126 SIGNAL header_select : STD_LOGIC;
130
127
131 SIGNAL header_send : STD_LOGIC;
128 SIGNAL header_send : STD_LOGIC;
132 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL header_send_ok : STD_LOGIC;
130 SIGNAL header_send_ok : STD_LOGIC;
134 SIGNAL header_send_ko : STD_LOGIC;
131 SIGNAL header_send_ko : STD_LOGIC;
135
132
136 SIGNAL component_send : STD_LOGIC;
133 SIGNAL component_send : STD_LOGIC;
137 SIGNAL component_send_ok : STD_LOGIC;
134 SIGNAL component_send_ok : STD_LOGIC;
138 SIGNAL component_send_ko : STD_LOGIC;
135 SIGNAL component_send_ko : STD_LOGIC;
139 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
140 SIGNAL fifo_ren_trash : STD_LOGIC;
137 SIGNAL fifo_ren_trash : STD_LOGIC;
141 SIGNAL component_fifo_ren : STD_LOGIC;
138 SIGNAL component_fifo_ren : STD_LOGIC;
142
139
143 -----------------------------------------------------------------------------
140 -----------------------------------------------------------------------------
144 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
145
142
146 BEGIN
143 BEGIN
147
144
148 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
149 -- DMA to AHB interface
146 -- DMA to AHB interface
150 -----------------------------------------------------------------------------
147 -----------------------------------------------------------------------------
151
148
152 DMA2AHB_1 : DMA2AHB
149 DMA2AHB_1 : DMA2AHB
153 GENERIC MAP (
150 GENERIC MAP (
154 hindex => hindex,
151 hindex => hindex,
155 vendorid => VENDOR_LPP,
152 vendorid => VENDOR_LPP,
156 deviceid => 0,
153 deviceid => 0,
157 version => 0,
154 version => 0,
158 syncrst => 1,
155 syncrst => 1,
159 boundary => 1) -- FIX 11/01/2013
156 boundary => 1) -- FIX 11/01/2013
160 PORT MAP (
157 PORT MAP (
161 HCLK => HCLK,
158 HCLK => HCLK,
162 HRESETn => HRESETn,
159 HRESETn => HRESETn,
163 DMAIn => DMAIn,
160 DMAIn => DMAIn,
164 DMAOut => DMAOut,
161 DMAOut => DMAOut,
165 AHBIn => AHB_Master_In,
162 AHBIn => AHB_Master_In,
166 AHBOut => AHB_Master_Out);
163 AHBOut => AHB_Master_Out);
167
164
168 debug_reg <= debug_reg_s;
165 debug_reg <= debug_reg_s;
169
166
170 debug_info: PROCESS (HCLK, HRESETn)
167 debug_info: PROCESS (HCLK, HRESETn)
171 BEGIN -- PROCESS debug_info
168 BEGIN -- PROCESS debug_info
172 IF HRESETn = '0' THEN -- asynchronous reset (active low)
169 IF HRESETn = '0' THEN -- asynchronous reset (active low)
173 debug_reg <= (OTHERS => '0');
170 debug_reg <= (OTHERS => '0');
174 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
171 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
175 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
172 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
176 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
173 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
177 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
174 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
178 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
175 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
179 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
176 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
180 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
177 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
181 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
178 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
182
179
183 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
180 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
184 END IF;
181 END IF;
185 END PROCESS debug_info;
182 END PROCESS debug_info;
186
183
187
184
188 matrix_type <= header(1 DOWNTO 0);
185 matrix_type <= header(1 DOWNTO 0);
189 component_type <= header(5 DOWNTO 2);
186 component_type <= header(5 DOWNTO 2);
190
187
191 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
188 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
192 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
189 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
193 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
190 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
194 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
191 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
195 '0';
192 '0';
196
193
197 header_check_ok <= '0' WHEN component_type = "1111" ELSE
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE
198 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
195 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
199 '1' WHEN component_type = component_type_pre + "0001" ELSE
196 '1' WHEN component_type = component_type_pre + "0001" ELSE
200 '0';
197 '0';
201
198
202 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
199 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
203 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
200 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
204 addr_matrix_f1 WHEN matrix_type = "10" ELSE
201 addr_matrix_f1 WHEN matrix_type = "10" ELSE
205 addr_matrix_f2 WHEN matrix_type = "11" ELSE
202 addr_matrix_f2 WHEN matrix_type = "11" ELSE
206 (OTHERS => '0');
203 (OTHERS => '0');
207
204
208 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
209 -- DMA control
206 -- DMA control
210 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
211 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
208 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
212 BEGIN -- PROCESS DMAWriteBurst_p
209 BEGIN -- PROCESS DMAWriteBurst_p
213 IF HRESETn = '0' THEN -- asynchronous reset (active low)
210 IF HRESETn = '0' THEN -- asynchronous reset (active low)
214 state <= IDLE;
211 state <= IDLE;
215 header_ack <= '0';
212 header_ack <= '0';
216 ready_matrix_f0_0 <= '0';
213 ready_matrix_f0_0 <= '0';
217 ready_matrix_f0_1 <= '0';
214 ready_matrix_f0_1 <= '0';
218 ready_matrix_f1 <= '0';
215 ready_matrix_f1 <= '0';
219 ready_matrix_f2 <= '0';
216 ready_matrix_f2 <= '0';
220 error_anticipating_empty_fifo <= '0';
217 error_anticipating_empty_fifo <= '0';
221 error_bad_component_error <= '0';
218 error_bad_component_error <= '0';
222 component_type_pre <= "1110";
219 component_type_pre <= "1110";
223 fifo_ren_trash <= '1';
220 fifo_ren_trash <= '1';
224 component_send <= '0';
221 component_send <= '0';
225 address <= (OTHERS => '0');
222 address <= (OTHERS => '0');
226 header_select <= '0';
223 header_select <= '0';
227 header_send <= '0';
224 header_send <= '0';
228 header_data <= (OTHERS => '0');
225 header_data <= (OTHERS => '0');
229 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
226 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
230
227
231 CASE state IS
228 CASE state IS
232 WHEN IDLE =>
229 WHEN IDLE =>
233 ready_matrix_f0_0 <= '0';
230 ready_matrix_f0_0 <= '0';
234 ready_matrix_f0_1 <= '0';
231 ready_matrix_f0_1 <= '0';
235 ready_matrix_f1 <= '0';
232 ready_matrix_f1 <= '0';
236 ready_matrix_f2 <= '0';
233 ready_matrix_f2 <= '0';
237 error_bad_component_error <= '0';
234 error_bad_component_error <= '0';
238 header_select <= '1';
235 header_select <= '1';
239 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
236 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
240 IF header_check_ok = '1' THEN
237 IF header_check_ok = '1' THEN
241 header_data <= header;
238 header_data <= header;
242 component_type_pre <= header(5 DOWNTO 2);
239 component_type_pre <= header(5 DOWNTO 2);
243 header_ack <= '1';
240 header_ack <= '1';
244 --
241 --
245 header_send <= '1';
242 header_send <= '1';
246 IF component_type = "0000" THEN
243 IF component_type = "0000" THEN
247 address <= address_matrix;
244 address <= address_matrix;
248 END IF;
245 END IF;
249 header_data <= header;
246 header_data <= header;
250 --
247 --
251 state <= WAIT_HEADER_ACK;
248 state <= WAIT_HEADER_ACK;
252 ELSE
249 ELSE
253 error_bad_component_error <= '1';
250 error_bad_component_error <= '1';
254 component_type_pre <= "1110";
251 component_type_pre <= "1110";
255 header_ack <= '1';
252 header_ack <= '1';
256 state <= TRASH_FIFO;
253 state <= TRASH_FIFO;
257 END IF;
254 END IF;
258 END IF;
255 END IF;
259
256
260 WHEN TRASH_FIFO =>
257 WHEN TRASH_FIFO =>
261 error_bad_component_error <= '0';
258 error_bad_component_error <= '0';
262 error_anticipating_empty_fifo <= '0';
259 error_anticipating_empty_fifo <= '0';
263 IF fifo_empty = '1' THEN
260 IF fifo_empty = '1' THEN
264 state <= IDLE;
261 state <= IDLE;
265 fifo_ren_trash <= '1';
262 fifo_ren_trash <= '1';
266 ELSE
263 ELSE
267 fifo_ren_trash <= '0';
264 fifo_ren_trash <= '0';
268 END IF;
265 END IF;
269
266
270 WHEN WAIT_HEADER_ACK =>
267 WHEN WAIT_HEADER_ACK =>
271 header_send <= '0';
268 header_send <= '0';
272 IF header_send_ko = '1' THEN
269 IF header_send_ko = '1' THEN
273 state <= TRASH_FIFO;
270 state <= TRASH_FIFO;
274 error_anticipating_empty_fifo <= '1';
271 error_anticipating_empty_fifo <= '1';
275 -- TODO : error sending header
272 -- TODO : error sending header
276 ELSIF header_send_ok = '1' THEN
273 ELSIF header_send_ok = '1' THEN
277 header_select <= '0';
274 header_select <= '0';
278 state <= SEND_DATA;
275 state <= SEND_DATA;
279 address <= address + 4;
276 address <= address + 4;
280 END IF;
277 END IF;
281
278
282 WHEN SEND_DATA =>
279 WHEN SEND_DATA =>
283 IF fifo_empty = '1' THEN
280 IF fifo_empty = '1' THEN
284 state <= IDLE;
281 state <= IDLE;
285 IF component_type = "1110" THEN
282 IF component_type = "1110" THEN
286 CASE matrix_type IS
283 CASE matrix_type IS
287 WHEN "00" => ready_matrix_f0_0 <= '1';
284 WHEN "00" => ready_matrix_f0_0 <= '1';
288 WHEN "01" => ready_matrix_f0_1 <= '1';
285 WHEN "01" => ready_matrix_f0_1 <= '1';
289 WHEN "10" => ready_matrix_f1 <= '1';
286 WHEN "10" => ready_matrix_f1 <= '1';
290 WHEN "11" => ready_matrix_f2 <= '1';
287 WHEN "11" => ready_matrix_f2 <= '1';
291 WHEN OTHERS => NULL;
288 WHEN OTHERS => NULL;
292 END CASE;
289 END CASE;
293 END IF;
290 END IF;
294 ELSE
291 ELSE
295 component_send <= '1';
292 component_send <= '1';
296 address <= address;
293 address <= address;
297 state <= WAIT_DATA_ACK;
294 state <= WAIT_DATA_ACK;
298 END IF;
295 END IF;
299
296
300 WHEN WAIT_DATA_ACK =>
297 WHEN WAIT_DATA_ACK =>
301 component_send <= '0';
298 component_send <= '0';
302 IF component_send_ok = '1' THEN
299 IF component_send_ok = '1' THEN
303 address <= address + 64;
300 address <= address + 64;
304 state <= SEND_DATA;
301 state <= SEND_DATA;
305 ELSIF component_send_ko = '1' THEN
302 ELSIF component_send_ko = '1' THEN
306 error_anticipating_empty_fifo <= '0';
303 error_anticipating_empty_fifo <= '0';
307 state <= TRASH_FIFO;
304 state <= TRASH_FIFO;
308 END IF;
305 END IF;
309
306
310 WHEN CHECK_LENGTH =>
307 WHEN CHECK_LENGTH =>
311 state <= IDLE;
308 state <= IDLE;
312 WHEN OTHERS => NULL;
309 WHEN OTHERS => NULL;
313 END CASE;
310 END CASE;
314
311
315 END IF;
312 END IF;
316 END PROCESS DMAWriteFSM_p;
313 END PROCESS DMAWriteFSM_p;
317
314
318 -----------------------------------------------------------------------------
315 -----------------------------------------------------------------------------
319 -- SEND 1 word by DMA
316 -- SEND 1 word by DMA
320 -----------------------------------------------------------------------------
317 -----------------------------------------------------------------------------
321 lpp_dma_send_1word_1 : lpp_dma_send_1word
318 lpp_dma_send_1word_1 : lpp_dma_send_1word
322 PORT MAP (
319 PORT MAP (
323 HCLK => HCLK,
320 HCLK => HCLK,
324 HRESETn => HRESETn,
321 HRESETn => HRESETn,
325 DMAIn => header_dmai,
322 DMAIn => header_dmai,
326 DMAOut => DMAOut,
323 DMAOut => DMAOut,
327
324
328 send => header_send,
325 send => header_send,
329 address => address,
326 address => address,
330 data => header_data,
327 data => header_data,
331 send_ok => header_send_ok,
328 send_ok => header_send_ok,
332 send_ko => header_send_ko
329 send_ko => header_send_ko
333 );
330 );
334
331
335 -----------------------------------------------------------------------------
332 -----------------------------------------------------------------------------
336 -- SEND 16 word by DMA (in burst mode)
333 -- SEND 16 word by DMA (in burst mode)
337 -----------------------------------------------------------------------------
334 -----------------------------------------------------------------------------
338 lpp_dma_send_16word_1 : lpp_dma_send_16word
335 lpp_dma_send_16word_1 : lpp_dma_send_16word
339 PORT MAP (
336 PORT MAP (
340 HCLK => HCLK,
337 HCLK => HCLK,
341 HRESETn => HRESETn,
338 HRESETn => HRESETn,
342 DMAIn => component_dmai,
339 DMAIn => component_dmai,
343 DMAOut => DMAOut,
340 DMAOut => DMAOut,
344
341
345 send => component_send,
342 send => component_send,
346 address => address,
343 address => address,
347 data => fifo_data,
344 data => fifo_data,
348 ren => component_fifo_ren,
345 ren => component_fifo_ren,
349 send_ok => component_send_ok,
346 send_ok => component_send_ok,
350 send_ko => component_send_ko);
347 send_ko => component_send_ko);
351
348
352 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
349 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
353 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
350 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
354
351
355 END Behavioral;
352 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,204 +1,200
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE std.textio.ALL;
27 USE std.textio.ALL;
28 LIBRARY grlib;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
30 USE grlib.stdlib.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34 LIBRARY lpp;
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38
38
39 PACKAGE lpp_dma_pkg IS
39 PACKAGE lpp_dma_pkg IS
40
40
41 COMPONENT lpp_dma
41 COMPONENT lpp_dma
42 GENERIC (
42 GENERIC (
43 tech : INTEGER;
43 tech : INTEGER;
44 hindex : INTEGER;
44 hindex : INTEGER;
45 pindex : INTEGER;
45 pindex : INTEGER;
46 paddr : INTEGER;
46 paddr : INTEGER;
47 pmask : INTEGER;
47 pmask : INTEGER;
48 pirq : INTEGER);
48 pirq : INTEGER);
49 PORT (
49 PORT (
50 HCLK : IN STD_ULOGIC;
50 HCLK : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
52 apbi : IN apb_slv_in_type;
52 apbi : IN apb_slv_in_type;
53 apbo : OUT apb_slv_out_type;
53 apbo : OUT apb_slv_out_type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 -- fifo interface
56 -- fifo interface
57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 fifo_empty : IN STD_LOGIC;
58 fifo_empty : IN STD_LOGIC;
59 fifo_ren : OUT STD_LOGIC;
59 fifo_ren : OUT STD_LOGIC;
60 -- header
60 -- header
61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 header_val : IN STD_LOGIC;
62 header_val : IN STD_LOGIC;
63 header_ack : OUT STD_LOGIC);
63 header_ack : OUT STD_LOGIC);
64 END COMPONENT;
64 END COMPONENT;
65
65
66 COMPONENT fifo_test_dma
66 COMPONENT fifo_test_dma
67 GENERIC (
67 GENERIC (
68 tech : INTEGER;
68 tech : INTEGER;
69 pindex : INTEGER;
69 pindex : INTEGER;
70 paddr : INTEGER;
70 paddr : INTEGER;
71 pmask : INTEGER);
71 pmask : INTEGER);
72 PORT (
72 PORT (
73 HCLK : IN STD_ULOGIC;
73 HCLK : IN STD_ULOGIC;
74 HRESETn : IN STD_ULOGIC;
74 HRESETn : IN STD_ULOGIC;
75 apbi : IN apb_slv_in_type;
75 apbi : IN apb_slv_in_type;
76 apbo : OUT apb_slv_out_type;
76 apbo : OUT apb_slv_out_type;
77 -- fifo interface
77 -- fifo interface
78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fifo_empty : OUT STD_LOGIC;
79 fifo_empty : OUT STD_LOGIC;
80 fifo_ren : IN STD_LOGIC;
80 fifo_ren : IN STD_LOGIC;
81 -- header
81 -- header
82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 header_val : OUT STD_LOGIC;
83 header_val : OUT STD_LOGIC;
84 header_ack : IN STD_LOGIC
84 header_ack : IN STD_LOGIC
85 );
85 );
86 END COMPONENT;
86 END COMPONENT;
87
87
88 COMPONENT lpp_dma_apbreg
88 COMPONENT lpp_dma_apbreg
89 GENERIC (
89 GENERIC (
90 pindex : INTEGER;
90 pindex : INTEGER;
91 paddr : INTEGER;
91 paddr : INTEGER;
92 pmask : INTEGER;
92 pmask : INTEGER;
93 pirq : INTEGER);
93 pirq : INTEGER);
94 PORT (
94 PORT (
95 HCLK : IN STD_ULOGIC;
95 HCLK : IN STD_ULOGIC;
96 HRESETn : IN STD_ULOGIC;
96 HRESETn : IN STD_ULOGIC;
97 apbi : IN apb_slv_in_type;
97 apbi : IN apb_slv_in_type;
98 apbo : OUT apb_slv_out_type;
98 apbo : OUT apb_slv_out_type;
99 -- IN
99 -- IN
100 ready_matrix_f0_0 : IN STD_LOGIC;
100 ready_matrix_f0_0 : IN STD_LOGIC;
101 ready_matrix_f0_1 : IN STD_LOGIC;
101 ready_matrix_f0_1 : IN STD_LOGIC;
102 ready_matrix_f1 : IN STD_LOGIC;
102 ready_matrix_f1 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107
107
108 -- OUT
108 -- OUT
109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
111 status_ready_matrix_f1 : OUT STD_LOGIC;
111 status_ready_matrix_f1 : OUT STD_LOGIC;
112 status_ready_matrix_f2 : OUT STD_LOGIC;
112 status_ready_matrix_f2 : OUT STD_LOGIC;
113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
114 status_error_bad_component_error : OUT STD_LOGIC;
114 status_error_bad_component_error : OUT STD_LOGIC;
115
115
116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
117 config_active_interruption_onError : OUT STD_LOGIC;
117 config_active_interruption_onError : OUT STD_LOGIC;
118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
122 );
122 );
123 END COMPONENT;
123 END COMPONENT;
124
124
125 COMPONENT lpp_dma_send_1word
125 COMPONENT lpp_dma_send_1word
126 PORT (
126 PORT (
127 HCLK : IN STD_ULOGIC;
127 HCLK : IN STD_ULOGIC;
128 HRESETn : IN STD_ULOGIC;
128 HRESETn : IN STD_ULOGIC;
129 DMAIn : OUT DMA_In_Type;
129 DMAIn : OUT DMA_In_Type;
130 DMAOut : IN DMA_OUt_Type;
130 DMAOut : IN DMA_OUt_Type;
131 send : IN STD_LOGIC;
131 send : IN STD_LOGIC;
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 send_ok : OUT STD_LOGIC;
134 send_ok : OUT STD_LOGIC;
135 send_ko : OUT STD_LOGIC);
135 send_ko : OUT STD_LOGIC);
136 END COMPONENT;
136 END COMPONENT;
137
137
138 COMPONENT lpp_dma_send_16word
138 COMPONENT lpp_dma_send_16word
139 PORT (
139 PORT (
140 HCLK : IN STD_ULOGIC;
140 HCLK : IN STD_ULOGIC;
141 HRESETn : IN STD_ULOGIC;
141 HRESETn : IN STD_ULOGIC;
142 DMAIn : OUT DMA_In_Type;
142 DMAIn : OUT DMA_In_Type;
143 DMAOut : IN DMA_OUt_Type;
143 DMAOut : IN DMA_OUt_Type;
144 send : IN STD_LOGIC;
144 send : IN STD_LOGIC;
145 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 ren : OUT STD_LOGIC;
147 ren : OUT STD_LOGIC;
148 send_ok : OUT STD_LOGIC;
148 send_ok : OUT STD_LOGIC;
149 send_ko : OUT STD_LOGIC);
149 send_ko : OUT STD_LOGIC);
150 END COMPONENT;
150 END COMPONENT;
151
151
152 COMPONENT fifo_latency_correction
152 COMPONENT fifo_latency_correction
153 PORT (
153 PORT (
154 HCLK : IN STD_ULOGIC;
154 HCLK : IN STD_ULOGIC;
155 HRESETn : IN STD_ULOGIC;
155 HRESETn : IN STD_ULOGIC;
156 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
156 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 fifo_empty : IN STD_LOGIC;
157 fifo_empty : IN STD_LOGIC;
158 fifo_ren : OUT STD_LOGIC;
158 fifo_ren : OUT STD_LOGIC;
159 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
159 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 dma_empty : OUT STD_LOGIC;
160 dma_empty : OUT STD_LOGIC;
161 dma_ren : IN STD_LOGIC);
161 dma_ren : IN STD_LOGIC);
162 END COMPONENT;
162 END COMPONENT;
163
163
164 COMPONENT lpp_dma_ip
164 COMPONENT lpp_dma_ip
165 GENERIC (
165 GENERIC (
166 tech : INTEGER;
166 tech : INTEGER;
167 hindex : INTEGER;
167 hindex : INTEGER);
168 pindex : INTEGER;
169 paddr : INTEGER;
170 pmask : INTEGER;
171 pirq : INTEGER);
172 PORT (
168 PORT (
173 HCLK : IN STD_ULOGIC;
169 HCLK : IN STD_ULOGIC;
174 HRESETn : IN STD_ULOGIC;
170 HRESETn : IN STD_ULOGIC;
175 AHB_Master_In : IN AHB_Mst_In_Type;
171 AHB_Master_In : IN AHB_Mst_In_Type;
176 AHB_Master_Out : OUT AHB_Mst_Out_Type;
172 AHB_Master_Out : OUT AHB_Mst_Out_Type;
177 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
173 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
178 fifo_empty : IN STD_LOGIC;
174 fifo_empty : IN STD_LOGIC;
179 fifo_ren : OUT STD_LOGIC;
175 fifo_ren : OUT STD_LOGIC;
180 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
176 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
181 header_val : IN STD_LOGIC;
177 header_val : IN STD_LOGIC;
182 header_ack : OUT STD_LOGIC;
178 header_ack : OUT STD_LOGIC;
183 ready_matrix_f0_0 : OUT STD_LOGIC;
179 ready_matrix_f0_0 : OUT STD_LOGIC;
184 ready_matrix_f0_1 : OUT STD_LOGIC;
180 ready_matrix_f0_1 : OUT STD_LOGIC;
185 ready_matrix_f1 : OUT STD_LOGIC;
181 ready_matrix_f1 : OUT STD_LOGIC;
186 ready_matrix_f2 : OUT STD_LOGIC;
182 ready_matrix_f2 : OUT STD_LOGIC;
187 error_anticipating_empty_fifo : OUT STD_LOGIC;
183 error_anticipating_empty_fifo : OUT STD_LOGIC;
188 error_bad_component_error : OUT STD_LOGIC;
184 error_bad_component_error : OUT STD_LOGIC;
189 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
190 status_ready_matrix_f0_0 : IN STD_LOGIC;
186 status_ready_matrix_f0_0 : IN STD_LOGIC;
191 status_ready_matrix_f0_1 : IN STD_LOGIC;
187 status_ready_matrix_f0_1 : IN STD_LOGIC;
192 status_ready_matrix_f1 : IN STD_LOGIC;
188 status_ready_matrix_f1 : IN STD_LOGIC;
193 status_ready_matrix_f2 : IN STD_LOGIC;
189 status_ready_matrix_f2 : IN STD_LOGIC;
194 status_error_anticipating_empty_fifo : IN STD_LOGIC;
190 status_error_anticipating_empty_fifo : IN STD_LOGIC;
195 status_error_bad_component_error : IN STD_LOGIC;
191 status_error_bad_component_error : IN STD_LOGIC;
196 config_active_interruption_onNewMatrix : IN STD_LOGIC;
192 config_active_interruption_onNewMatrix : IN STD_LOGIC;
197 config_active_interruption_onError : IN STD_LOGIC;
193 config_active_interruption_onError : IN STD_LOGIC;
198 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
194 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
199 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
195 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
200 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
201 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
197 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
202 END COMPONENT;
198 END COMPONENT;
203
199
204 END;
200 END;
Show file before | Show file after | Hide comments
@@ -1,354 +1,332
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
5 USE lpp.iir_filter.ALL;
6 USE lpp.FILTERcfg.ALL;
6 USE lpp.FILTERcfg.ALL;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
9 LIBRARY techmap;
9 LIBRARY techmap;
10 USE techmap.gencomp.ALL;
10 USE techmap.gencomp.ALL;
11
11
12 ENTITY lpp_top_acq IS
12 ENTITY lpp_top_acq IS
13 GENERIC(
13 GENERIC(
14 tech : INTEGER := 0
14 tech : INTEGER := 0
15 );
15 );
16 PORT (
16 PORT (
17 -- ADS7886
17 -- ADS7886
18 cnv_run : IN STD_LOGIC;
18 cnv_run : IN STD_LOGIC;
19 cnv : OUT STD_LOGIC;
19 cnv : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 --
22 --
23 cnv_clk : IN STD_LOGIC;
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
24 cnv_rstn : IN STD_LOGIC;
24 cnv_rstn : IN STD_LOGIC;
25 --
25 --
26 clk : IN STD_LOGIC;
26 clk : IN STD_LOGIC; -- 25 MHz
27 rstn : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 --
28 --
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
32 --
32 --
33 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
34 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
35 --
35 --
36 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
37 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
38 --
38 --
39 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
40 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0)
40 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0)
41 );
41 );
42 END lpp_top_acq;
42 END lpp_top_acq;
43
43
44 ARCHITECTURE tb OF lpp_top_acq IS
44 ARCHITECTURE tb OF lpp_top_acq IS
45
45
46 COMPONENT Downsampling
46 COMPONENT Downsampling
47 GENERIC (
47 GENERIC (
48 ChanelCount : INTEGER;
48 ChanelCount : INTEGER;
49 SampleSize : INTEGER;
49 SampleSize : INTEGER;
50 DivideParam : INTEGER);
50 DivideParam : INTEGER);
51 PORT (
51 PORT (
52 clk : IN STD_LOGIC;
52 clk : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
54 sample_in_val : IN STD_LOGIC;
54 sample_in_val : IN STD_LOGIC;
55 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
55 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
56 sample_out_val : OUT STD_LOGIC;
56 sample_out_val : OUT STD_LOGIC;
57 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
57 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
58 END COMPONENT;
58 END COMPONENT;
59
59
60 -----------------------------------------------------------------------------
60 -----------------------------------------------------------------------------
61 CONSTANT ChanelCount : INTEGER := 8;
61 CONSTANT ChanelCount : INTEGER := 8;
62 CONSTANT ncycle_cnv_high : INTEGER := 79;
62 CONSTANT ncycle_cnv_high : INTEGER := 79;
63 CONSTANT ncycle_cnv : INTEGER := 500;
63 CONSTANT ncycle_cnv : INTEGER := 500;
64
64
65 -----------------------------------------------------------------------------
65 -----------------------------------------------------------------------------
66 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
66 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
67 SIGNAL sample_val : STD_LOGIC;
67 SIGNAL sample_val : STD_LOGIC;
68 SIGNAL sample_val_delay : STD_LOGIC;
68 SIGNAL sample_val_delay : STD_LOGIC;
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70 CONSTANT Coef_SZ : INTEGER := 9;
70 CONSTANT Coef_SZ : INTEGER := 9;
71 CONSTANT CoefCntPerCel : INTEGER := 6;
71 CONSTANT CoefCntPerCel : INTEGER := 6;
72 CONSTANT CoefPerCel : INTEGER := 5;
72 CONSTANT CoefPerCel : INTEGER := 5;
73 CONSTANT Cels_count : INTEGER := 5;
73 CONSTANT Cels_count : INTEGER := 5;
74
74
75 -- SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
75 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
76 SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
77 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
76 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 -- SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --
77 --
80 SIGNAL sample_filter_JC_out_val : STD_LOGIC;
78 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
81 SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 --
80 --
83 SIGNAL sample_filter_JC_out_r_val : STD_LOGIC;
81 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
84 SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 -----------------------------------------------------------------------------
83 -----------------------------------------------------------------------------
86 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
84 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
87 SIGNAL sample_downsampling_out_val : STD_LOGIC;
85 SIGNAL sample_downsampling_out_val : STD_LOGIC;
88 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
86 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 --
87 --
90 SIGNAL sample_f0_val : STD_LOGIC;
88 SIGNAL sample_f0_val : STD_LOGIC;
91 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
92 --
90 --
93 SIGNAL sample_f0_0_val : STD_LOGIC;
91 SIGNAL sample_f0_0_val : STD_LOGIC;
94 SIGNAL sample_f0_1_val : STD_LOGIC;
92 SIGNAL sample_f0_1_val : STD_LOGIC;
95 SIGNAL counter_f0 : INTEGER;
93 SIGNAL counter_f0 : INTEGER;
96 -----------------------------------------------------------------------------
94 -----------------------------------------------------------------------------
97 SIGNAL sample_f1_val : STD_LOGIC;
95 SIGNAL sample_f1_val : STD_LOGIC;
98 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
96 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
99 --
97 --
100 SIGNAL sample_f2_val : STD_LOGIC;
98 SIGNAL sample_f2_val : STD_LOGIC;
101 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
99 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
102 --
100 --
103 SIGNAL sample_f3_val : STD_LOGIC;
101 SIGNAL sample_f3_val : STD_LOGIC;
104 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
102 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
105
103
106 BEGIN
104 BEGIN
107
105
108 -- component instantiation
106 -- component instantiation
109 -----------------------------------------------------------------------------
107 -----------------------------------------------------------------------------
110 DIGITAL_acquisition : ADS7886_drvr
108 DIGITAL_acquisition : ADS7886_drvr
111 GENERIC MAP (
109 GENERIC MAP (
112 ChanelCount => ChanelCount,
110 ChanelCount => ChanelCount,
113 ncycle_cnv_high => ncycle_cnv_high,
111 ncycle_cnv_high => ncycle_cnv_high,
114 ncycle_cnv => ncycle_cnv)
112 ncycle_cnv => ncycle_cnv)
115 PORT MAP (
113 PORT MAP (
116 cnv_clk => cnv_clk, --
114 cnv_clk => cnv_clk, --
117 cnv_rstn => cnv_rstn, --
115 cnv_rstn => cnv_rstn, --
118 cnv_run => cnv_run, --
116 cnv_run => cnv_run, --
119 cnv => cnv, --
117 cnv => cnv, --
120 clk => clk, --
118 clk => clk, --
121 rstn => rstn, --
119 rstn => rstn, --
122 sck => sck, --
120 sck => sck, --
123 sdo => sdo(ChanelCount-1 DOWNTO 0), --
121 sdo => sdo(ChanelCount-1 DOWNTO 0), --
124 sample => sample,
122 sample => sample,
125 sample_val => sample_val);
123 sample_val => sample_val);
126
124
127 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
128
126
129 PROCESS (clk, rstn)
127 PROCESS (clk, rstn)
130 BEGIN -- PROCESS
128 BEGIN -- PROCESS
131 IF rstn = '0' THEN -- asynchronous reset (active low)
129 IF rstn = '0' THEN -- asynchronous reset (active low)
132 sample_val_delay <= '0';
130 sample_val_delay <= '0';
133 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
131 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
134 sample_val_delay <= sample_val;
132 sample_val_delay <= sample_val;
135 END IF;
133 END IF;
136 END PROCESS;
134 END PROCESS;
137
135
138 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
139 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
137 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
140 SampleLoop : FOR j IN 0 TO 15 GENERATE
138 SampleLoop : FOR j IN 0 TO 15 GENERATE
141 sample_filter_in(i, j) <= sample(i)(j);
139 sample_filter_in(i, j) <= sample(i)(j);
142 END GENERATE;
140 END GENERATE;
143
141
144 sample_filter_in(i, 16) <= sample(i)(15);
142 sample_filter_in(i, 16) <= sample(i)(15);
145 sample_filter_in(i, 17) <= sample(i)(15);
143 sample_filter_in(i, 17) <= sample(i)(15);
146 END GENERATE;
144 END GENERATE;
147
145
148 -- coefs <= CoefsInitValCst;
146 coefs_v2 <= CoefsInitValCst_v2;
149 coefs_JC <= CoefsInitValCst_JC;
150
151 --FILTER : IIR_CEL_CTRLR
152 -- GENERIC MAP (
153 -- tech => 0,
154 -- Sample_SZ => 18,
155 -- ChanelsCount => ChanelCount,
156 -- Coef_SZ => Coef_SZ,
157 -- CoefCntPerCel => CoefCntPerCel,
158 -- Cels_count => Cels_count,
159 -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
160 -- PORT MAP (
161 -- reset => rstn,
162 -- clk => clk,
163 -- sample_clk => sample_val_delay,
164 -- sample_in => sample_filter_in,
165 -- sample_out => sample_filter_out,
166 -- virg_pos => 7,
167 -- GOtest => OPEN,
168 -- coefs => coefs);
169
147
170 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
148 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
171 GENERIC MAP (
149 GENERIC MAP (
172 tech => 0,
150 tech => 0,
173 Mem_use => use_CEL,
151 Mem_use => use_CEL,
174 Sample_SZ => 18,
152 Sample_SZ => 18,
175 Coef_SZ => Coef_SZ,
153 Coef_SZ => Coef_SZ,
176 Coef_Nb => 25, -- TODO
154 Coef_Nb => 25, -- TODO
177 Coef_sel_SZ => 5, -- TODO
155 Coef_sel_SZ => 5, -- TODO
178 Cels_count => Cels_count,
156 Cels_count => Cels_count,
179 ChanelsCount => ChanelCount)
157 ChanelsCount => ChanelCount)
180 PORT MAP (
158 PORT MAP (
181 rstn => rstn,
159 rstn => rstn,
182 clk => clk,
160 clk => clk,
183 virg_pos => 7,
161 virg_pos => 7,
184 coefs => coefs_JC,
162 coefs => coefs_v2,
185 sample_in_val => sample_val_delay,
163 sample_in_val => sample_val_delay,
186 sample_in => sample_filter_in,
164 sample_in => sample_filter_in,
187 sample_out_val => sample_filter_JC_out_val,
165 sample_out_val => sample_filter_v2_out_val,
188 sample_out => sample_filter_JC_out);
166 sample_out => sample_filter_v2_out);
189
167
190 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
191 PROCESS (clk, rstn)
169 PROCESS (clk, rstn)
192 BEGIN -- PROCESS
170 BEGIN -- PROCESS
193 IF rstn = '0' THEN -- asynchronous reset (active low)
171 IF rstn = '0' THEN -- asynchronous reset (active low)
194 sample_filter_JC_out_r_val <= '0';
172 sample_filter_v2_out_r_val <= '0';
195 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
173 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
196 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
174 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
197 sample_filter_JC_out_r(I, J) <= '0';
175 sample_filter_v2_out_r(I, J) <= '0';
198 END LOOP rst_all_bits;
176 END LOOP rst_all_bits;
199 END LOOP rst_all_chanel;
177 END LOOP rst_all_chanel;
200 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
178 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
201 sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
179 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
202 IF sample_filter_JC_out_val = '1' THEN
180 IF sample_filter_v2_out_val = '1' THEN
203 sample_filter_JC_out_r <= sample_filter_JC_out;
181 sample_filter_v2_out_r <= sample_filter_v2_out;
204 END IF;
182 END IF;
205 END IF;
183 END IF;
206 END PROCESS;
184 END PROCESS;
207
185
208 -----------------------------------------------------------------------------
186 -----------------------------------------------------------------------------
209 -- F0 -- @24.576 kHz
187 -- F0 -- @24.576 kHz
210 -----------------------------------------------------------------------------
188 -----------------------------------------------------------------------------
211 Downsampling_f0 : Downsampling
189 Downsampling_f0 : Downsampling
212 GENERIC MAP (
190 GENERIC MAP (
213 ChanelCount => ChanelCount,
191 ChanelCount => ChanelCount,
214 SampleSize => 18,
192 SampleSize => 18,
215 DivideParam => 4)
193 DivideParam => 4)
216 PORT MAP (
194 PORT MAP (
217 clk => clk,
195 clk => clk,
218 rstn => rstn,
196 rstn => rstn,
219 sample_in_val => sample_filter_JC_out_val ,
197 sample_in_val => sample_filter_v2_out_val ,
220 sample_in => sample_filter_JC_out,
198 sample_in => sample_filter_v2_out,
221 sample_out_val => sample_f0_val,
199 sample_out_val => sample_f0_val,
222 sample_out => sample_f0);
200 sample_out => sample_f0);
223
201
224 all_bit_sample_f0 : FOR I IN 17 DOWNTO 0 GENERATE
202 all_bit_sample_f0 : FOR I IN 17 DOWNTO 0 GENERATE
225 sample_f0_wdata(I) <= sample_f0(0, I);
203 sample_f0_wdata(I) <= sample_f0(0, I);
226 sample_f0_wdata(18*1+I) <= sample_f0(1, I);
204 sample_f0_wdata(18*1+I) <= sample_f0(1, I);
227 sample_f0_wdata(18*2+I) <= sample_f0(2, I);
205 sample_f0_wdata(18*2+I) <= sample_f0(2, I);
228 sample_f0_wdata(18*3+I) <= sample_f0(6, I);
206 sample_f0_wdata(18*3+I) <= sample_f0(6, I);
229 sample_f0_wdata(18*4+I) <= sample_f0(7, I);
207 sample_f0_wdata(18*4+I) <= sample_f0(7, I);
230 END GENERATE all_bit_sample_f0;
208 END GENERATE all_bit_sample_f0;
231
209
232 PROCESS (clk, rstn)
210 PROCESS (clk, rstn)
233 BEGIN -- PROCESS
211 BEGIN -- PROCESS
234 IF rstn = '0' THEN -- asynchronous reset (active low)
212 IF rstn = '0' THEN -- asynchronous reset (active low)
235 counter_f0 <= 0;
213 counter_f0 <= 0;
236 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
214 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
237 IF sample_f0_val = '1' THEN
215 IF sample_f0_val = '1' THEN
238 IF counter_f0 = 511 THEN
216 IF counter_f0 = 511 THEN
239 counter_f0 <= 0;
217 counter_f0 <= 0;
240 ELSE
218 ELSE
241 counter_f0 <= counter_f0 + 1;
219 counter_f0 <= counter_f0 + 1;
242 END IF;
220 END IF;
243 END IF;
221 END IF;
244 END IF;
222 END IF;
245 END PROCESS;
223 END PROCESS;
246
224
247 sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
225 sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
248 sample_f0_0_wen <= NOT(sample_f0_0_val) &
226 sample_f0_0_wen <= NOT(sample_f0_0_val) &
249 NOT(sample_f0_0_val) &
227 NOT(sample_f0_0_val) &
250 NOT(sample_f0_0_val) &
228 NOT(sample_f0_0_val) &
251 NOT(sample_f0_0_val) &
229 NOT(sample_f0_0_val) &
252 NOT(sample_f0_0_val);
230 NOT(sample_f0_0_val);
253
231
254 sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
232 sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
255 sample_f0_1_wen <= NOT(sample_f0_1_val) &
233 sample_f0_1_wen <= NOT(sample_f0_1_val) &
256 NOT(sample_f0_1_val) &
234 NOT(sample_f0_1_val) &
257 NOT(sample_f0_1_val) &
235 NOT(sample_f0_1_val) &
258 NOT(sample_f0_1_val) &
236 NOT(sample_f0_1_val) &
259 NOT(sample_f0_1_val);
237 NOT(sample_f0_1_val);
260
238
261
239
262 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
263 -- F1 -- @4096 Hz
241 -- F1 -- @4096 Hz
264 -----------------------------------------------------------------------------
242 -----------------------------------------------------------------------------
265 Downsampling_f1 : Downsampling
243 Downsampling_f1 : Downsampling
266 GENERIC MAP (
244 GENERIC MAP (
267 ChanelCount => ChanelCount,
245 ChanelCount => ChanelCount,
268 SampleSize => 18,
246 SampleSize => 18,
269 DivideParam => 6)
247 DivideParam => 6)
270 PORT MAP (
248 PORT MAP (
271 clk => clk,
249 clk => clk,
272 rstn => rstn,
250 rstn => rstn,
273 sample_in_val => sample_f0_val ,
251 sample_in_val => sample_f0_val ,
274 sample_in => sample_f0,
252 sample_in => sample_f0,
275 sample_out_val => sample_f1_val,
253 sample_out_val => sample_f1_val,
276 sample_out => sample_f1);
254 sample_out => sample_f1);
277
255
278 sample_f1_wen <= NOT(sample_f1_val) &
256 sample_f1_wen <= NOT(sample_f1_val) &
279 NOT(sample_f1_val) &
257 NOT(sample_f1_val) &
280 NOT(sample_f1_val) &
258 NOT(sample_f1_val) &
281 NOT(sample_f1_val) &
259 NOT(sample_f1_val) &
282 NOT(sample_f1_val);
260 NOT(sample_f1_val);
283
261
284 all_bit_sample_f1 : FOR I IN 17 DOWNTO 0 GENERATE
262 all_bit_sample_f1 : FOR I IN 17 DOWNTO 0 GENERATE
285 sample_f1_wdata(I) <= sample_f1(0, I);
263 sample_f1_wdata(I) <= sample_f1(0, I);
286 sample_f1_wdata(18*1+I) <= sample_f1(1, I);
264 sample_f1_wdata(18*1+I) <= sample_f1(1, I);
287 sample_f1_wdata(18*2+I) <= sample_f1(2, I);
265 sample_f1_wdata(18*2+I) <= sample_f1(2, I);
288 sample_f1_wdata(18*3+I) <= sample_f1(6, I);
266 sample_f1_wdata(18*3+I) <= sample_f1(6, I);
289 sample_f1_wdata(18*4+I) <= sample_f1(7, I);
267 sample_f1_wdata(18*4+I) <= sample_f1(7, I);
290 END GENERATE all_bit_sample_f1;
268 END GENERATE all_bit_sample_f1;
291
269
292 -----------------------------------------------------------------------------
270 -----------------------------------------------------------------------------
293 -- F2 -- @16 Hz
271 -- F2 -- @16 Hz
294 -----------------------------------------------------------------------------
272 -----------------------------------------------------------------------------
295 Downsampling_f2 : Downsampling
273 Downsampling_f2 : Downsampling
296 GENERIC MAP (
274 GENERIC MAP (
297 ChanelCount => ChanelCount,
275 ChanelCount => ChanelCount,
298 SampleSize => 18,
276 SampleSize => 18,
299 DivideParam => 256)
277 DivideParam => 256)
300 PORT MAP (
278 PORT MAP (
301 clk => clk,
279 clk => clk,
302 rstn => rstn,
280 rstn => rstn,
303 sample_in_val => sample_f1_val ,
281 sample_in_val => sample_f1_val ,
304 sample_in => sample_f1,
282 sample_in => sample_f1,
305 sample_out_val => sample_f2_val,
283 sample_out_val => sample_f2_val,
306 sample_out => sample_f2);
284 sample_out => sample_f2);
307
285
308 sample_f2_wen <= NOT(sample_f2_val) &
286 sample_f2_wen <= NOT(sample_f2_val) &
309 NOT(sample_f2_val) &
287 NOT(sample_f2_val) &
310 NOT(sample_f2_val) &
288 NOT(sample_f2_val) &
311 NOT(sample_f2_val) &
289 NOT(sample_f2_val) &
312 NOT(sample_f2_val);
290 NOT(sample_f2_val);
313
291
314 all_bit_sample_f2 : FOR I IN 17 DOWNTO 0 GENERATE
292 all_bit_sample_f2 : FOR I IN 17 DOWNTO 0 GENERATE
315 sample_f2_wdata(I) <= sample_f2(0, I);
293 sample_f2_wdata(I) <= sample_f2(0, I);
316 sample_f2_wdata(18*1+I) <= sample_f2(1, I);
294 sample_f2_wdata(18*1+I) <= sample_f2(1, I);
317 sample_f2_wdata(18*2+I) <= sample_f2(2, I);
295 sample_f2_wdata(18*2+I) <= sample_f2(2, I);
318 sample_f2_wdata(18*3+I) <= sample_f2(6, I);
296 sample_f2_wdata(18*3+I) <= sample_f2(6, I);
319 sample_f2_wdata(18*4+I) <= sample_f2(7, I);
297 sample_f2_wdata(18*4+I) <= sample_f2(7, I);
320 END GENERATE all_bit_sample_f2;
298 END GENERATE all_bit_sample_f2;
321
299
322 -----------------------------------------------------------------------------
300 -----------------------------------------------------------------------------
323 -- F3 -- @256 Hz
301 -- F3 -- @256 Hz
324 -----------------------------------------------------------------------------
302 -----------------------------------------------------------------------------
325 Downsampling_f3 : Downsampling
303 Downsampling_f3 : Downsampling
326 GENERIC MAP (
304 GENERIC MAP (
327 ChanelCount => ChanelCount,
305 ChanelCount => ChanelCount,
328 SampleSize => 18,
306 SampleSize => 18,
329 DivideParam => 96)
307 DivideParam => 96)
330 PORT MAP (
308 PORT MAP (
331 clk => clk,
309 clk => clk,
332 rstn => rstn,
310 rstn => rstn,
333 sample_in_val => sample_f0_val ,
311 sample_in_val => sample_f0_val ,
334 sample_in => sample_f0,
312 sample_in => sample_f0,
335 sample_out_val => sample_f3_val,
313 sample_out_val => sample_f3_val,
336 sample_out => sample_f3);
314 sample_out => sample_f3);
337
315
338 sample_f3_wen <= (NOT sample_f3_val) &
316 sample_f3_wen <= (NOT sample_f3_val) &
339 (NOT sample_f3_val) &
317 (NOT sample_f3_val) &
340 (NOT sample_f3_val) &
318 (NOT sample_f3_val) &
341 (NOT sample_f3_val) &
319 (NOT sample_f3_val) &
342 (NOT sample_f3_val);
320 (NOT sample_f3_val);
343
321
344 all_bit_sample_f3 : FOR I IN 17 DOWNTO 0 GENERATE
322 all_bit_sample_f3 : FOR I IN 17 DOWNTO 0 GENERATE
345 sample_f3_wdata(I) <= sample_f3(0, I);
323 sample_f3_wdata(I) <= sample_f3(0, I);
346 sample_f3_wdata(18*1+I) <= sample_f3(1, I);
324 sample_f3_wdata(18*1+I) <= sample_f3(1, I);
347 sample_f3_wdata(18*2+I) <= sample_f3(2, I);
325 sample_f3_wdata(18*2+I) <= sample_f3(2, I);
348 sample_f3_wdata(18*3+I) <= sample_f3(6, I);
326 sample_f3_wdata(18*3+I) <= sample_f3(6, I);
349 sample_f3_wdata(18*4+I) <= sample_f3(7, I);
327 sample_f3_wdata(18*4+I) <= sample_f3(7, I);
350 END GENERATE all_bit_sample_f3;
328 END GENERATE all_bit_sample_f3;
351
329
352
330
353
331
354 END tb;
332 END tb;
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@@ -1,36 +1,68
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
5 USE lpp.iir_filter.ALL;
6 USE lpp.FILTERcfg.ALL;
6 USE lpp.FILTERcfg.ALL;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
8 LIBRARY techmap;
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
9 USE techmap.gencomp.ALL;
10
10
11 PACKAGE lpp_top_lfr_pkg IS
11 PACKAGE lpp_top_lfr_pkg IS
12
12
13 COMPONENT lpp_top_acq
13 COMPONENT lpp_top_acq
14 GENERIC (
14 GENERIC (
15 tech : integer);
15 tech : integer);
16 PORT (
16 PORT (
17 cnv_run : IN STD_LOGIC;
17 cnv_run : IN STD_LOGIC;
18 cnv : OUT STD_LOGIC;
18 cnv : OUT STD_LOGIC;
19 sck : OUT STD_LOGIC;
19 sck : OUT STD_LOGIC;
20 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
20 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 cnv_clk : IN STD_LOGIC;
21 cnv_clk : IN STD_LOGIC;
22 cnv_rstn : IN STD_LOGIC;
22 cnv_rstn : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25 sample_f0_0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
25 sample_f0_0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f0_1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f0_1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
27 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
28 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
29 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
30 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
31 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0));
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0));
34 END COMPONENT;
34 END COMPONENT;
35
35
36 COMPONENT lpp_top_apbreg
37 GENERIC (
38 pindex : INTEGER;
39 paddr : INTEGER;
40 pmask : INTEGER;
41 pirq : INTEGER);
42 PORT (
43 HCLK : IN STD_ULOGIC;
44 HRESETn : IN STD_ULOGIC;
45 apbi : IN apb_slv_in_type;
46 apbo : OUT apb_slv_out_type;
47 ready_matrix_f0_0 : IN STD_LOGIC;
48 ready_matrix_f0_1 : IN STD_LOGIC;
49 ready_matrix_f1 : IN STD_LOGIC;
50 ready_matrix_f2 : IN STD_LOGIC;
51 error_anticipating_empty_fifo : IN STD_LOGIC;
52 error_bad_component_error : IN STD_LOGIC;
53 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 status_ready_matrix_f0_0 : OUT STD_LOGIC;
55 status_ready_matrix_f0_1 : OUT STD_LOGIC;
56 status_ready_matrix_f1 : OUT STD_LOGIC;
57 status_ready_matrix_f2 : OUT STD_LOGIC;
58 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
59 status_error_bad_component_error : OUT STD_LOGIC;
60 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
61 config_active_interruption_onError : OUT STD_LOGIC;
62 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
66 END COMPONENT;
67
36 END lpp_top_lfr_pkg;
68 END lpp_top_lfr_pkg;
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@@ -1,2 +1,3
1 lpp_top_lfr_pkg.vhd
1 lpp_top_lfr_pkg.vhd
2 lpp_top_acq.vhd
2 lpp_top_acq.vhd
3 lpp_top_lfr.vhd
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