##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

(MINI-LFR) MINI-LFR_testMS_v2...
pellion -
r404:bd28120c33d2 JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -1,161 +1,169
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_lfr_pkg.ALL;
32 32 --USE lpp.lpp_amba.ALL;
33 33 USE lpp.apb_devices_list.ALL;
34 34 USE lpp.lpp_memory.ALL;
35 35 LIBRARY techmap;
36 36 USE techmap.gencomp.ALL;
37 37
38 38 ENTITY lpp_lfr_apbreg_tb IS
39 39 GENERIC (
40 40 pindex : INTEGER := 4;
41 41 paddr : INTEGER := 4;
42 42 pmask : INTEGER := 16#fff#);
43 43 PORT (
44 44 -- AMBA AHB system signals
45 45 HCLK : IN STD_ULOGIC;
46 46 HRESETn : IN STD_ULOGIC;
47 47
48 48 -- AMBA APB Slave Interface
49 49 apbi : IN apb_slv_in_type;
50 50 apbo : OUT apb_slv_out_type;
51 51
52 52 ---------------------------------------------------------------------------
53 53 MEM_IN_SM_wData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
54 54 MEM_IN_SM_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
55 55 MEM_IN_SM_Full_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
56 56 MEM_IN_SM_Empty_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
57 57 MEM_IN_SM_locked_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
58 58 ---------------------------------------------------------------------------
59 59 MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 60 MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
61 61 MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
62 62 MEM_OUT_SM_Full_2 : IN STD_LOGIC;
63 63 MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
64 64 ---------------------------------------------------------------------------
65 65 );
66 66
67 67 END lpp_lfr_apbreg_tb;
68 68
69 69 ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS
70 70
71 71 CONSTANT REVISION : INTEGER := 1;
72 72
73 73 CONSTANT pconfig : apb_config_type := (
74 74 0 => ahb_device_reg (VENDOR_LPP, 16#19#, 0, REVISION, 1),
75 75 1 => apb_iobar(paddr, pmask));
76 76
77 77 TYPE reg_debug_fft IS RECORD
78 78 MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
79 79 MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 80 --
81 81 out_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
82 82 END RECORD;
83 83 SIGNAL reg_ftt : reg_debug_fft;
84 84
85 85 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86
87 87 BEGIN -- beh
88 88
89 89 ---------------------------------------------------------------------------
90 90 MEM_IN_SM_wen <= reg_ftt.MEM_IN_SM_wen;
91 91 MEM_IN_SM_wData <= reg_ftt.MEM_IN_SM_wData;
92 92 ---------------------------------------------------------------------------
93 93 MEM_OUT_SM_ren <= reg_ftt.out_ren;
94 94 ---------------------------------------------------------------------------
95 95
96 96 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
97 97 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
98 98 BEGIN
99 99 IF HRESETn = '0' THEN
100 100 reg_ftt.MEM_IN_SM_wData <= (OTHERS => '0');
101
101 102 reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1');
102
103 103 reg_ftt.out_ren <= (OTHERS => '1');
104 104
105 105 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
106 106
107 107 reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1');
108 108 reg_ftt.out_ren <= (OTHERS => '1');
109 109
110 110 paddr := "000000";
111 111 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
112 112 prdata <= (OTHERS => '0');
113 113 IF apbi.psel(pindex) = '1' THEN
114 114 -- APB DMA READ --
115 115 CASE paddr(7 DOWNTO 2) IS
116 116 --0
117 117 WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*1-1 DOWNTO 32*0);
118 118 WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*2-1 DOWNTO 32*1);
119 119 WHEN "000010" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*3-1 DOWNTO 32*2);
120 120 WHEN "000011" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*4-1 DOWNTO 32*3);
121 121 WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*5-1 DOWNTO 32*4);
122 122 WHEN "000101" => prdata( 4 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wen;
123 123 prdata( 9 DOWNTO 5) <= MEM_IN_SM_Full_out;
124 124 prdata(14 DOWNTO 10) <= MEM_IN_SM_Empty_out;
125 125 prdata(19 DOWNTO 15) <= MEM_IN_SM_locked_out;
126 126
127 127 WHEN "000110" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*1-1 DOWNTO 32*0);
128 128 WHEN "000111" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*2-1 DOWNTO 32*1);
129 129
130 130 WHEN "001000" => prdata(1 DOWNTO 0) <= reg_ftt.out_ren;
131 131 prdata(3 DOWNTO 2) <= MEM_OUT_SM_Full;
132 132 prdata(5 DOWNTO 4) <= MEM_OUT_SM_Empty;
133 133 prdata(6) <= MEM_OUT_SM_Full_2;
134 134 WHEN OTHERS => NULL;
135 135
136 136 END CASE;
137 137 IF (apbi.pwrite AND apbi.penable) = '1' THEN
138 138 -- APB DMA WRITE --
139 139 CASE paddr(7 DOWNTO 2) IS
140 140 WHEN "000000" => reg_ftt.MEM_IN_SM_wData(32*1-1 DOWNTO 32*0) <= apbi.pwdata(31 DOWNTO 0);
141 141 WHEN "000001" => reg_ftt.MEM_IN_SM_wData(32*2-1 DOWNTO 32*1) <= apbi.pwdata(31 DOWNTO 0);
142 142 WHEN "000010" => reg_ftt.MEM_IN_SM_wData(32*3-1 DOWNTO 32*2) <= apbi.pwdata(31 DOWNTO 0);
143 143 WHEN "000011" => reg_ftt.MEM_IN_SM_wData(32*4-1 DOWNTO 32*3) <= apbi.pwdata(31 DOWNTO 0);
144 144 WHEN "000100" => reg_ftt.MEM_IN_SM_wData(32*5-1 DOWNTO 32*4) <= apbi.pwdata(31 DOWNTO 0);
145 145 WHEN "000101" => reg_ftt.MEM_IN_SM_wen <= apbi.pwdata(4 DOWNTO 0);
146 146
147 147 WHEN "001000" => reg_ftt.out_ren <= apbi.pwdata(1 DOWNTO 0);
148 148
149 149 WHEN OTHERS => NULL;
150 150 END CASE;
151 151 END IF;
152
153 --IF (apbi.psel(pindex) AND apbi.pwrite AND apbi.penable) = '1' AND paddr(7 DOWNTO 2) = "000101" THEN
154 -- reg_ftt.MEM_IN_SM_wen <= apbi.pwdata(4 DOWNTO 0);
155 --ELSE
156 -- reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1');
157 --END IF;
158
159
152 160 END IF;
153 161
154 162 END IF;
155 163 END PROCESS lpp_lfr_apbreg;
156 164
157 165 apbo.pindex <= pindex;
158 166 apbo.pconfig <= pconfig;
159 167 apbo.prdata <= prdata;
160 168
161 169 END beh;
Show file before | Show file after | Hide comments
@@ -1,220 +1,357
1 1 LIBRARY IEEE;
2 2 USE IEEE.numeric_std.ALL;
3 3 USE IEEE.std_logic_1164.ALL;
4 4
5 5 LIBRARY grlib;
6 6 USE grlib.amba.ALL;
7 7 USE grlib.stdlib.ALL;
8 8
9 9 LIBRARY lpp;
10 10 USE lpp.iir_filter.ALL;
11 11
12 12 ENTITY testbench_ms IS
13 13
14 14 END testbench_ms;
15 15
16 16 ARCHITECTURE tb OF testbench_ms IS
17 17 -----------------------------------------------------------------------------
18 18 -- COMPONENT ----------------------------------------------------------------
19 19 -----------------------------------------------------------------------------
20 20 COMPONENT lpp_lfr_apbreg_tb
21 21 GENERIC (
22 22 pindex : INTEGER;
23 23 paddr : INTEGER;
24 24 pmask : INTEGER);
25 25 PORT (
26 26 HCLK : IN STD_ULOGIC;
27 27 HRESETn : IN STD_ULOGIC;
28 28 apbi : IN apb_slv_in_type;
29 29 apbo : OUT apb_slv_out_type;
30 30 MEM_IN_SM_wData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
31 31 MEM_IN_SM_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 32 MEM_IN_SM_Full_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 33 MEM_IN_SM_Empty_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 34 MEM_IN_SM_locked_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 35 MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
36 36 MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
37 37 MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
38 38 MEM_OUT_SM_Full_2 : IN STD_LOGIC;
39 39 MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
40 40 END COMPONENT;
41 41
42 42 COMPONENT lpp_lfr_ms_tb
43 43 GENERIC (
44 44 Mem_use : INTEGER);
45 45 PORT (
46 46 clk : IN STD_LOGIC;
47 47 rstn : IN STD_LOGIC;
48 48 MEM_IN_SM_wData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
49 49 MEM_IN_SM_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
50 50 MEM_IN_SM_Full_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
51 51 MEM_IN_SM_Empty_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
52 52 MEM_IN_SM_locked_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
53 53 MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
54 54 MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
55 55 MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
56 56 MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC;
57 57 MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
58 58 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
59 59 observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
60 60 observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
61 61 END COMPONENT;
62 62
63 63 -----------------------------------------------------------------------------
64 64 -- SIGNAL -------------------------------------------------------------------
65 65 -----------------------------------------------------------------------------
66 66 SIGNAL clk : STD_LOGIC := '0';
67 67 SIGNAL rstn : STD_LOGIC := '0';
68 68 SIGNAL apbi : apb_slv_in_type;
69 69 SIGNAL apbo : apb_slv_out_type;
70 70
71 71 SIGNAL MEM_OUT_SM_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
72 72 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
73 73 SIGNAL MEM_OUT_SM_Full_pad : STD_LOGIC_VECTOR(1 DOWNTO 0);
74 74 SIGNAL MEM_OUT_SM_Full_pad_2 : STD_LOGIC;
75 75 SIGNAL MEM_OUT_SM_Empty_pad : STD_LOGIC_VECTOR(1 DOWNTO 0);
76 76
77 77 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
78 78 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
79 79 SIGNAL MEM_IN_SM_Full_out : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 80 SIGNAL MEM_IN_SM_Empty_out : STD_LOGIC_VECTOR(4 DOWNTO 0);
81 81 SIGNAL MEM_IN_SM_locked_out : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 82
83 83
84 84 -----------------------------------------------------------------------------
85 85 -- FFT
86 86 -----------------------------------------------------------------------------
87 TYPE fft_tab_type IS ARRAY (255 DOWNTO 0) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
87 TYPE fft_tab_type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
88 88 SIGNAL fft_1_re : fft_tab_type;
89 89 SIGNAL fft_1_im : fft_tab_type;
90 90 SIGNAL fft_2_re : fft_tab_type;
91 91 SIGNAL fft_2_im : fft_tab_type;
92 92 SIGNAL fft_3_re : fft_tab_type;
93 93 SIGNAL fft_3_im : fft_tab_type;
94 94 SIGNAL fft_4_re : fft_tab_type;
95 95 SIGNAL fft_4_im : fft_tab_type;
96 96 SIGNAL fft_5_re : fft_tab_type;
97 97 SIGNAL fft_5_im : fft_tab_type;
98 98
99 99 SIGNAL counter_1 : INTEGER;
100 100 SIGNAL counter_2 : INTEGER;
101 101 SIGNAL counter_3 : INTEGER;
102 102 SIGNAL counter_4 : INTEGER;
103 103 SIGNAL counter_5 : INTEGER;
104 104
105 SIGNAL not_full : STD_LOGIC;
106
107 TYPE ms_component_tab_type IS ARRAY (0 TO 1, 127 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
108 TYPE spectral_matrix_type IS ARRAY (0 TO 5, 0 TO 5) OF ms_component_tab_type;
109
110 SIGNAL spectral_matrix_data : spectral_matrix_type;
111
112 CONSTANT DIRAC_FREQ : INTEGER := 0;
113 CONSTANT DIRAC_FREQ2 : INTEGER := 10;
114 CONSTANT DIRAC_FREQ3 : INTEGER := 127;
115 CONSTANT FFT_RE : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0020";
116 CONSTANT FFT_IM : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0010";
105 117
106 118 BEGIN -- tb
107 119
108 120
109 121 clk <= NOT clk AFTER 20 ns;
110 122 rstn <= '1' AFTER 100 ns;
111 123
112 124 PROCESS (clk, rstn)
113 125 BEGIN
114 126 IF rstn = '0' THEN -- asynchronous reset (active low)
115 all_data: FOR i IN 255 DOWNTO 0 LOOP
127 all_data: FOR i IN 127 DOWNTO 0 LOOP
116 128 fft_1_re(I) <= (OTHERS => '0');
117 129 fft_1_im(I) <= (OTHERS => '0');
118 130 fft_2_re(I) <= (OTHERS => '0');
119 131 fft_2_im(I) <= (OTHERS => '0');
120 132 fft_3_re(I) <= (OTHERS => '0');
121 133 fft_3_im(I) <= (OTHERS => '0');
122 134 fft_4_re(I) <= (OTHERS => '0');
123 135 fft_4_im(I) <= (OTHERS => '0');
124 136 fft_5_re(I) <= (OTHERS => '0');
125 137 fft_5_im(I) <= (OTHERS => '0');
126 138 END LOOP all_data;
127 fft_1_re(8*0) <= x"0fff";
128 fft_1_im(8*0) <= x"0010";
129 fft_2_re(8*1) <= x"0010";
130 fft_2_im(8*1+1) <= x"0040";
131 fft_3_re(8*2) <= x"0010";
132 fft_3_im(8*3) <= x"0100";
133 fft_4_re(8*4) <= x"0001";
134 fft_4_im(8*5) <= x"0111";
135 fft_5_re(8*6) <= x"0033";
136 fft_5_im(8*7) <= x"0444";
139
140 fft_1_re(DIRAC_FREQ) <= FFT_RE;
141 fft_1_im(DIRAC_FREQ) <= FFT_IM;
142 fft_1_re(DIRAC_FREQ) <= FFT_RE;
143 fft_1_im(DIRAC_FREQ) <= FFT_IM;
144 fft_2_re(DIRAC_FREQ) <= FFT_RE;
145 fft_2_im(DIRAC_FREQ) <= FFT_IM;
146 fft_3_re(DIRAC_FREQ) <= FFT_RE;
147 fft_3_im(DIRAC_FREQ) <= FFT_IM;
148 fft_4_re(DIRAC_FREQ) <= FFT_RE;
149 fft_4_im(DIRAC_FREQ) <= FFT_IM;
150 fft_5_re(DIRAC_FREQ) <= FFT_RE;
151 fft_5_im(DIRAC_FREQ) <= FFT_IM;
152
153 --fft_1_re(DIRAC_FREQ2) <= FFT_RE;
154 --fft_1_im(DIRAC_FREQ2) <= FFT_IM;
155 --fft_1_re(DIRAC_FREQ2) <= FFT_RE;
156 --fft_1_im(DIRAC_FREQ2) <= FFT_IM;
157 --fft_2_re(DIRAC_FREQ2) <= FFT_RE;
158 --fft_2_im(DIRAC_FREQ2) <= FFT_IM;
159 --fft_3_re(DIRAC_FREQ2) <= FFT_RE;
160 --fft_3_im(DIRAC_FREQ2) <= FFT_IM;
161 --fft_4_re(DIRAC_FREQ2) <= FFT_RE;
162 --fft_4_im(DIRAC_FREQ2) <= FFT_IM;
163 --fft_5_re(DIRAC_FREQ2) <= FFT_RE;
164 --fft_5_im(DIRAC_FREQ2) <= FFT_IM;
165
166 --fft_1_re(DIRAC_FREQ3) <= FFT_RE;
167 --fft_1_im(DIRAC_FREQ3) <= FFT_IM;
168 --fft_1_re(DIRAC_FREQ3) <= FFT_RE;
169 --fft_1_im(DIRAC_FREQ3) <= FFT_IM;
170 --fft_2_re(DIRAC_FREQ3) <= FFT_RE;
171 --fft_2_im(DIRAC_FREQ3) <= FFT_IM;
172 --fft_3_re(DIRAC_FREQ3) <= FFT_RE;
173 --fft_3_im(DIRAC_FREQ3) <= FFT_IM;
174 --fft_4_re(DIRAC_FREQ3) <= FFT_RE;
175 --fft_4_im(DIRAC_FREQ3) <= FFT_IM;
176 --fft_5_re(DIRAC_FREQ3) <= FFT_RE;
177 --fft_5_im(DIRAC_FREQ3) <= FFT_IM;
137 178
138 179 counter_1 <= 0;
139 180 counter_2 <= 0;
140 181 counter_3 <= 0;
141 182 counter_4 <= 0;
142 183 counter_5 <= 0;
143 184
144 MEM_IN_SM_wen <= (OTHERS => '1');
145 MEM_OUT_SM_ren <= (OTHERS => '1');
185 -- MEM_IN_SM_wen <= (OTHERS => '1');
186 -- MEM_OUT_SM_ren <= (OTHERS => '1');
146 187
147 188 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
148 IF MEM_IN_SM_locked_out(0) = '0' AND MEM_IN_SM_Full_out(0) = '0' THEN
149 counter_1 <= counter_1 + 1;
150 MEM_IN_SM_wData(15 DOWNTO 0) <= fft_1_re(counter_1);
151 MEM_IN_SM_wData(31 DOWNTO 16) <= fft_1_im(counter_1);
152 MEM_IN_SM_wen(0) <= '0';
153 ELSE
154 counter_1 <= 0;
155 MEM_IN_SM_wData(31 DOWNTO 0) <= (OTHERS => 'X');
156 MEM_IN_SM_wen(0) <= '1';
157 END IF;
189 --IF MEM_IN_SM_locked_out(0) = '0' AND MEM_IN_SM_Full_out(0) = '0' THEN
190 -- counter_1 <= counter_1 + 1;
191 -- MEM_IN_SM_wData(15 DOWNTO 0) <= fft_1_re(counter_1);
192 -- MEM_IN_SM_wData(31 DOWNTO 16) <= fft_1_im(counter_1);
193 -- MEM_IN_SM_wen(0) <= '0';
194 --ELSE
195 -- counter_1 <= 0;
196 -- MEM_IN_SM_wData(31 DOWNTO 0) <= (OTHERS => 'X');
197 -- MEM_IN_SM_wen(0) <= '1';
198 --END IF;
158 199
159 200 END IF;
160 201 END PROCESS;
161 202
203 PROCESS
204 BEGIN -- PROCESS
205 WAIT FOR 1 us;
206 not_full <= '0';
207 WAIT UNTIL clk = '1' AND clk'EVENT;
208 loop_DATA_write: FOR I IN 0 TO 127 LOOP
209 apbi.pwdata <= fft_1_im(I) & fft_1_re(I);
210 apbi.psel(15) <= '1';
211 apbi.paddr(7 DOWNTO 2) <= "000000";
212 apbi.penable <= '1';
213 apbi.pwrite <= '1';
214 WAIT UNTIL clk = '1' AND clk'EVENT;
162 215
216 apbi.pwdata <= fft_2_im(I) & fft_2_re(I);
217 apbi.psel(15) <= '1';
218 apbi.paddr(7 DOWNTO 2) <= "000001";
219 apbi.penable <= '1';
220 apbi.pwrite <= '1';
221 WAIT UNTIL clk = '1' AND clk'EVENT;
222
223 apbi.pwdata <= fft_3_im(I) & fft_3_re(I);
224 apbi.psel(15) <= '1';
225 apbi.paddr(7 DOWNTO 2) <= "000010";
226 apbi.penable <= '1';
227 apbi.pwrite <= '1';
228 WAIT UNTIL clk = '1' AND clk'EVENT;
229
230 apbi.pwdata <= fft_4_im(I) & fft_4_re(I);
231 apbi.psel(15) <= '1';
232 apbi.paddr(7 DOWNTO 2) <= "000011";
233 apbi.penable <= '1';
234 apbi.pwrite <= '1';
235 WAIT UNTIL clk = '1' AND clk'EVENT;
236
237 apbi.pwdata <= fft_5_im(I) & fft_5_re(I);
238 apbi.psel(15) <= '1';
239 apbi.paddr(7 DOWNTO 2) <= "000100";
240 apbi.penable <= '1';
241 apbi.pwrite <= '1';
242 WAIT UNTIL clk = '1' AND clk'EVENT;
243
244 apbi.pwdata <= X"FFFFFFE0";
245 apbi.psel(15) <= '1';
246 apbi.paddr(7 DOWNTO 2) <= "000101";
247 apbi.penable <= '1';
248 apbi.pwrite <= '1';
249 WAIT UNTIL clk = '1' AND clk'EVENT;
250
251 apbi.pwrite <= '0';
252 END LOOP loop_DATA_write;
253
254
255 WAIT UNTIL clk = '1' AND clk'EVENT;
256
257 not_full <= '0';
258
259 tant_que_not_full: WHILE not_full = '0' LOOP
260 -- apbi.pwdata <= X"FFFFFFE0";
261 apbi.psel(15) <= '1';
262 apbi.paddr(7 DOWNTO 2) <= "001000";
263 apbi.penable <= '1';
264 WAIT UNTIL clk = '1' AND clk'EVENT;
265 not_full <= apbo.prdata(3);
266 END LOOP tant_que_not_full;
267
268
269 all_data_0: FOR I IN 0 TO 127 LOOP
270 WAIT UNTIL clk = '1' AND clk'EVENT;
271 --apbi.pwdata <= X"FFFFFFFE";
272 apbi.psel(15) <= '1';
273 apbi.paddr(7 DOWNTO 2) <= "000110";
274 apbi.penable <= '1';
275 apbi.pwrite <= '0';
276 WAIT UNTIL clk = '1' AND clk'EVENT;
277 apbi.penable <= '0';
278 spectral_matrix_data(0,0)(0,I) <= apbo.prdata;
279 spectral_matrix_data(0,0)(1,I) <= (OTHERS => '0');
280 WAIT UNTIL clk = '1' AND clk'EVENT;
281 apbi.pwdata <= X"FFFFFFFE";
282 apbi.psel(15) <= '1';
283 apbi.paddr(7 DOWNTO 2) <= "001000";
284 apbi.penable <= '1';
285 apbi.pwrite <= '1';
286 WAIT UNTIL clk = '1' AND clk'EVENT;
287 apbi.pwrite <= '0';
288 apbi.penable <= '0';
289 WAIT UNTIL clk = '1' AND clk'EVENT;
290 END LOOP all_data_0;
291
292
293
294 WAIT FOR 100 us;
295
296 REPORT "*** END simulation ***" SEVERITY failure;
297 WAIT;
298
299 END PROCESS;
163 300
164 301
165 302
166 303
167 304
168 305
169 306 -------------------------------------------------------------------------------
170 307 -- MS ------------------------------------------------------------------------
171 308 -------------------------------------------------------------------------------
172 309
173 --lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb
174 -- GENERIC MAP (
175 -- pindex => 15,
176 -- paddr => 15,
177 -- pmask => 16#fff#)
178 -- PORT MAP (
179 -- HCLK => clk,
180 -- HRESETn => rstn,
181 -- apbi => apbi,
182 -- apbo => apbo,
310 lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb
311 GENERIC MAP (
312 pindex => 15,
313 paddr => 15,
314 pmask => 16#fff#)
315 PORT MAP (
316 HCLK => clk,
317 HRESETn => rstn,
318 apbi => apbi,
319 apbo => apbo,
183 320
184 -- MEM_IN_SM_wData => MEM_IN_SM_wData,
185 -- MEM_IN_SM_wen => MEM_IN_SM_wen,
186 -- MEM_IN_SM_Full_out => MEM_IN_SM_Full_out,
187 -- MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out,
188 -- MEM_IN_SM_locked_out => MEM_IN_SM_locked_out,
321 MEM_IN_SM_wData => MEM_IN_SM_wData,
322 MEM_IN_SM_wen => MEM_IN_SM_wen,
323 MEM_IN_SM_Full_out => MEM_IN_SM_Full_out,
324 MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out,
325 MEM_IN_SM_locked_out => MEM_IN_SM_locked_out,
189 326
190 -- MEM_OUT_SM_ren => MEM_OUT_SM_ren ,
191 -- MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out ,
192 -- MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad ,
193 -- MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 ,
194 -- MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad);
327 MEM_OUT_SM_ren => MEM_OUT_SM_ren ,
328 MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out ,
329 MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad ,
330 MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 ,
331 MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad);
195 332
196 333 lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb
197 334 GENERIC MAP (
198 Mem_use => use_CEL)
335 Mem_use => use_RAM)-- use_RAM use_CEL
199 336 PORT MAP (
200 337 clk => clk,
201 338 rstn => rstn,
202 339
203 340 MEM_IN_SM_wData => MEM_IN_SM_wData,
204 341 MEM_IN_SM_wen => MEM_IN_SM_wen,
205 342 MEM_IN_SM_Full_out => MEM_IN_SM_Full_out,
206 343 MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out,
207 344 MEM_IN_SM_locked_out => MEM_IN_SM_locked_out,
208 345
209 346 MEM_OUT_SM_Read => MEM_OUT_SM_ren ,
210 347 MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out ,
211 348 MEM_OUT_SM_Full_pad => MEM_OUT_SM_Full_pad ,
212 349 MEM_OUT_SM_Full_pad_2 => MEM_OUT_SM_Full_pad_2 ,
213 350 MEM_OUT_SM_Empty_pad => MEM_OUT_SM_Empty_pad,
214 351
215 352 error_input_fifo_write => OPEN,
216 353 observation_vector_0 => OPEN,
217 354 observation_vector_1 => OPEN);
218 355
219 356 -----------------------------------------------------------------------------
220 357 END tb;
Show file before | Show file after | Hide comments
@@ -1,100 +1,109
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 25
26 entity RAM_CEL is
27 generic(DataSz : integer range 1 to 32 := 8;
28 abits : integer range 2 to 12 := 8);
29 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
30 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
31 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
32 std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
26 ENTITY RAM_CEL IS
27 GENERIC(
28 DataSz : INTEGER RANGE 1 TO 32 := 8;
29 abits : INTEGER RANGE 2 TO 12 := 8);
30 PORT(
31 WD : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
32 RD : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
33 WEN, REN : IN STD_LOGIC;
34 WADDR : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
35 RADDR : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
36 RWCLK, RESET : IN STD_LOGIC
33 37 ) ;
34 end RAM_CEL;
38 END RAM_CEL;
35 39
36 40
37 41
38 architecture ar_RAM_CEL of RAM_CEL is
42 ARCHITECTURE ar_RAM_CEL OF RAM_CEL IS
39 43
40 constant VectInit : std_logic_vector(DataSz-1 downto 0):=(others => '0');
41 constant MAX : integer := 2**(abits);
44 CONSTANT VectInit : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0) := (OTHERS => '0');
45 CONSTANT MAX : INTEGER := 2**(abits);
42 46
43 type RAMarrayT is array (0 to MAX-1) of std_logic_vector(DataSz-1 downto 0);
47 TYPE RAMarrayT IS ARRAY (0 TO MAX-1) OF STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
44 48
45 signal RAMarray : RAMarrayT:=(others => VectInit);
46 signal RD_int : std_logic_vector(DataSz-1 downto 0);
49 SIGNAL RAMarray : RAMarrayT := (OTHERS => VectInit);
50 SIGNAL RD_int : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
47 51
48 begin
52 SIGNAL RADDR_reg : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
49 53
50 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
54 BEGIN
55
56 RD_int <= RAMarray(to_integer(UNSIGNED(RADDR)));
51 57
52 58
53 process(RWclk,reset)
54 begin
55 if reset = '0' then
59 PROCESS(RWclk, reset)
60 BEGIN
61 IF reset = '0' THEN
56 62 RD <= VectInit;
57 rst:for i in 0 to MAX-1 loop
58 RAMarray(i) <= (others => '0');
59 end loop;
63 rst : FOR i IN 0 TO MAX-1 LOOP
64 RAMarray(i) <= (OTHERS => '0');
65 END LOOP;
60 66
61 elsif RWclk'event and RWclk = '1' then
62 if REN = '0' then
67 ELSIF RWclk'EVENT AND RWclk = '1' THEN
68 -- IF REN = '0' THEN
63 69 RD <= RD_int;
64 end if;
70 -- END IF;
71 IF REN = '0' THEN
72 RADDR_reg <= RADDR;
73 END IF;
65 74
66 if WEN = '0' then
67 RAMarray(to_integer(unsigned(WADDR))) <= WD;
68 end if;
75 IF WEN = '0' THEN
76 RAMarray(to_integer(UNSIGNED(WADDR))) <= WD;
77 END IF;
69 78
70 end if;
71 end process;
72 end ar_RAM_CEL;
79 END IF;
80 END PROCESS;
81 END ar_RAM_CEL;
73 82
74 83
75 84
76 85
77 86
78 87
79 88
80 89
81 90
82 91
83 92
84 93
85 94
86 95
87 96
88 97
89 98
90 99
91 100
92 101
93 102
94 103
95 104
96 105
97 106
98 107
99 108
100 109
Show file before | Show file after | Hide comments
@@ -1,225 +1,253
1 1 LIBRARY IEEE;
2 2 USE IEEE.std_logic_1164.ALL;
3 3
4 4 LIBRARY lpp;
5 5 USE lpp.general_purpose.ALL;
6 6
7 7 ENTITY MS_calculation IS
8 8 PORT (
9 9 clk : IN STD_LOGIC;
10 10 rstn : IN STD_LOGIC;
11 11 -- IN
12 12 fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
13 13 fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
14 14 fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
15 15 -- OUT
16 16 fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
17 17 fifo_out_wen : OUT STD_LOGIC;
18 18 fifo_out_full : IN STD_LOGIC;
19 19 --
20 20 correlation_start : IN STD_LOGIC;
21 21 correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
22 22
23 23 correlation_begin : OUT STD_LOGIC;
24 24 correlation_done : OUT STD_LOGIC
25 25 );
26 26 END MS_calculation;
27 27
28 28 ARCHITECTURE beh OF MS_calculation IS
29 29
30 30 TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a);
31 31 SIGNAL state : fsm_calculation_MS;
32 32
33 33 SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
34 34 SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
35 35 SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0);
36 36
37 37 SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0);
38 38
39 39
40 40 CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
41 41 CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010";
42 42 CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001";
43 43 CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001";
44 44
45
45 SIGNAL select_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
46 CONSTANT select_ctrl_NOP : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
47 CONSTANT select_ctrl_MULT : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
48 CONSTANT select_ctrl_MAC : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
49 CONSTANT select_ctrl_MACn : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
46 50
47 51 SIGNAL select_op1 : STD_LOGIC;
48 52 SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
49 53
50 54 CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
51 55 CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
52 56 CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
53 57 CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
54 58
55 59 SIGNAL res_wen : STD_LOGIC;
56 60 SIGNAL res_wen_reg1 : STD_LOGIC;
57 61 SIGNAL res_wen_reg2 : STD_LOGIC;
58 62 --SIGNAL res_wen_reg3 : STD_LOGIC;
59 63
64 SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
65
60 66 BEGIN
61 67
62 68
69 PROCESS (clk, rstn)
70 BEGIN -- PROCESS
71 IF rstn = '0' THEN -- asynchronous reset (active low)
72 fifo_in_ren <= "11";
73 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
74 fifo_in_ren <= fifo_in_ren_s;
75 END IF;
76 END PROCESS;
77
63 78
64 79 PROCESS (clk, rstn)
65 80 BEGIN
66 81 IF rstn = '0' THEN
67 82
68 83 correlation_begin <= '0';
69 84 correlation_done <= '0';
70 85 state <= IDLE;
71 fifo_in_ren <= "11";
72 ALU_CTRL <= ALU_CTRL_NOP;
86 fifo_in_ren_s <= "11";
87 select_ctrl <= select_ctrl_NOP;
88 --ALU_CTRL <= ALU_CTRL_NOP;
73 89 select_op1 <= select_R0(0);
74 90 select_op2 <= select_R0;
75 91 res_wen <= '1';
76 92
77 93 ELSIF clk'EVENT AND clk = '1' THEN
78 ALU_CTRL <= ALU_CTRL_NOP;
94 select_ctrl <= select_ctrl_NOP;
95 --ALU_CTRL <= ALU_CTRL_NOP;
79 96 correlation_begin <= '0';
80 fifo_in_ren <= "11";
97 fifo_in_ren_s <= "11";
81 98 res_wen <= '1';
82 99 correlation_done <= '0';
83 100 CASE state IS
84 101 WHEN IDLE =>
85 102 IF correlation_start = '1' THEN
86 103 IF correlation_auto = '1' THEN
87 104 IF fifo_out_full = '1' THEN
88 105 state <= WFa;
89 106 ELSE
90 107 correlation_begin <= '1';
91 108 state <= S1a;
92 fifo_in_ren <= "10";
109 fifo_in_ren_s <= "10";
93 110 END IF;
94 111 ELSE
95 112 IF fifo_out_full = '1' THEN
96 113 state <= WF;
97 114 ELSE
98 115 correlation_begin <= '1';
99 116 state <= S1;
100 fifo_in_ren <= "00";
117 fifo_in_ren_s <= "00";
101 118 END IF;
102 119 END IF;
103 120 END IF;
104 121
105 122 ---------------------------------------------------------------------
106 123 -- INTER CORRELATION
107 124 ---------------------------------------------------------------------
108 125 WHEN WF =>
109 126 IF fifo_out_full = '0' THEN
110 127 correlation_begin <= '1';
111 128 state <= S1;
112 fifo_in_ren <= "00";
129 fifo_in_ren_s <= "00";
113 130 END IF;
114 131 WHEN S1 =>
115 ALU_CTRL <= ALU_CTRL_MULT;
132 select_ctrl <= select_ctrl_MULT;
133 --ALU_CTRL <= ALU_CTRL_MULT;
116 134 select_op1 <= select_R0(0);
117 135 select_op2 <= select_R1;
118 136 state <= S2;
119 137 WHEN S2 =>
120 ALU_CTRL <= ALU_CTRL_MAC;
138 select_ctrl <= select_ctrl_MAC;
139 --ALU_CTRL <= ALU_CTRL_MAC;
121 140 select_op1 <= select_I0(0);
122 141 select_op2 <= select_I1;
123 142 res_wen <= '0';
124 143 state <= S3;
125 144 WHEN S3 =>
126 ALU_CTRL <= ALU_CTRL_MULT;
145 select_ctrl <= select_ctrl_MULT;
146 --ALU_CTRL <= ALU_CTRL_MULT;
127 147 select_op1 <= select_I0(0);
128 148 select_op2 <= select_R1;
129 149 state <= S4;
130 150 WHEN S4 =>
131 ALU_CTRL <= ALU_CTRL_MACn;
151 select_ctrl <= select_ctrl_MACn;
152 --ALU_CTRL <= ALU_CTRL_MACn;
132 153 select_op1 <= select_R0(0);
133 154 select_op2 <= select_I1;
134 155 res_wen <= '0';
135 156 IF fifo_in_empty = "00" THEN
136 157 state <= S1;
137 fifo_in_ren <= "00";
158 fifo_in_ren_s <= "00";
138 159 ELSE
139 160 correlation_done <= '1';
140 161 state <= IDLE;
141 162 END IF;
142 163
143 164
144 165
145 166 ---------------------------------------------------------------------
146 167 -- AUTO CORRELATION
147 168 ---------------------------------------------------------------------
148 169 WHEN WFa =>
149 170 IF fifo_out_full = '0' THEN
150 171 correlation_begin <= '1';
151 172 state <= S1a;
152 fifo_in_ren <= "10";
173 fifo_in_ren_s <= "10";
153 174 END IF;
154 175 WHEN S1a =>
155 ALU_CTRL <= ALU_CTRL_MULT;
176 select_ctrl <= select_ctrl_MULT;
177 --ALU_CTRL <= ALU_CTRL_MULT;
156 178 select_op1 <= select_R0(0);
157 179 select_op2 <= select_R0;
158 180 state <= S2a;
159 181 WHEN S2a =>
160 ALU_CTRL <= ALU_CTRL_MAC;
182 select_ctrl <= select_ctrl_MAC;
183 --ALU_CTRL <= ALU_CTRL_MAC;
161 184 select_op1 <= select_I0(0);
162 185 select_op2 <= select_I0;
163 186 res_wen <= '0';
164 187 IF fifo_in_empty(0) = '0' THEN
165 188 state <= S1a;
166 fifo_in_ren <= "10";
189 fifo_in_ren_s <= "10";
167 190 ELSE
168 191 correlation_done <= '1';
169 192 state <= IDLE;
170 193 END IF;
171 194
172 195
173 196 WHEN OTHERS => NULL;
174 197 END CASE;
175 198
176 199 END IF;
177 200 END PROCESS;
178 201
202 ALU_CTRL <= ALU_CTRL_NOP WHEN select_ctrl = select_ctrl_NOP ELSE
203 ALU_CTRL_MULT WHEN select_ctrl = select_ctrl_MULT ELSE
204 ALU_CTRL_MAC WHEN select_ctrl = select_ctrl_MAC ELSE
205 ALU_CTRL_MACn;
206
179 207 OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE
180 208 fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE
181 209
182 210 OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE
183 211 fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE
184 212 fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE
185 213 fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE
186 214
187 215 ALU_MS : ALU
188 216 GENERIC MAP (
189 217 Arith_en => 1,
190 218 Logic_en => 0,
191 219 Input_SZ_1 => 16,
192 220 Input_SZ_2 => 16,
193 221 COMP_EN => 0) -- 0> Enable and 1> Disable
194 222 PORT MAP (
195 223 clk => clk,
196 224 reset => rstn,
197 225
198 226 ctrl => ALU_CTRL(2 DOWNTO 0),
199 227 comp => ALU_CTRL(4 DOWNTO 3),
200 228
201 229 OP1 => OP1,
202 230 OP2 => OP2,
203 231
204 232 RES => RES);
205 233
206 234 fifo_out_data <= RES;
207 235
208 236
209 237 PROCESS (clk, rstn)
210 238 BEGIN
211 239 IF rstn = '0' THEN
212 240 res_wen_reg1 <= '1';
213 241 res_wen_reg2 <= '1';
214 242 --res_wen_reg3 <= '1';
215 243 fifo_out_wen <= '1';
216 244 ELSIF clk'event AND clk = '1' THEN
217 245 res_wen_reg1 <= res_wen;
218 246 res_wen_reg2 <= res_wen_reg1;
219 247 --res_wen_reg3 <= res_wen_reg2;
220 248 fifo_out_wen <= res_wen_reg2;
221 249 END IF;
222 250 END PROCESS;
223 251
224 252
225 253 END beh;
General Comments 0
You need to be logged in to leave comments. Login now