@@ -0,0 +1,10 | |||
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1 | SUBDIRS := $(shell find ./ -maxdepth 1 -mindepth 1 -type d) | |
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2 | ||
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3 | all : | |
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4 | ||
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5 | .PHONY: force | |
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6 | ||
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7 | ||
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8 | %: | |
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9 | -for d in $(SUBDIRS); do (cd $$d; $(MAKE) $@ ); done | |
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10 |
@@ -30,4 +30,5 test: | |||
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30 | 30 | |
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31 | 31 | distclean: |
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32 | 32 | $(MAKE) -C tests distclean |
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33 | $(MAKE) -C designs distclean | |
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33 | 34 |
@@ -78,7 +78,7 set_io {led[0]} -pinname K17 -fixed yes | |||
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78 | 78 | set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout |
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79 | 79 | set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout |
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80 | 80 | |
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81 | set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout | |
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81 | #set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout | |
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82 | 82 | set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout |
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83 | 83 | set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout |
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84 | 84 | set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout |
@@ -256,6 +256,7 BEGIN -- beh | |||
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256 | 256 | NB_APB_SLAVE => NB_APB_SLAVE, |
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257 | 257 | ADDRESS_SIZE => 19, |
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258 | 258 | USES_IAP_MEMCTRLR => 1, |
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259 | USES_MBE_PIN => 1, | |
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259 | 260 | BYPASS_EDAC_MEMCTRLR => '0', |
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260 | 261 | SRBANKSZ => 8) |
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261 | 262 | PORT MAP ( |
@@ -260,6 +260,7 BEGIN -- beh | |||
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260 | 260 | NB_APB_SLAVE => NB_APB_SLAVE, |
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261 | 261 | ADDRESS_SIZE => 19, |
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262 | 262 | USES_IAP_MEMCTRLR => 1, |
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263 | USES_MBE_PIN => 1, | |
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263 | 264 | BYPASS_EDAC_MEMCTRLR => '0', |
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264 | 265 | SRBANKSZ => 8) |
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265 | 266 | PORT MAP ( |
@@ -602,4 +603,4 BEGIN -- beh | |||
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602 | 603 | --TAG(8) <= nSRAM_BUSY; |
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603 | 604 | END GENERATE USE_DEBUG_VECTOR_IF2; |
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604 | 605 | |
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605 | END beh; No newline at end of file | |
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606 | END beh; |
@@ -164,6 +164,7 ARCHITECTURE beh OF LFR_em IS | |||
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164 | 164 | ---------------------------------------------------------------------------- |
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165 | 165 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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166 | 166 | SIGNAL nSRAM_READY : STD_LOGIC; |
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167 | SIGNAL SRAM_MBE : STD_LOGIC; | |
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167 | 168 | |
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168 | 169 | BEGIN -- beh |
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169 | 170 | |
@@ -234,6 +235,7 BEGIN -- beh | |||
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234 | 235 | NB_APB_SLAVE => NB_APB_SLAVE, |
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235 | 236 | ADDRESS_SIZE => 20, |
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236 | 237 | USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, |
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238 | USES_MBE_PIN => 0, | |
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237 | 239 | BYPASS_EDAC_MEMCTRLR => '0', |
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238 | 240 | SRBANKSZ => 9) |
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239 | 241 | PORT MAP ( |
@@ -256,7 +258,7 BEGIN -- beh | |||
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256 | 258 | nSRAM_CE => nSRAM_CE_s, |
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257 | 259 | nSRAM_OE => nSRAM_OE, |
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258 | 260 | nSRAM_READY => nSRAM_READY, |
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259 |
SRAM_MBE => |
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261 | SRAM_MBE => SRAM_MBE, | |
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260 | 262 | |
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261 | 263 | apbi_ext => apbi_ext, |
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262 | 264 | apbo_ext => apbo_ext, |
@@ -1,4 +1,3 | |||
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1 | #GRLIB=../.. | |
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2 | 1 |
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3 | 2 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
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4 | 3 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
@@ -11,13 +10,9 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |||
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11 | 10 | EFFORT=high |
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12 | 11 | XSTOPT= |
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13 | 12 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" |
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14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |
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15 | #VHDLSYNFILES=config.vhd leon3mp.vhd | |
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16 | 13 |
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17 | 14 | VHDLSIMFILES=testbench.vhd |
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18 | #SIMTOP=testbench | |
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19 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |
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20 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc | |
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15 | ||
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21 | 16 |
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22 | 17 | |
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23 | 18 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc |
@@ -29,7 +24,7 CLEAN=soft-clean | |||
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29 | 24 | TECHLIBS = proasic3e |
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30 | 25 | |
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31 | 26 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ |
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32 | tmtc openchip hynix ihp gleichmann micron usbhc | |
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27 | tmtc openchip hynix ihp gleichmann micron usbhc opencores can greth | |
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33 | 28 | |
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34 | 29 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ |
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35 | 30 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ |
@@ -73,6 +73,7 ENTITY leon3_soc IS | |||
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73 | 73 | -- |
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74 | 74 | ADDRESS_SIZE : INTEGER := 19; |
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75 | 75 | USES_IAP_MEMCTRLR : INTEGER := 1; |
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76 | USES_MBE_PIN : INTEGER := 1; | |
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76 | 77 | BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0'; |
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77 | 78 | SRBANKSZ : INTEGER := 8; |
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78 | 79 | SLOW_TIMING_EMULATION : integer := 0 |
@@ -447,6 +448,7 BEGIN | |||
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447 | 448 | |
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448 | 449 | memi.brdyn <= nSRAM_READY; |
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449 | 450 | |
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451 | drv_mbe: IF USES_MBE_PIN = 1 GENERATE | |
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450 | 452 | mbe_pad : iopad |
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451 | 453 | GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR) |
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452 | 454 | PORT MAP(pad => SRAM_MBE, |
@@ -456,6 +458,12 BEGIN | |||
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456 | 458 | |
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457 | 459 | nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0)); |
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458 | 460 | nSRAM_OE_s <= memo.oen; |
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461 | END GENERATE; | |
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462 | ||
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463 | no_drv_mbe: IF USES_MBE_PIN /= 1 GENERATE | |
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464 | memi.bexcn <= '1'; | |
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465 | END GENERATE; | |
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466 | ||
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459 | 467 |
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460 | 468 | END GENERATE; |
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461 | 469 |
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