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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | -- jean-christophe.pellion@easii-ic.com |
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22 | 22 | ---------------------------------------------------------------------------- |
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23 | 23 | LIBRARY ieee; |
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24 | 24 | USE ieee.std_logic_1164.ALL; |
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25 | 25 | USE ieee.numeric_std.ALL; |
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26 | 26 | LIBRARY grlib; |
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27 | 27 | USE grlib.amba.ALL; |
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28 | 28 | USE grlib.stdlib.ALL; |
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29 | 29 | USE grlib.devices.ALL; |
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30 | 30 | LIBRARY lpp; |
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31 | 31 | USE lpp.lpp_amba.ALL; |
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32 | 32 | USE lpp.apb_devices_list.ALL; |
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33 | 33 | USE lpp.lpp_memory.ALL; |
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34 | 34 | LIBRARY techmap; |
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35 | 35 | USE techmap.gencomp.ALL; |
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36 | 36 | |
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37 | 37 | ENTITY lpp_top_apbreg IS |
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38 | 38 | GENERIC ( |
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39 | 39 | nb_burst_available_size : INTEGER := 11; |
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40 | 40 | nb_snapshot_param_size : INTEGER := 11; |
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41 | 41 | delta_snapshot_size : INTEGER := 16; |
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42 | 42 | delta_f2_f0_size : INTEGER := 10; |
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43 | 43 | delta_f2_f1_size : INTEGER := 10; |
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44 | 44 | |
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45 | 45 | pindex : INTEGER := 4; |
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46 | 46 | paddr : INTEGER := 4; |
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47 | 47 | pmask : INTEGER := 16#fff#; |
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48 | 48 | pirq : INTEGER := 0); |
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49 | 49 | PORT ( |
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50 | 50 | -- AMBA AHB system signals |
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51 | 51 | HCLK : IN STD_ULOGIC; |
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52 | 52 | HRESETn : IN STD_ULOGIC; |
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53 | 53 | |
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54 | 54 | -- AMBA APB Slave Interface |
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55 | 55 | apbi : IN apb_slv_in_type; |
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56 | 56 | apbo : OUT apb_slv_out_type; |
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57 | 57 | |
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58 | 58 | --------------------------------------------------------------------------- |
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59 | 59 | -- Spectral Matrix Reg |
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60 | 60 | -- IN |
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61 | 61 | ready_matrix_f0_0 : IN STD_LOGIC; |
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62 | 62 | ready_matrix_f0_1 : IN STD_LOGIC; |
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63 | 63 | ready_matrix_f1 : IN STD_LOGIC; |
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64 | 64 | ready_matrix_f2 : IN STD_LOGIC; |
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65 | 65 | error_anticipating_empty_fifo : IN STD_LOGIC; |
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66 | 66 | error_bad_component_error : IN STD_LOGIC; |
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67 | 67 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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68 | 68 | |
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69 | 69 | -- OUT |
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70 | 70 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
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71 | 71 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
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72 | 72 | status_ready_matrix_f1 : OUT STD_LOGIC; |
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73 | 73 | status_ready_matrix_f2 : OUT STD_LOGIC; |
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74 | 74 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
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75 | 75 | status_error_bad_component_error : OUT STD_LOGIC; |
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76 | 76 | |
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77 | 77 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
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78 | 78 | config_active_interruption_onError : OUT STD_LOGIC; |
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79 | 79 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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80 | 80 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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81 | 81 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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82 | 82 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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83 | 83 | --------------------------------------------------------------------------- |
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84 | 84 | --------------------------------------------------------------------------- |
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85 | 85 | -- WaveForm picker Reg |
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86 | 86 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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87 | 87 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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88 | 88 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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89 | 89 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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90 | 90 | |
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91 | 91 | -- OUT |
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92 | 92 | data_shaping_BW : OUT STD_LOGIC; |
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93 | 93 | data_shaping_SP0 : OUT STD_LOGIC; |
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94 | 94 | data_shaping_SP1 : OUT STD_LOGIC; |
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95 | 95 | data_shaping_R0 : OUT STD_LOGIC; |
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96 | 96 | data_shaping_R1 : OUT STD_LOGIC; |
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97 | 97 | |
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98 | 98 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
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99 | 99 | delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
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100 | 100 | delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
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101 | 101 | nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
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102 | 102 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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103 | 103 | |
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104 | 104 | enable_f0 : OUT STD_LOGIC; |
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105 | 105 | enable_f1 : OUT STD_LOGIC; |
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106 | 106 | enable_f2 : OUT STD_LOGIC; |
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107 | 107 | enable_f3 : OUT STD_LOGIC; |
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108 | 108 | |
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109 | 109 | burst_f0 : OUT STD_LOGIC; |
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110 | 110 | burst_f1 : OUT STD_LOGIC; |
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111 | 111 | burst_f2 : OUT STD_LOGIC; |
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112 | 112 | |
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113 | 113 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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114 | 114 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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115 | 115 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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116 | 116 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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117 | 117 | |
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118 | 118 | --------------------------------------------------------------------------- |
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119 | 119 | ); |
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120 | 120 | |
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121 | 121 | END lpp_top_apbreg; |
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122 | 122 | |
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123 | 123 | ARCHITECTURE beh OF lpp_top_apbreg IS |
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124 | 124 | |
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125 | 125 | CONSTANT REVISION : INTEGER := 1; |
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126 | 126 | |
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127 | 127 | CONSTANT pconfig : apb_config_type := ( |
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128 | 128 | 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 2, REVISION, pirq), |
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129 | 129 | 1 => apb_iobar(paddr, pmask)); |
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130 | 130 | |
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131 | 131 | TYPE lpp_SpectralMatrix_regs IS RECORD |
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132 | 132 | config_active_interruption_onNewMatrix : STD_LOGIC; |
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133 | 133 | config_active_interruption_onError : STD_LOGIC; |
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134 | 134 | status_ready_matrix_f0_0 : STD_LOGIC; |
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135 | 135 | status_ready_matrix_f0_1 : STD_LOGIC; |
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136 | 136 | status_ready_matrix_f1 : STD_LOGIC; |
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137 | 137 | status_ready_matrix_f2 : STD_LOGIC; |
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138 | 138 | status_error_anticipating_empty_fifo : STD_LOGIC; |
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139 | 139 | status_error_bad_component_error : STD_LOGIC; |
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140 | 140 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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141 | 141 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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142 | 142 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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143 | 143 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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144 | 144 | END RECORD; |
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145 | 145 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
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146 | 146 | |
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147 | 147 | TYPE lpp_WaveformPicker_regs IS RECORD |
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148 | 148 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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149 | 149 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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150 | 150 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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151 | 151 | data_shaping_BW : STD_LOGIC; |
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152 | 152 | data_shaping_SP0 : STD_LOGIC; |
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153 | 153 | data_shaping_SP1 : STD_LOGIC; |
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154 | 154 | data_shaping_R0 : STD_LOGIC; |
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155 | 155 | data_shaping_R1 : STD_LOGIC; |
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156 | 156 | delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
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157 | 157 | delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
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158 | 158 | delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
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159 | 159 | nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
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160 | 160 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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161 | 161 | enable_f0 : STD_LOGIC; |
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162 | 162 | enable_f1 : STD_LOGIC; |
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163 | 163 | enable_f2 : STD_LOGIC; |
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164 | 164 | enable_f3 : STD_LOGIC; |
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165 | 165 | burst_f0 : STD_LOGIC; |
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166 | 166 | burst_f1 : STD_LOGIC; |
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167 | 167 | burst_f2 : STD_LOGIC; |
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168 | 168 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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169 | 169 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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170 | 170 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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171 | 171 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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172 | 172 | END RECORD; |
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173 | 173 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
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174 | 174 | |
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175 | 175 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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176 | 176 | |
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177 | 177 | BEGIN -- beh |
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178 | 178 | |
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179 | 179 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; |
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180 | 180 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; |
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181 | 181 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; |
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182 | 182 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
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183 | 183 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; |
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184 | 184 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; |
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185 | 185 | |
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186 | 186 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; |
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187 | 187 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; |
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188 | 188 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; |
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189 | 189 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; |
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190 | 190 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; |
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191 | 191 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; |
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192 | 192 | |
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193 | 193 | |
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194 | 194 | |
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195 | 195 | |
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196 | data_shaping_BW <= reg_wp.data_shaping_BW; | |
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196 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |
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197 | 197 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; |
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198 | 198 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; |
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199 | 199 | data_shaping_R0 <= reg_wp.data_shaping_R0; |
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200 | 200 | data_shaping_R1 <= reg_wp.data_shaping_R1; |
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201 | 201 | |
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202 | 202 | delta_snapshot <= reg_wp.delta_snapshot; |
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203 | 203 | delta_f2_f1 <= reg_wp.delta_f2_f1; |
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204 | 204 | delta_f2_f0 <= reg_wp.delta_f2_f0; |
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205 | 205 | nb_burst_available <= reg_wp.nb_burst_available; |
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206 | 206 | nb_snapshot_param <= reg_wp.nb_snapshot_param; |
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207 | 207 | |
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208 | 208 | enable_f0 <= reg_wp.enable_f0; |
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209 | 209 | enable_f1 <= reg_wp.enable_f1; |
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210 | 210 | enable_f2 <= reg_wp.enable_f2; |
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211 | 211 | enable_f3 <= reg_wp.enable_f3; |
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212 | 212 | |
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213 | 213 | burst_f0 <= reg_wp.burst_f0; |
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214 | 214 | burst_f1 <= reg_wp.burst_f1; |
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215 | 215 | burst_f2 <= reg_wp.burst_f2; |
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216 | 216 | |
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217 | 217 | addr_data_f0 <= reg_wp.addr_data_f0; |
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218 | 218 | addr_data_f1 <= reg_wp.addr_data_f1; |
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219 | 219 | addr_data_f2 <= reg_wp.addr_data_f2; |
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220 | 220 | addr_data_f3 <= reg_wp.addr_data_f3; |
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221 | 221 | |
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222 | 222 | lpp_top_apbreg : PROCESS (HCLK, HRESETn) |
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223 | 223 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
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224 | 224 | BEGIN -- PROCESS lpp_dma_top |
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225 | 225 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
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226 | 226 | reg_sp.config_active_interruption_onNewMatrix <= '0'; |
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227 | 227 | reg_sp.config_active_interruption_onError <= '0'; |
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228 | 228 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
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229 | 229 | reg_sp.status_ready_matrix_f0_1 <= '0'; |
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230 | 230 | reg_sp.status_ready_matrix_f1 <= '0'; |
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231 | 231 | reg_sp.status_ready_matrix_f2 <= '0'; |
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232 | 232 | reg_sp.status_error_anticipating_empty_fifo <= '0'; |
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233 | 233 | reg_sp.status_error_bad_component_error <= '0'; |
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234 | 234 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); |
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235 | 235 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); |
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236 | 236 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); |
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237 | 237 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); |
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238 | 238 | prdata <= (OTHERS => '0'); |
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239 | 239 | |
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240 | 240 | apbo.pirq <= (OTHERS => '0'); |
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241 | 241 | |
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242 | 242 | status_full_ack <= (OTHERS => '0'); |
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243 | 243 | |
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244 | 244 | reg_wp.data_shaping_BW <= '0'; |
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245 | 245 | reg_wp.data_shaping_SP0 <= '0'; |
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246 | 246 | reg_wp.data_shaping_SP1 <= '0'; |
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247 | 247 | reg_wp.data_shaping_R0 <= '0'; |
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248 | 248 | reg_wp.data_shaping_R1 <= '0'; |
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249 | 249 | reg_wp.enable_f0 <= '0'; |
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250 | 250 | reg_wp.enable_f1 <= '0'; |
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251 | 251 | reg_wp.enable_f2 <= '0'; |
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252 | 252 | reg_wp.enable_f3 <= '0'; |
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253 | 253 | reg_wp.burst_f0 <= '0'; |
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254 | 254 | reg_wp.burst_f1 <= '0'; |
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255 | 255 | reg_wp.burst_f2 <= '0'; |
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256 | 256 | reg_wp.addr_data_f0 <= (OTHERS => '0'); |
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257 | 257 | reg_wp.addr_data_f1 <= (OTHERS => '0'); |
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258 | 258 | reg_wp.addr_data_f2 <= (OTHERS => '0'); |
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259 | 259 | reg_wp.addr_data_f3 <= (OTHERS => '0'); |
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260 | 260 | reg_wp.status_full <= (OTHERS => '0'); |
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261 | 261 | reg_wp.status_full_err <= (OTHERS => '0'); |
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262 | 262 | reg_wp.status_new_err <= (OTHERS => '0'); |
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263 | 263 | reg_wp.delta_snapshot <= (OTHERS => '0'); |
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264 | 264 | reg_wp.delta_f2_f1 <= (OTHERS => '0'); |
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265 | 265 | reg_wp.delta_f2_f0 <= (OTHERS => '0'); |
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266 | 266 | reg_wp.nb_burst_available <= (OTHERS => '0'); |
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267 | 267 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); |
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268 | 268 | |
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269 | 269 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
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270 | 270 | status_full_ack <= (OTHERS => '0'); |
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271 | 271 | |
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272 | 272 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; |
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273 | 273 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; |
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274 | 274 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; |
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275 | 275 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; |
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276 | 276 | |
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277 | 277 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
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278 | 278 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
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279 | 279 | |
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280 | 280 | reg_wp.status_full <= reg_wp.status_full OR status_full; |
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281 | 281 | reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err; |
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282 | 282 | reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err; |
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283 | 283 | |
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284 | 284 | paddr := "000000"; |
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285 | 285 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
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286 | 286 | prdata <= (OTHERS => '0'); |
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287 | 287 | IF apbi.psel(pindex) = '1' THEN |
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288 | 288 | -- APB DMA READ -- |
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289 | 289 | CASE paddr(7 DOWNTO 2) IS |
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290 | 290 | -- |
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291 | 291 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; |
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292 | 292 | prdata(1) <= reg_sp.config_active_interruption_onError; |
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293 | 293 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
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294 | 294 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; |
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295 | 295 | prdata(2) <= reg_sp.status_ready_matrix_f1; |
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296 | 296 | prdata(3) <= reg_sp.status_ready_matrix_f2; |
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297 | 297 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; |
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298 | 298 | prdata(5) <= reg_sp.status_error_bad_component_error; |
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299 | 299 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; |
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300 | 300 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; |
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301 | 301 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; |
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302 | 302 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; |
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303 | 303 | WHEN "000110" => prdata <= debug_reg; |
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304 | 304 | -- |
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305 | 305 | WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW; |
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306 | 306 | prdata(1) <= reg_wp.data_shaping_SP0; |
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307 | 307 | prdata(2) <= reg_wp.data_shaping_SP1; |
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308 | 308 | prdata(3) <= reg_wp.data_shaping_R0; |
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309 | 309 | prdata(4) <= reg_wp.data_shaping_R1; |
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310 | 310 | WHEN "001001" => prdata(0) <= reg_wp.enable_f0; |
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311 | 311 | prdata(1) <= reg_wp.enable_f1; |
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312 | 312 | prdata(2) <= reg_wp.enable_f2; |
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313 | 313 | prdata(3) <= reg_wp.enable_f3; |
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314 | 314 | prdata(4) <= reg_wp.burst_f0; |
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315 | 315 | prdata(5) <= reg_wp.burst_f1; |
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316 | 316 | prdata(6) <= reg_wp.burst_f2; |
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317 | 317 | WHEN "001010" => prdata <= reg_wp.addr_data_f0; |
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318 | 318 | WHEN "001011" => prdata <= reg_wp.addr_data_f1; |
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319 | 319 | WHEN "001100" => prdata <= reg_wp.addr_data_f2; |
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320 | 320 | WHEN "001101" => prdata <= reg_wp.addr_data_f3; |
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321 | 321 | WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; |
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322 | 322 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
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323 | 323 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; |
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324 | 324 | WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; |
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325 | 325 | WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1; |
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326 | 326 | WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0; |
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327 | 327 | WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available; |
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328 | 328 | WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; |
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329 | 329 | -- |
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330 | 330 | WHEN OTHERS => NULL; |
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331 | 331 | END CASE; |
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332 | 332 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
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333 | 333 | -- APB DMA WRITE -- |
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334 | 334 | CASE paddr(7 DOWNTO 2) IS |
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335 | 335 | -- |
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336 | 336 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
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337 | 337 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
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338 | 338 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); |
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339 | 339 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); |
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340 | 340 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); |
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341 | 341 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); |
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342 | 342 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); |
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343 | 343 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); |
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344 | 344 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; |
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345 | 345 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; |
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346 | 346 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; |
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347 | 347 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; |
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348 | 348 | -- |
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349 | 349 | WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); |
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350 | 350 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
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351 | 351 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); |
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352 | 352 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
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353 | 353 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); |
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354 | 354 | WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0); |
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355 | 355 | reg_wp.enable_f1 <= apbi.pwdata(1); |
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356 | 356 | reg_wp.enable_f2 <= apbi.pwdata(2); |
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357 | 357 | reg_wp.enable_f3 <= apbi.pwdata(3); |
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358 | 358 | reg_wp.burst_f0 <= apbi.pwdata(4); |
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359 | 359 | reg_wp.burst_f1 <= apbi.pwdata(5); |
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360 | 360 | reg_wp.burst_f2 <= apbi.pwdata(6); |
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361 | 361 | WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata; |
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362 | 362 | WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata; |
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363 | 363 | WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata; |
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364 | 364 | WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata; |
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365 | 365 | WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); |
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366 | 366 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
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367 | 367 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
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368 | 368 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); |
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369 | 369 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); |
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370 | 370 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); |
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371 | 371 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); |
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372 | 372 | WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0); |
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373 | 373 | WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0); |
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374 | 374 | WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0); |
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375 | 375 | WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0); |
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376 | 376 | WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); |
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377 | 377 | -- |
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378 | 378 | WHEN OTHERS => NULL; |
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|
379 | 379 | END CASE; |
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380 | 380 | END IF; |
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381 | 381 | END IF; |
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382 | 382 | |
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383 | 383 | apbo.pirq(pirq) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR |
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384 | 384 | ready_matrix_f0_1 OR |
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385 | 385 | ready_matrix_f1 OR |
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386 | 386 | ready_matrix_f2) |
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387 | 387 | ) |
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388 | 388 | OR |
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389 | 389 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR |
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390 | 390 | error_bad_component_error) |
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391 | 391 | ) |
|
|
392 | 392 | OR |
|
|
393 | 393 | (status_full(0) OR status_full_err(0) OR status_new_err(0) OR |
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394 | 394 | status_full(1) OR status_full_err(1) OR status_new_err(1) OR |
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395 | 395 | status_full(2) OR status_full_err(2) OR status_new_err(2) OR |
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396 | 396 | status_full(3) OR status_full_err(3) OR status_new_err(3) |
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397 | 397 | ); |
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398 | 398 | |
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399 | 399 | |
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400 | 400 | END IF; |
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401 | 401 | END PROCESS lpp_top_apbreg; |
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402 | 402 | |
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403 | 403 | apbo.pindex <= pindex; |
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404 | 404 | apbo.pconfig <= pconfig; |
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405 | 405 | apbo.prdata <= prdata; |
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406 | 406 | |
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407 | 407 | |
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408 | END beh; No newline at end of file | |
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408 | END beh; | |
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