##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

fixed bug on UART
martin -
r62:add206a96e71 default
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,44
1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19
20 include ../../rules.mk
21 LIBDIR = ../../lib
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
24 LIBS=-lapb_uart_Driver -llpp_apb_functions
25 INPUTFILE=main.c
26 EXEC=BenchUART.bin
27 OUTBINDIR=bin/
28
29
30 .PHONY:bin
31
32 all:bin
33 @echo $(EXEC)" file created"
34
35 clean:
36 rm -f *.{o,a}
37
38
39
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
44
Show file before | Show file after | Hide comments
@@ -0,0 +1,56
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_UART_DRIVER_H
23 #define APB_UART_DRIVER_H
24
25
26 #define BaudGenOnDuty 0
27 #define DataSended 0x10
28 #define NewData 0x100
29
30 /*===================================================
31 T Y P E S D E F
32 ====================================================*/
33
34 struct UART_Driver
35 {
36 int ConfigReg;
37 int DataWReg;
38 int DataRReg;
39 };
40
41 typedef struct UART_Driver UART_Device;
42
43
44 /*===================================================
45 F U N C T I O N S
46 ====================================================*/
47
48
49 UART_Device* openUART(int count);
50 void uartputc(UART_Device* dev,char c);
51 void uartputs(UART_Device* dev,char* s);
52 char uartgetc(UART_Device* dev);
53 void uartgets(UART_Device* dev,char* s);
54
55
56 #endif
Show file before | Show file after | Hide comments
@@ -0,0 +1,25
1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19 FILE = apb_uart_Driver
20 LIB = liblpp_uart_Driver.a
21
22 include ../../rules.mk
23
24 all: $(FILE).a
25 @echo $(FILE)".a created"
Show file before | Show file after | Hide comments
@@ -0,0 +1,124
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FFT_config.all;
26
27 entity Flag_Extremum is
28 port(
29 clk,raz : in std_logic;
30 load : in std_logic;
31 y_rdy : in std_logic;
32 d_valid_WR : in std_logic;
33 read_y_RE : in std_logic;
34 full : out std_logic;
35 empty : out std_logic
36 );
37 end Flag_Extremum;
38
39 architecture ar_Flag_Extremum of Flag_Extremum is
40
41 type etat is (eA,eB,eC,eD,eX,e0,e1,e2,e3);
42 signal ect : etat;
43
44 signal load_reg : std_logic;
45 signal y_rdy_reg : std_logic;
46 signal RE_reg : std_logic;
47 signal WR_reg : std_logic;
48
49 begin
50 process (clk,raz)
51 begin
52 if(raz='0')then
53 full <= '0';
54 empty <= '1';
55 ect <= eA;
56
57 elsif(clk' event and clk='1')then
58 load_reg <= load;
59 y_rdy_reg <= y_rdy;
60 RE_reg <= read_y_RE;
61 WR_reg <= d_valid_WR;
62
63 case ect is
64
65 when eA =>
66 if(WR_reg='0' and d_valid_WR='1')then
67 empty <= '0';
68 ect <= eB;
69 end if;
70
71 when eB =>
72 if(load_reg='1' and load='0')then
73 ect <= eC;
74 end if;
75
76 when eC =>
77 if(load_reg='1' and load='0')then
78 full <= '1';
79 ect <= eD;
80 end if;
81
82 when eD =>
83 if(RE_reg='0' and read_y_RE='1')then
84 full <= '0';
85 ect <= eX;
86 end if;
87
88 when eX =>
89 empty <= '1';
90 ect <= e0;
91
92 when e0 =>
93 if(WR_reg='0' and d_valid_WR='1')then
94 empty <= '0';
95 ect <= e1;
96 end if;
97
98 when e1 =>
99 if(load_reg='1' and load='0')then
100 full <= '1';
101 ect <= e2;
102 end if;
103
104 when e2 =>
105 if(RE_reg='0' and read_y_RE='1')then
106 full <= '0';
107 ect <= e3;
108 end if;
109
110 when e3 =>
111 if(y_rdy_reg='1' and y_rdy='0')then
112 empty <= '1';
113 ect <= e0;
114 end if;
115
116 end case;
117 end if;
118 end process;
119
120 end ar_Flag_Extremum;
121
122
123
124
Show file before | Show file after | Hide comments
@@ -27,7 +27,7
27 27 UART_Device* openUART(int count)
28 28 {
29 29 UART_Device* uart0;
30 uart0 = (UART_Device*) apbgetdevice(LPP_UART_CTRLR,VENDOR_LPP,count);
30 uart0 = (UART_Device*) apbgetdevice(LPP_UART,VENDOR_LPP,count);
31 31 uart0->ConfigReg = BaudGenOnDuty;
32 32 return uart0;
33 33 }
Show file before | Show file after | Hide comments
@@ -29,6 +29,7 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_fft.all;
32 use lpp.lpp_memory.all;
32 33 use work.fft_components.all;
33 34
34 35 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
@@ -63,20 +64,24 signal DataOut : std_logic_vector(D
63 64 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
64 65 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
65 66
66 signal X,Y,Z : std_logic;
67 --signal Pong : std_logic;
68 --signal Valid : std_logic;
67 signal start : std_logic;
68 signal load : std_logic;
69 signal rdy : std_logic;
69 70 signal DummyIn : std_logic_vector(Data_sz-1 downto 0);
70 --signal DummyOut : std_logic_vector(Data_sz-1 downto 0);
71
71 72
72 73 begin
73 74
74 APB : entity work.ApbDriver
75 APB : ApbDriver
75 76 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
76 77 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77 78
78 79
79 DEVICE : entity work.CoreFFT
80 Extremum : Flag_Extremum
81 port map(clk,raz,load,rdy,WriteEnable,ReadEnable,FlagFull,FlagEmpty);
82
83
84 DEVICE : CoreFFT
80 85 generic map(
81 86 LOGPTS => gLOGPTS,
82 87 LOGLOGPTS => gLOGLOGPTS,
@@ -89,11 +94,11 begin
89 94 PTS => gPTS,
90 95 HALFPTS => gHALFPTS,
91 96 inBuf_RWDLY => gInBuf_RWDLY)
92 port map(clk,X,rst,WriteEnable,ReadEnable,DummyIn,DataIn,Y,open,open,DataOut,open,Z);
97 port map(clk,start,rst,WriteEnable,ReadEnable,DummyIn,DataIn,load,open,open,DataOut,open,rdy);
93 98
94 X <= not rst;
95 Y <= not FlagFull;
96 Z <= not FlagEmpty;
99 start <= not rst;
100 --FlagFull <= not load;
101 --FlagEmpty <= not rdy;
97 102 DummyIn <= (others => '0');
98 103
99 104 end ar_APB_FFT; No newline at end of file
Show file before | Show file after | Hide comments
@@ -53,6 +53,19 component APB_FFT is
53 53 end component;
54 54
55 55
56 component Flag_Extremum is
57 port(
58 clk,raz : in std_logic;
59 load : in std_logic;
60 y_rdy : in std_logic;
61 d_valid_WR : in std_logic;
62 read_y_RE : in std_logic;
63 full : out std_logic;
64 empty : out std_logic
65 );
66 end component;
67
68
56 69 component CoreFFT IS
57 70 GENERIC (
58 71 LOGPTS : integer := gLOGPTS;
Show file before | Show file after | Hide comments
@@ -77,7 +77,7 begin
77 77 enable <= Rec.CNA_Cfg(0);
78 78 Rec.CNA_Cfg(1) <= flag_sd;
79 79
80 CONVERTER : entity Work.CNA_TabloC
80 CONVERTER : CNA_TabloC
81 81 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
82 82
83 83
Show file before | Show file after | Hide comments
@@ -28,7 +28,7 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
31 use lpp.lpp_memory.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34 34
@@ -64,12 +64,12 signal AddrOut : std_logic_vector(A
64 64
65 65 begin
66 66
67 APB : entity work.ApbDriver
67 APB : ApbDriver
68 68 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
69 69 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
70 70
71 71
72 DEVICE : entity work.Top_FIFO
72 DEVICE : Top_FIFO
73 73 generic map(Data_sz,Addr_sz,addr_max_int)
74 74 port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
75 75
Show file before | Show file after | Hide comments
@@ -52,76 +52,29 entity APB_FifoRead is
52 52 );
53 53 end APB_FifoRead;
54 54
55 --! @details Gestion de la FIFO uniquement en �criture
55 56
56 57 architecture ar_APB_FifoRead of APB_FifoRead is
57 58
58 constant REVISION : integer := 1;
59
60 constant pconfig : apb_config_type := (
61 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0),
62 1 => apb_iobar(paddr, pmask));
63
64 type FIFO_ctrlr_Reg is record
65 FIFO_Cfg : std_logic_vector(1 downto 0);
66 FIFO_DataW : std_logic_vector(15 downto 0);
67 FIFO_DataR : std_logic_vector(15 downto 0);
68 FIFO_AddrR : std_logic_vector(7 downto 0);
69 end record;
70
71 signal Rec : FIFO_ctrlr_Reg;
72 signal Rdata : std_logic_vector(31 downto 0);
73
74 signal flag_RE : std_logic;
75 signal empty : std_logic;
59 signal ReadEnable : std_logic;
60 --signal WriteEnable : std_logic;
61 signal FlagEmpty : std_logic;
62 --signal FlagFull : std_logic;
63 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
64 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
65 --signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
66 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
76 67
77 68 begin
78 69
79 Rec.FIFO_Cfg(0) <= flag_RE;
80 Rec.FIFO_Cfg(2) <= empty;
81
82
83 MEMORY_READ : entity Work.Top_FifoRead
84 generic map(Data_sz,Addr_sz,addr_max_int)
85 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,Rec.FIFO_AddrR,full,Waddr,Rec.FIFO_DataR);
70 APB : ApbDriver
71 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
72 port map(clk,rst,ReadEnable,open,FlagEmpty,open,DataIn,DataOut,open,AddrOut,apbi,apbo);
86 73
87 74
88 process(rst,clk)
89 begin
90 if(rst='0')then
91 Rec.FIFO_AddrR <= (others => '0');
92
93 elsif(clk'event and clk='1')then
94
95 --APB Write OP
96 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
97 case apbi.paddr(abits-1 downto 2) is
98 when others =>
99 null;
100 end case;
101 end if;
75 MEMORY_READ : Top_FifoRead
76 generic map(Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,ReadEnable,flag_WR,DataIn,Waddr,FlagEmpty,AddrOut,DataOut);
102 78
103 --APB Read OP
104 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
105 case apbi.paddr(abits-1 downto 2) is
106 when "000000" =>
107 Rdata(31 downto 16) <= X"DDDD";
108 Rdata(15 downto 0) <= Rec.FIFO_DataR;
109 when "000001" =>
110 Rdata(31 downto 8) <= X"AAAAAA";
111 Rdata(7 downto 0) <= Rec.FIFO_AddrR;
112 when "000010" =>
113 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
114 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
115 Rdata(31 downto 8) <= X"CCCCCC";
116 when others =>
117 Rdata <= (others => '0');
118 end case;
119 end if;
120
121 end if;
122 apbo.pconfig <= pconfig;
123 end process;
124
125 apbo.prdata <= Rdata when apbi.penable = '1';
126 79
127 80 end ar_APB_FifoReade; No newline at end of file
Show file before | Show file after | Hide comments
@@ -52,80 +52,29 entity APB_FifoWrite is
52 52 );
53 53 end APB_FifoWrite;
54 54
55 --! @details Gestion de la FIFO uniquement en lecture
55 56
56 57 architecture ar_APB_FifoWrite of APB_FifoWrite is
57 58
58 constant REVISION : integer := 1;
59
60 constant pconfig : apb_config_type := (
61 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0),
62 1 => apb_iobar(paddr, pmask));
63
64 type FIFO_ctrlr_Reg is record
65 FIFO_Cfg : std_logic_vector(1 downto 0);
66 FIFO_DataW : std_logic_vector(15 downto 0);
67 FIFO_DataR : std_logic_vector(15 downto 0);
68 FIFO_AddrW : std_logic_vector(7 downto 0);
69 end record;
70
71 signal Rec : FIFO_ctrlr_Reg;
72 signal Rdata : std_logic_vector(31 downto 0);
73
74 signal flag_WR : std_logic;
75 signal full : std_logic;
59 --signal ReadEnable : std_logic;
60 signal WriteEnable : std_logic;
61 --signal FlagEmpty : std_logic;
62 signal FlagFull : std_logic;
63 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
64 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
65 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
66 --signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
76 67
77 68 begin
78 69
79 Rec.FIFO_Cfg(0) <= flag_WR;
80 Rec.FIFO_Cfg(1) <= full;
81
82 MEMORY_WRITE : entity Work.Top_FifoWrite
83 generic map(Data_sz,Addr_sz,addr_max_int)
84 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,Raddr,full,Rec.FIFO_AddrW,Rec.FIFO_DataR);
70 APB : ApbDriver
71 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
72 port map(clk,rst,open,WriteEnable,open,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
85 73
86 74
87 process(rst,clk)
88 begin
89 if(rst='0')then
90 Rec.FIFO_DataW <= (others => '0');
91
92 elsif(clk'event and clk='1')then
93
94 --APB Write OP
95 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
96 case apbi.paddr(abits-1 downto 2) is
97 when "000000" =>
98 flag_WR <= '1';
99 Rec.FIFO_DataW <= apbi.pwdata(15 downto 0);
100 when others =>
101 null;
102 end case;
103 else
104 flag_WR <= '0';
105 end if;
75 MEMORY_WRITE : Top_FifoWrite
76 generic map(Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,flag_RE,WriteEnable,DataIn,Raddr,FlagFull,AddrIn,DataOut);
106 78
107 --APB Read OP
108 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
109 case apbi.paddr(abits-1 downto 2) is
110 when "000000" =>
111 Rdata(31 downto 16) <= X"DDDD";
112 Rdata(15 downto 0) <= Rec.FIFO_DataR;
113 when "000001" =>
114 Rdata(31 downto 8) <= X"AAAAAA";
115 Rdata(7 downto 0) <= Rec.FIFO_AddrW;
116 when "000010" =>
117 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
118 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
119 Rdata(31 downto 8) <= X"CCCCCC";
120 when others =>
121 Rdata <= (others => '0');
122 end case;
123 end if;
124
125 end if;
126 apbo.pconfig <= pconfig;
127 end process;
128
129 apbo.prdata <= Rdata when apbi.penable = '1';
130 79
131 80 end ar_APB_FifoWrite; No newline at end of file
Show file before | Show file after | Hide comments
@@ -29,6 +29,7 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31
32 --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO
32 33
33 34 entity ApbDriver is
34 35 generic (
@@ -44,19 +45,20 entity ApbDriver is
44 45 port (
45 46 clk : in std_logic; --! Horloge du composant
46 47 rst : in std_logic; --! Reset general du composant
47 ReadEnable : out std_logic;
48 WriteEnable : out std_logic;
49 FlagEmpty : in std_logic;
50 FlagFull : in std_logic;
51 DataIn : out std_logic_vector(Data_sz-1 downto 0);
52 DataOut : in std_logic_vector(Data_sz-1 downto 0);
53 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
54 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
48 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
50 FlagEmpty : in std_logic; --! Flag, M�moire vide
51 FlagFull : in std_logic; --! Flag, M�moire pleine
52 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
53 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
54 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
55 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
55 56 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
56 57 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
57 58 );
58 59 end ApbDriver;
59 60
61 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
60 62
61 63 architecture ar_ApbDriver of ApbDriver is
62 64
Show file before | Show file after | Hide comments
@@ -25,6 +25,7 use IEEE.numeric_std.all;
25 25 library techmap;
26 26 use techmap.gencomp.all;
27 27 use work.config.all;
28 use lpp.lpp_memory.all;
28 29
29 30 --! Programme de la FIFO
30 31
@@ -75,7 +76,7 signal s_flag_WR : std_logic;
75 76
76 77 begin
77 78
78 WR : entity work.Fifo_Write
79 WR : Fifo_Write
79 80 generic map(Addr_sz,addr_max_int)
80 81 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
81 82
@@ -85,11 +86,11 begin
85 86 port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
86 87
87 88
88 link : entity work.Link_Reg
89 link : Link_Reg
89 90 generic map(Data_sz)
90 91 port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
91 92
92 RE : entity work.Fifo_Read
93 RE : Fifo_Read
93 94 generic map(Addr_sz,addr_max_int)
94 95 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr);
95 96
Show file before | Show file after | Hide comments
@@ -39,7 +39,6 entity Top_FifoRead is
39 39 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
40 40 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
41 41 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
42 full : out std_logic; --! Flag, M�moire pleine
43 42 empty : out std_logic; --! Flag, M�moire vide
44 43 Raddr : out std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la m�moire
45 44 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
Show file before | Show file after | Hide comments
@@ -85,20 +85,20 end component;
85 85
86 86 component Top_FIFO is
87 87 generic(
88 Data_sz : integer := 16;
88 89 Addr_sz : integer := 8;
89 Data_sz : integer := 16;
90 addr_max_int : integer := 256);
90 addr_max_int : integer := 256
91 );
91 92 port(
92 clk : in std_logic;
93 raz : in std_logic;
94 Send_RE : in std_logic;
95 Send_WR : in std_logic;
96 Data_in : in std_logic_vector(Data_sz-1 downto 0);
97 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
98 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
99 full : out std_logic;
100 empty : out std_logic;
101 Data_out : out std_logic_vector(Data_sz-1 downto 0)
93 clk,raz : in std_logic; --! Horloge et reset general du composant
94 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
95 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
96 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
97 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
98 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
99 full : out std_logic; --! Flag, M�moire pleine
100 empty : out std_logic; --! Flag, M�moire vide
101 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
102 102 );
103 103 end component;
104 104
Show file before | Show file after | Hide comments
@@ -83,7 +83,7 Rec.UART_Cfg(1) <= Sended;
83 83 Rec.UART_Cfg(2) <= NwData;
84 84
85 85
86 COM0 : entity work.UART
86 COM0 : UART
87 87 generic map (Data_sz)
88 88 port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
89 89
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
General Comments 0
You need to be logged in to leave comments. Login now