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fixed bug on UART
martin -
r62:add206a96e71 default
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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19
20 include ../../rules.mk
21 LIBDIR = ../../lib
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
24 LIBS=-lapb_uart_Driver -llpp_apb_functions
25 INPUTFILE=main.c
26 EXEC=BenchUART.bin
27 OUTBINDIR=bin/
28
29
30 .PHONY:bin
31
32 all:bin
33 @echo $(EXEC)" file created"
34
35 clean:
36 rm -f *.{o,a}
37
38
39
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
44
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_UART_DRIVER_H
23 #define APB_UART_DRIVER_H
24
25
26 #define BaudGenOnDuty 0
27 #define DataSended 0x10
28 #define NewData 0x100
29
30 /*===================================================
31 T Y P E S D E F
32 ====================================================*/
33
34 struct UART_Driver
35 {
36 int ConfigReg;
37 int DataWReg;
38 int DataRReg;
39 };
40
41 typedef struct UART_Driver UART_Device;
42
43
44 /*===================================================
45 F U N C T I O N S
46 ====================================================*/
47
48
49 UART_Device* openUART(int count);
50 void uartputc(UART_Device* dev,char c);
51 void uartputs(UART_Device* dev,char* s);
52 char uartgetc(UART_Device* dev);
53 void uartgets(UART_Device* dev,char* s);
54
55
56 #endif
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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19 FILE = apb_uart_Driver
20 LIB = liblpp_uart_Driver.a
21
22 include ../../rules.mk
23
24 all: $(FILE).a
25 @echo $(FILE)".a created"
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FFT_config.all;
26
27 entity Flag_Extremum is
28 port(
29 clk,raz : in std_logic;
30 load : in std_logic;
31 y_rdy : in std_logic;
32 d_valid_WR : in std_logic;
33 read_y_RE : in std_logic;
34 full : out std_logic;
35 empty : out std_logic
36 );
37 end Flag_Extremum;
38
39 architecture ar_Flag_Extremum of Flag_Extremum is
40
41 type etat is (eA,eB,eC,eD,eX,e0,e1,e2,e3);
42 signal ect : etat;
43
44 signal load_reg : std_logic;
45 signal y_rdy_reg : std_logic;
46 signal RE_reg : std_logic;
47 signal WR_reg : std_logic;
48
49 begin
50 process (clk,raz)
51 begin
52 if(raz='0')then
53 full <= '0';
54 empty <= '1';
55 ect <= eA;
56
57 elsif(clk' event and clk='1')then
58 load_reg <= load;
59 y_rdy_reg <= y_rdy;
60 RE_reg <= read_y_RE;
61 WR_reg <= d_valid_WR;
62
63 case ect is
64
65 when eA =>
66 if(WR_reg='0' and d_valid_WR='1')then
67 empty <= '0';
68 ect <= eB;
69 end if;
70
71 when eB =>
72 if(load_reg='1' and load='0')then
73 ect <= eC;
74 end if;
75
76 when eC =>
77 if(load_reg='1' and load='0')then
78 full <= '1';
79 ect <= eD;
80 end if;
81
82 when eD =>
83 if(RE_reg='0' and read_y_RE='1')then
84 full <= '0';
85 ect <= eX;
86 end if;
87
88 when eX =>
89 empty <= '1';
90 ect <= e0;
91
92 when e0 =>
93 if(WR_reg='0' and d_valid_WR='1')then
94 empty <= '0';
95 ect <= e1;
96 end if;
97
98 when e1 =>
99 if(load_reg='1' and load='0')then
100 full <= '1';
101 ect <= e2;
102 end if;
103
104 when e2 =>
105 if(RE_reg='0' and read_y_RE='1')then
106 full <= '0';
107 ect <= e3;
108 end if;
109
110 when e3 =>
111 if(y_rdy_reg='1' and y_rdy='0')then
112 empty <= '1';
113 ect <= e0;
114 end if;
115
116 end case;
117 end if;
118 end process;
119
120 end ar_Flag_Extremum;
121
122
123
124
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1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 -----------------------------------------------------------------------------*/
22 22 #include "apb_uart_Driver.h"
23 23 #include "lpp_apb_functions.h"
24 24 #include <stdio.h>
25 25
26 26
27 27 UART_Device* openUART(int count)
28 28 {
29 29 UART_Device* uart0;
30 uart0 = (UART_Device*) apbgetdevice(LPP_UART_CTRLR,VENDOR_LPP,count);
30 uart0 = (UART_Device*) apbgetdevice(LPP_UART,VENDOR_LPP,count);
31 31 uart0->ConfigReg = BaudGenOnDuty;
32 32 return uart0;
33 33 }
34 34
35 35
36 36 void uartputc(UART_Device* dev,char c)
37 37 {
38 38 //while (!(dev->ConfigReg & (1<<5)));
39 39 while (!((dev->ConfigReg & DataSended) == DataSended));
40 40 dev->DataWReg = c;
41 41 printf(" ");
42 42 }
43 43
44 44 void uartputs(UART_Device* dev,char* s)
45 45 {
46 46 while (*s) uartputc(dev,*(s++));
47 47 }
48 48
49 49 char uartgetc(UART_Device* dev)
50 50 {
51 51 //while (!((dev->ConfigReg & (1<<2))));
52 52 while (!((dev->ConfigReg & NewData) == NewData));
53 53 return dev->DataRReg;
54 54 }
55 55
56 56 void uartgets(UART_Device* dev,char* s)
57 57 {
58 58 while (*s && (*s!=0xd)) *s++ = uartgetc(dev);
59 59 }
60 60
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_fft.all;
32 use lpp.lpp_memory.all;
32 33 use work.fft_components.all;
33 34
34 35 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
35 36
36 37 entity APB_FFT is
37 38 generic (
38 39 pindex : integer := 0;
39 40 paddr : integer := 0;
40 41 pmask : integer := 16#fff#;
41 42 pirq : integer := 0;
42 43 abits : integer := 8;
43 44 Data_sz : integer := 16;
44 45 Addr_sz : integer := 8;
45 46 addr_max_int : integer := 256);
46 47 port (
47 48 clk : in std_logic; --! Horloge du composant
48 49 rst : in std_logic; --! Reset general du composant
49 50 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
50 51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
51 52 );
52 53 end APB_FFT;
53 54
54 55
55 56 architecture ar_APB_FFT of APB_FFT is
56 57
57 58 signal ReadEnable : std_logic;
58 59 signal WriteEnable : std_logic;
59 60 signal FlagEmpty : std_logic;
60 61 signal FlagFull : std_logic;
61 62 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
62 63 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
63 64 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
64 65 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
65 66
66 signal X,Y,Z : std_logic;
67 --signal Pong : std_logic;
68 --signal Valid : std_logic;
67 signal start : std_logic;
68 signal load : std_logic;
69 signal rdy : std_logic;
69 70 signal DummyIn : std_logic_vector(Data_sz-1 downto 0);
70 --signal DummyOut : std_logic_vector(Data_sz-1 downto 0);
71
71 72
72 73 begin
73 74
74 APB : entity work.ApbDriver
75 APB : ApbDriver
75 76 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
76 77 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
77
78
78 79
79 DEVICE : entity work.CoreFFT
80 Extremum : Flag_Extremum
81 port map(clk,raz,load,rdy,WriteEnable,ReadEnable,FlagFull,FlagEmpty);
82
83
84 DEVICE : CoreFFT
80 85 generic map(
81 86 LOGPTS => gLOGPTS,
82 87 LOGLOGPTS => gLOGLOGPTS,
83 88 WSIZE => gWSIZE,
84 89 TWIDTH => gTWIDTH,
85 90 DWIDTH => gDWIDTH,
86 91 TDWIDTH => gTDWIDTH,
87 92 RND_MODE => gRND_MODE,
88 93 SCALE_MODE => gSCALE_MODE,
89 94 PTS => gPTS,
90 95 HALFPTS => gHALFPTS,
91 96 inBuf_RWDLY => gInBuf_RWDLY)
92 port map(clk,X,rst,WriteEnable,ReadEnable,DummyIn,DataIn,Y,open,open,DataOut,open,Z);
97 port map(clk,start,rst,WriteEnable,ReadEnable,DummyIn,DataIn,load,open,open,DataOut,open,rdy);
93 98
94 X <= not rst;
95 Y <= not FlagFull;
96 Z <= not FlagEmpty;
97 DummyIn <= (others => '0');
99 start <= not rst;
100 --FlagFull <= not load;
101 --FlagEmpty <= not rdy;
102 DummyIn <= (others => '0');
98 103
99 104 end ar_APB_FFT; No newline at end of file
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29 use lpp.lpp_memory.all;
30 30 use work.fft_components.all;
31 31
32 32
33 33 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
34 34
35 35 package lpp_fft is
36 36
37 37 component APB_FFT is
38 38 generic (
39 39 pindex : integer := 0;
40 40 paddr : integer := 0;
41 41 pmask : integer := 16#fff#;
42 42 pirq : integer := 0;
43 43 abits : integer := 8;
44 44 Data_sz : integer := 16;
45 45 Addr_sz : integer := 8;
46 46 addr_max_int : integer := 256);
47 47 port (
48 48 clk : in std_logic;
49 49 rst : in std_logic;
50 50 apbi : in apb_slv_in_type;
51 51 apbo : out apb_slv_out_type
52 52 );
53 53 end component;
54 54
55 55
56 component Flag_Extremum is
57 port(
58 clk,raz : in std_logic;
59 load : in std_logic;
60 y_rdy : in std_logic;
61 d_valid_WR : in std_logic;
62 read_y_RE : in std_logic;
63 full : out std_logic;
64 empty : out std_logic
65 );
66 end component;
67
68
56 69 component CoreFFT IS
57 70 GENERIC (
58 71 LOGPTS : integer := gLOGPTS;
59 72 LOGLOGPTS : integer := gLOGLOGPTS;
60 73 WSIZE : integer := gWSIZE;
61 74 TWIDTH : integer := gTWIDTH;
62 75 DWIDTH : integer := gDWIDTH;
63 76 TDWIDTH : integer := gTDWIDTH;
64 77 RND_MODE : integer := gRND_MODE;
65 78 SCALE_MODE : integer := gSCALE_MODE;
66 79 PTS : integer := gPTS;
67 80 HALFPTS : integer := gHALFPTS;
68 81 inBuf_RWDLY : integer := gInBuf_RWDLY );
69 82 PORT (
70 83 clk,ifiStart,ifiNreset : IN std_logic;
71 84 ifiD_valid, ifiRead_y : IN std_logic;
72 85 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
73 86 ifoLoad, ifoPong : OUT std_logic;
74 87 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
75 88 ifoY_valid, ifoY_rdy : OUT std_logic);
76 89 END component;
77 90
78 91
79 92 component actar is
80 93 port( DataA : in std_logic_vector(15 downto 0); DataB : in
81 94 std_logic_vector(15 downto 0); Mult : out
82 95 std_logic_vector(31 downto 0);Clock : in std_logic) ;
83 96 end component;
84 97
85 98 component actram is
86 99 port( DI : in std_logic_vector(31 downto 0); DO : out
87 100 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
88 101 WADDR : in std_logic_vector(6 downto 0); RADDR : in
89 102 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
90 103 std_logic) ;
91 104 end component;
92 105
93 106 component switch IS
94 107 GENERIC ( DWIDTH : integer := 32 );
95 108 PORT (
96 109 clk, sel, validIn : IN std_logic;
97 110 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
98 111 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
99 112 validOut : OUT std_logic);
100 113 END component;
101 114
102 115 component twid_rA IS
103 116 GENERIC (LOGPTS : integer := 8;
104 117 LOGLOGPTS : integer := 3 );
105 118 PORT (clk : IN std_logic;
106 119 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
107 120 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
108 121 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
109 122 END component;
110 123
111 124 component counter IS
112 125 GENERIC (
113 126 WIDTH : integer := 7;
114 127 TERMCOUNT : integer := 127 );
115 128 PORT (
116 129 clk, nGrst, rst, cntEn : IN std_logic;
117 130 tc : OUT std_logic;
118 131 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
119 132 END component;
120 133
121 134
122 135 component twiddle IS
123 136 PORT (
124 137 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
125 138 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
126 139 END component;
127 140
128 141
129 142 end; No newline at end of file
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_cna.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
34 34
35 35 entity APB_CNA is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8);
42 42 port (
43 43 clk : in std_logic; --! Horloge du composant
44 44 rst : in std_logic; --! Reset general du composant
45 45 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
46 46 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
47 47 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
48 48 SCLK : out std_logic; --! Horloge systeme du convertisseur
49 49 DATA : out std_logic --! Donn�e num�rique s�rialis�
50 50 );
51 51 end APB_CNA;
52 52
53 53 --! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
54 54 --! et les sorties seront cabl�es vers le convertisseur.
55 55
56 56 architecture ar_APB_CNA of APB_CNA is
57 57
58 58 constant REVISION : integer := 1;
59 59
60 60 constant pconfig : apb_config_type := (
61 61 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
62 62 1 => apb_iobar(paddr, pmask));
63 63
64 64 signal enable : std_logic;
65 65 signal flag_sd : std_logic;
66 66
67 67 type CNA_ctrlr_Reg is record
68 68 CNA_Cfg : std_logic_vector(1 downto 0);
69 69 CNA_Data : std_logic_vector(15 downto 0);
70 70 end record;
71 71
72 72 signal Rec : CNA_ctrlr_Reg;
73 73 signal Rdata : std_logic_vector(31 downto 0);
74 74
75 75 begin
76 76
77 77 enable <= Rec.CNA_Cfg(0);
78 78 Rec.CNA_Cfg(1) <= flag_sd;
79 79
80 CONVERTER : entity Work.CNA_TabloC
80 CONVERTER : CNA_TabloC
81 81 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
82 82
83 83
84 84 process(rst,clk)
85 85 begin
86 86 if(rst='0')then
87 87 Rec.CNA_Data <= (others => '0');
88 88
89 89 elsif(clk'event and clk='1')then
90 90
91 91
92 92 --APB Write OP
93 93 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
94 94 case apbi.paddr(abits-1 downto 2) is
95 95 when "000000" =>
96 96 Rec.CNA_Cfg(0) <= apbi.pwdata(0);
97 97 when "000001" =>
98 98 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
99 99 when others =>
100 100 null;
101 101 end case;
102 102 end if;
103 103
104 104 --APB READ OP
105 105 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
106 106 case apbi.paddr(abits-1 downto 2) is
107 107 when "000000" =>
108 108 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
109 109 Rdata(1 downto 0) <= Rec.CNA_Cfg;
110 110 when "000001" =>
111 111 Rdata(31 downto 16) <= X"FD18";
112 112 Rdata(15 downto 0) <= Rec.CNA_Data;
113 113 when others =>
114 114 Rdata <= (others => '0');
115 115 end case;
116 116 end if;
117 117
118 118 end if;
119 119 apbo.pconfig <= pconfig;
120 120 end process;
121 121
122 122 apbo.prdata <= Rdata when apbi.penable = '1';
123 123 end ar_APB_CNA;
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@@ -1,77 +1,77
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
31 use lpp.lpp_memory.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34 34
35 35 entity APB_FIFO is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8;
42 42 Data_sz : integer := 16;
43 43 Addr_sz : integer := 8;
44 44 addr_max_int : integer := 256);
45 45 port (
46 46 clk : in std_logic; --! Horloge du composant
47 47 rst : in std_logic; --! Reset general du composant
48 48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 49 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
50 50 );
51 51 end APB_FIFO;
52 52
53 53
54 54 architecture ar_APB_FIFO of APB_FIFO is
55 55
56 56 signal ReadEnable : std_logic;
57 57 signal WriteEnable : std_logic;
58 58 signal FlagEmpty : std_logic;
59 59 signal FlagFull : std_logic;
60 60 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
61 61 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
62 62 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
63 63 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
64 64
65 65 begin
66 66
67 APB : entity work.ApbDriver
67 APB : ApbDriver
68 68 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
69 69 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
70 70
71 71
72 DEVICE : entity work.Top_FIFO
72 DEVICE : Top_FIFO
73 73 generic map(Data_sz,Addr_sz,addr_max_int)
74 74 port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
75 75
76 76
77 77 end ar_APB_FIFO; No newline at end of file
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@@ -1,127 +1,80
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_fifo.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34 34
35 35 entity APB_FifoRead is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8;
42 42 Data_sz : integer := 16;
43 43 Addr_sz : integer := 8;
44 44 addr_max_int : integer := 256);
45 45 port (
46 46 clk : in std_logic; --! Horloge du composant
47 47 rst : in std_logic; --! Reset general du composant
48 48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 49 Flag_WR : in std_logic; --! Demande l'�criture dans la m�moire, g�r� hors de l'IP
50 50 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
51 51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 52 );
53 53 end APB_FifoRead;
54 54
55 --! @details Gestion de la FIFO uniquement en �criture
55 56
56 57 architecture ar_APB_FifoRead of APB_FifoRead is
57 58
58 constant REVISION : integer := 1;
59
60 constant pconfig : apb_config_type := (
61 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0),
62 1 => apb_iobar(paddr, pmask));
63
64 type FIFO_ctrlr_Reg is record
65 FIFO_Cfg : std_logic_vector(1 downto 0);
66 FIFO_DataW : std_logic_vector(15 downto 0);
67 FIFO_DataR : std_logic_vector(15 downto 0);
68 FIFO_AddrR : std_logic_vector(7 downto 0);
69 end record;
70
71 signal Rec : FIFO_ctrlr_Reg;
72 signal Rdata : std_logic_vector(31 downto 0);
73
74 signal flag_RE : std_logic;
75 signal empty : std_logic;
59 signal ReadEnable : std_logic;
60 --signal WriteEnable : std_logic;
61 signal FlagEmpty : std_logic;
62 --signal FlagFull : std_logic;
63 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
64 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
65 --signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
66 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
76 67
77 68 begin
78 69
79 Rec.FIFO_Cfg(0) <= flag_RE;
80 Rec.FIFO_Cfg(2) <= empty;
81
82
83 MEMORY_READ : entity Work.Top_FifoRead
84 generic map(Data_sz,Addr_sz,addr_max_int)
85 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,Rec.FIFO_AddrR,full,Waddr,Rec.FIFO_DataR);
70 APB : ApbDriver
71 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
72 port map(clk,rst,ReadEnable,open,FlagEmpty,open,DataIn,DataOut,open,AddrOut,apbi,apbo);
86 73
87 74
88 process(rst,clk)
89 begin
90 if(rst='0')then
91 Rec.FIFO_AddrR <= (others => '0');
92
93 elsif(clk'event and clk='1')then
94
95 --APB Write OP
96 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
97 case apbi.paddr(abits-1 downto 2) is
98 when others =>
99 null;
100 end case;
101 end if;
75 MEMORY_READ : Top_FifoRead
76 generic map(Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,ReadEnable,flag_WR,DataIn,Waddr,FlagEmpty,AddrOut,DataOut);
102 78
103 --APB Read OP
104 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
105 case apbi.paddr(abits-1 downto 2) is
106 when "000000" =>
107 Rdata(31 downto 16) <= X"DDDD";
108 Rdata(15 downto 0) <= Rec.FIFO_DataR;
109 when "000001" =>
110 Rdata(31 downto 8) <= X"AAAAAA";
111 Rdata(7 downto 0) <= Rec.FIFO_AddrR;
112 when "000010" =>
113 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
114 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
115 Rdata(31 downto 8) <= X"CCCCCC";
116 when others =>
117 Rdata <= (others => '0');
118 end case;
119 end if;
120
121 end if;
122 apbo.pconfig <= pconfig;
123 end process;
124
125 apbo.prdata <= Rdata when apbi.penable = '1';
126 79
127 80 end ar_APB_FifoReade; No newline at end of file
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@@ -1,131 +1,80
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_fifo.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34 34
35 35 entity APB_FifoWrite is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8;
42 42 Data_sz : integer := 16;
43 43 Addr_sz : integer := 8;
44 44 addr_max_int : integer := 256);
45 45 port (
46 46 clk : in std_logic; --! Horloge du composant
47 47 rst : in std_logic; --! Reset general du composant
48 48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 49 Flag_RE : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
50 50 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture dans la m�moire
51 51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 52 );
53 53 end APB_FifoWrite;
54 54
55 --! @details Gestion de la FIFO uniquement en lecture
55 56
56 57 architecture ar_APB_FifoWrite of APB_FifoWrite is
57 58
58 constant REVISION : integer := 1;
59
60 constant pconfig : apb_config_type := (
61 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0),
62 1 => apb_iobar(paddr, pmask));
63
64 type FIFO_ctrlr_Reg is record
65 FIFO_Cfg : std_logic_vector(1 downto 0);
66 FIFO_DataW : std_logic_vector(15 downto 0);
67 FIFO_DataR : std_logic_vector(15 downto 0);
68 FIFO_AddrW : std_logic_vector(7 downto 0);
69 end record;
70
71 signal Rec : FIFO_ctrlr_Reg;
72 signal Rdata : std_logic_vector(31 downto 0);
73
74 signal flag_WR : std_logic;
75 signal full : std_logic;
59 --signal ReadEnable : std_logic;
60 signal WriteEnable : std_logic;
61 --signal FlagEmpty : std_logic;
62 signal FlagFull : std_logic;
63 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
64 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
65 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
66 --signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
76 67
77 68 begin
78 69
79 Rec.FIFO_Cfg(0) <= flag_WR;
80 Rec.FIFO_Cfg(1) <= full;
81
82 MEMORY_WRITE : entity Work.Top_FifoWrite
83 generic map(Data_sz,Addr_sz,addr_max_int)
84 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,Raddr,full,Rec.FIFO_AddrW,Rec.FIFO_DataR);
70 APB : ApbDriver
71 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
72 port map(clk,rst,open,WriteEnable,open,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
85 73
86 74
87 process(rst,clk)
88 begin
89 if(rst='0')then
90 Rec.FIFO_DataW <= (others => '0');
91
92 elsif(clk'event and clk='1')then
93
94 --APB Write OP
95 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
96 case apbi.paddr(abits-1 downto 2) is
97 when "000000" =>
98 flag_WR <= '1';
99 Rec.FIFO_DataW <= apbi.pwdata(15 downto 0);
100 when others =>
101 null;
102 end case;
103 else
104 flag_WR <= '0';
105 end if;
75 MEMORY_WRITE : Top_FifoWrite
76 generic map(Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,flag_RE,WriteEnable,DataIn,Raddr,FlagFull,AddrIn,DataOut);
106 78
107 --APB Read OP
108 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
109 case apbi.paddr(abits-1 downto 2) is
110 when "000000" =>
111 Rdata(31 downto 16) <= X"DDDD";
112 Rdata(15 downto 0) <= Rec.FIFO_DataR;
113 when "000001" =>
114 Rdata(31 downto 8) <= X"AAAAAA";
115 Rdata(7 downto 0) <= Rec.FIFO_AddrW;
116 when "000010" =>
117 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
118 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
119 Rdata(31 downto 8) <= X"CCCCCC";
120 when others =>
121 Rdata <= (others => '0');
122 end case;
123 end if;
124
125 end if;
126 apbo.pconfig <= pconfig;
127 end process;
128
129 apbo.prdata <= Rdata when apbi.penable = '1';
130 79
131 80 end ar_APB_FifoWrite; No newline at end of file
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@@ -1,152 +1,154
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31
32 --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO
32 33
33 34 entity ApbDriver is
34 35 generic (
35 36 pindex : integer := 0;
36 37 paddr : integer := 0;
37 38 pmask : integer := 16#fff#;
38 39 pirq : integer := 0;
39 40 abits : integer := 8;
40 41 LPP_DEVICE : integer;
41 42 Data_sz : integer := 16;
42 43 Addr_sz : integer := 8;
43 44 addr_max_int : integer := 256);
44 45 port (
45 clk : in std_logic; --! Horloge du composant
46 rst : in std_logic; --! Reset general du composant
47 ReadEnable : out std_logic;
48 WriteEnable : out std_logic;
49 FlagEmpty : in std_logic;
50 FlagFull : in std_logic;
51 DataIn : out std_logic_vector(Data_sz-1 downto 0);
52 DataOut : in std_logic_vector(Data_sz-1 downto 0);
53 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
54 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
55 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
56 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
50 FlagEmpty : in std_logic; --! Flag, M�moire vide
51 FlagFull : in std_logic; --! Flag, M�moire pleine
52 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
53 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
54 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
55 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
56 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
57 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
57 58 );
58 59 end ApbDriver;
59 60
61 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
60 62
61 63 architecture ar_ApbDriver of ApbDriver is
62 64
63 65 constant REVISION : integer := 1;
64 66
65 67 constant pconfig : apb_config_type := (
66 68 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
67 69 1 => apb_iobar(paddr, pmask));
68 70
69 71 type DEVICE_ctrlr_Reg is record
70 72 DEVICE_Cfg : std_logic_vector(3 downto 0);
71 73 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
72 74 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
73 75 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
74 76 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
75 77 end record;
76 78
77 79 signal Rec : DEVICE_ctrlr_Reg;
78 80 signal Rdata : std_logic_vector(31 downto 0);
79 81
80 82 signal FlagRE : std_logic;
81 83 signal FlagWR : std_logic;
82 84 begin
83 85
84 86 Rec.DEVICE_Cfg(0) <= FlagRE;
85 87 Rec.DEVICE_Cfg(1) <= FlagWR;
86 88 Rec.DEVICE_Cfg(2) <= FlagEmpty;
87 89 Rec.DEVICE_Cfg(3) <= FlagFull;
88 90
89 91 DataIn <= Rec.DEVICE_DataW;
90 92 Rec.DEVICE_DataR <= DataOut;
91 93 Rec.DEVICE_AddrW <= AddrIn;
92 94 Rec.DEVICE_AddrR <= AddrOut;
93 95
94 96
95 97
96 98 process(rst,clk)
97 99 begin
98 100 if(rst='0')then
99 101 Rec.DEVICE_DataW <= (others => '0');
100 102 FlagWR <= '0';
101 103 FlagRE <= '0';
102 104
103 105 elsif(clk'event and clk='1')then
104 106
105 107 --APB Write OP
106 108 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
107 109 case apbi.paddr(abits-1 downto 2) is
108 110 when "000000" =>
109 111 FlagWR <= '1';
110 112 Rec.DEVICE_DataW <= apbi.pwdata(15 downto 0);
111 113 when others =>
112 114 null;
113 115 end case;
114 116 else
115 117 FlagWR <= '0';
116 118 end if;
117 119
118 120 --APB Read OP
119 121 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
120 122 case apbi.paddr(abits-1 downto 2) is
121 123 when "000000" =>
122 124 FlagRE <= '1';
123 125 Rdata(31 downto 16) <= X"DDDD";
124 126 Rdata(15 downto 0) <= Rec.DEVICE_DataR;
125 127 when "000001" =>
126 128 Rdata(31 downto 8) <= X"AAAAAA";
127 129 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
128 130 when "000101" =>
129 131 Rdata(31 downto 8) <= X"AAAAAA";
130 132 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
131 133 when "000010" =>
132 134 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
133 135 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
134 136 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
135 137 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
136 138 Rdata(31 downto 16) <= X"CCCC";
137 139 when others =>
138 140 Rdata <= (others => '0');
139 141 end case;
140 142 else
141 143 FlagRE <= '0';
142 144 end if;
143 145
144 146 end if;
145 147 apbo.pconfig <= pconfig;
146 148 end process;
147 149
148 150 apbo.prdata <= Rdata when apbi.penable = '1';
149 151 WriteEnable <= FlagWR;
150 152 ReadEnable <= FlagRE;
151 153
152 154 end ar_ApbDriver; No newline at end of file
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@@ -1,123 +1,124
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 library techmap;
26 26 use techmap.gencomp.all;
27 27 use work.config.all;
28 use lpp.lpp_memory.all;
28 29
29 30 --! Programme de la FIFO
30 31
31 32 entity Top_FIFO is
32 33 generic(
33 34 Data_sz : integer := 16;
34 35 Addr_sz : integer := 8;
35 36 addr_max_int : integer := 256
36 37 );
37 38 port(
38 39 clk,raz : in std_logic; --! Horloge et reset general du composant
39 40 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
40 41 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
41 42 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
42 43 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
43 44 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
44 45 full : out std_logic; --! Flag, M�moire pleine
45 46 empty : out std_logic; --! Flag, M�moire vide
46 47 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
47 48 );
48 49 end Top_FIFO;
49 50
50 51 --! @details Une m�moire SRAM de chez Gaisler est utilis�e,
51 52 --! associ�e a deux Drivers, un pour �crire l'autre pour lire cette m�moire
52 53
53 54 architecture ar_Top_FIFO of Top_FIFO is
54 55
55 56 component syncram_2p
56 57 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
57 58 port (
58 59 rclk : in std_ulogic;
59 60 renable : in std_ulogic;
60 61 raddress : in std_logic_vector((abits -1) downto 0);
61 62 dataout : out std_logic_vector((dbits -1) downto 0);
62 63 wclk : in std_ulogic;
63 64 write : in std_ulogic;
64 65 waddress : in std_logic_vector((abits -1) downto 0);
65 66 datain : in std_logic_vector((dbits -1) downto 0));
66 67 end component;
67 68
68 69 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
69 70 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
70 71 signal Data_int : std_logic_vector(Data_sz-1 downto 0);
71 72 signal s_empty : std_logic;
72 73 signal s_full : std_logic;
73 74 signal s_flag_RE : std_logic;
74 75 signal s_flag_WR : std_logic;
75 76
76 77 begin
77 78
78 WR : entity work.Fifo_Write
79 WR : Fifo_Write
79 80 generic map(Addr_sz,addr_max_int)
80 81 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
81 82
82 83
83 84 SRAM : syncram_2p
84 85 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
85 86 port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
86 87
87 88
88 link : entity work.Link_Reg
89 link : Link_Reg
89 90 generic map(Data_sz)
90 91 port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
91 92
92 RE : entity work.Fifo_Read
93 RE : Fifo_Read
93 94 generic map(Addr_sz,addr_max_int)
94 95 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr);
95 96
96 97 process(clk,raz)
97 98 begin
98 99 if(raz='0')then
99 100 s_flag_RE <= '0';
100 101 s_flag_WR <= '0';
101 102
102 103 elsif(clk'event and clk='1')then
103 104 if(s_full='0')then
104 105 s_flag_WR <= Flag_WR;
105 106 else
106 107 s_flag_WR <= '0';
107 108 end if;
108 109
109 110 if(s_empty='0')then
110 111 s_flag_RE <= Flag_RE;
111 112 else
112 113 s_flag_RE <= '0';
113 114 end if;
114 115
115 116 end if;
116 117 end process;
117 118
118 119 full <= s_full;
119 120 empty <= s_empty;
120 121 Addr_RE <= Raddr;
121 122 Addr_WR <= Waddr;
122 123
123 124 end ar_Top_FIFO; No newline at end of file
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@@ -1,104 +1,103
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 library techmap;
26 26 use techmap.gencomp.all;
27 27 use work.config.all;
28 28
29 29 --! Programme de la FIFO
30 30
31 31 entity Top_FifoRead is
32 32 generic(
33 33 Data_sz : integer := 16;
34 34 Addr_sz : integer := 8;
35 35 addr_max_int : integer := 256);
36 36 port(
37 37 clk,raz : in std_logic; --! Horloge et reset general du composant
38 38 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
39 39 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
40 40 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
41 41 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
42 full : out std_logic; --! Flag, M�moire pleine
43 42 empty : out std_logic; --! Flag, M�moire vide
44 43 Raddr : out std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la m�moire
45 44 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
46 45 );
47 46 end Top_FifoRead;
48 47
49 48 --! @details Une m�moire SRAM de chez Gaisler est utilis�e,
50 49 --! associ�e a une fifo, utilis� pour la lecture
51 50
52 51 architecture ar_Top_FifoRead of Top_FifoRead is
53 52
54 53 component syncram_2p
55 54 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
56 55 port (
57 56 rclk : in std_ulogic;
58 57 renable : in std_ulogic;
59 58 raddress : in std_logic_vector((abits -1) downto 0);
60 59 dataout : out std_logic_vector((dbits -1) downto 0);
61 60 wclk : in std_ulogic;
62 61 write : in std_ulogic;
63 62 waddress : in std_logic_vector((abits -1) downto 0);
64 63 datain : in std_logic_vector((dbits -1) downto 0));
65 64 end component;
66 65
67 66 signal Raddr_int : std_logic_vector(addr_sz-1 downto 0);
68 67 signal s_flag_RE : std_logic;
69 68 signal s_empty : std_logic;
70 69
71 70 begin
72 71
73 72 SRAM : syncram_2p
74 73 generic map(CFG_MEMTECH,addr_sz,Data_sz)
75 74 port map(clk,s_flag_RE,Waddr,Data_int,clk,flag_WR,Raddr_int,Data_in);
76 75
77 76
78 77 RE : entity work.Fifo_Read
79 78 generic map(Addr_sz,addr_max_int)
80 79 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr_int);
81 80
82 81 link : entity work.Link_Reg
83 82 generic map(Data_sz)
84 83 port map(clk,raz,Data_in,Data_int,s_flag_RE,flag_WR,s_empty,Data_out);
85 84
86 85 process(clk,raz)
87 86 begin
88 87 if(raz='0')then
89 88 s_flag_RE <= '0';
90 89
91 90 elsif(clk'event and clk='1')then
92 91 if(s_empty='0')then
93 92 s_flag_RE <= Flag_RE;
94 93 else
95 94 s_flag_RE <= '0';
96 95 end if;
97 96
98 97 end if;
99 98 end process;
100 99
101 100 empty <= s_empty;
102 101 Raddr <= Raddr_int;
103 102
104 103 end ar_Top_FifoRead; No newline at end of file
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@@ -1,233 +1,233
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 30
31 31 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32 32
33 33 package lpp_memory is
34 34
35 35 --===========================================================|
36 36 --================= FIFOW SRAM FIFOR ========================|
37 37 --===========================================================|
38 38
39 39 component APB_FIFO is
40 40 generic (
41 41 pindex : integer := 0;
42 42 paddr : integer := 0;
43 43 pmask : integer := 16#fff#;
44 44 pirq : integer := 0;
45 45 abits : integer := 8;
46 46 Data_sz : integer := 16;
47 47 Addr_sz : integer := 8;
48 48 addr_max_int : integer := 256);
49 49 port (
50 50 clk : in std_logic;
51 51 rst : in std_logic;
52 52 apbi : in apb_slv_in_type;
53 53 apbo : out apb_slv_out_type
54 54 );
55 55 end component;
56 56
57 57
58 58 component ApbDriver is
59 59 generic (
60 60 pindex : integer := 0;
61 61 paddr : integer := 0;
62 62 pmask : integer := 16#fff#;
63 63 pirq : integer := 0;
64 64 abits : integer := 8;
65 65 LPP_DEVICE : integer;
66 66 Data_sz : integer := 16;
67 67 Addr_sz : integer := 8;
68 68 addr_max_int : integer := 256);
69 69 port (
70 70 clk : in std_logic;
71 71 rst : in std_logic;
72 72 ReadEnable : in std_logic;
73 73 WriteEnable : in std_logic;
74 74 FlagEmpty : in std_logic;
75 75 FlagFull : in std_logic;
76 76 DataIn : out std_logic_vector(Data_sz-1 downto 0);
77 77 DataOut : in std_logic_vector(Data_sz-1 downto 0);
78 78 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
79 79 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
80 80 apbi : in apb_slv_in_type;
81 81 apbo : out apb_slv_out_type
82 82 );
83 83 end component;
84 84
85 85
86 86 component Top_FIFO is
87 87 generic(
88 Addr_sz : integer := 8;
89 88 Data_sz : integer := 16;
90 addr_max_int : integer := 256);
89 Addr_sz : integer := 8;
90 addr_max_int : integer := 256
91 );
91 92 port(
92 clk : in std_logic;
93 raz : in std_logic;
94 Send_RE : in std_logic;
95 Send_WR : in std_logic;
96 Data_in : in std_logic_vector(Data_sz-1 downto 0);
97 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
98 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
99 full : out std_logic;
100 empty : out std_logic;
101 Data_out : out std_logic_vector(Data_sz-1 downto 0)
93 clk,raz : in std_logic; --! Horloge et reset general du composant
94 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
95 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
96 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
97 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
98 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
99 full : out std_logic; --! Flag, M�moire pleine
100 empty : out std_logic; --! Flag, M�moire vide
101 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
102 102 );
103 103 end component;
104 104
105 105
106 106 component Fifo_Read is
107 107 generic(
108 108 Addr_sz : integer := 8;
109 109 addr_max_int : integer := 256);
110 110 port(
111 111 clk : in std_logic;
112 112 raz : in std_logic;
113 113 flag_RE : in std_logic;
114 114 Waddr : in std_logic_vector(addr_sz-1 downto 0);
115 115 empty : out std_logic;
116 116 Raddr : out std_logic_vector(addr_sz-1 downto 0)
117 117 );
118 118 end component;
119 119
120 120
121 121 component Fifo_Write is
122 122 generic(
123 123 Addr_sz : integer := 8;
124 124 addr_max_int : integer := 256);
125 125 port(
126 126 clk : in std_logic;
127 127 raz : in std_logic;
128 128 flag_WR : in std_logic;
129 129 Raddr : in std_logic_vector(addr_sz-1 downto 0);
130 130 full : out std_logic;
131 131 Waddr : out std_logic_vector(addr_sz-1 downto 0)
132 132 );
133 133 end component;
134 134
135 135
136 136 component Link_Reg is
137 137 generic(Data_sz : integer := 16);
138 138 port(
139 139 clk,raz : in std_logic;
140 140 Data_one : in std_logic_vector(Data_sz-1 downto 0);
141 141 Data_two : in std_logic_vector(Data_sz-1 downto 0);
142 142 flag_RE : in std_logic;
143 143 flag_WR : in std_logic;
144 144 empty : in std_logic;
145 145 Data_out : out std_logic_vector(Data_sz-1 downto 0)
146 146 );
147 147 end component;
148 148
149 149 --===========================================================|
150 150 --===================== FIFOW SRAM ==========================|
151 151 --===========================================================|
152 152
153 153 component APB_FifoWrite is
154 154 generic (
155 155 pindex : integer := 0;
156 156 paddr : integer := 0;
157 157 pmask : integer := 16#fff#;
158 158 pirq : integer := 0;
159 159 abits : integer := 8;
160 160 Data_sz : integer := 16;
161 161 Addr_sz : integer := 8;
162 162 addr_max_int : integer := 256);
163 163 port (
164 164 clk : in std_logic;
165 165 rst : in std_logic;
166 166 apbi : in apb_slv_in_type;
167 167 apbo : out apb_slv_out_type
168 168 );
169 169 end component;
170 170
171 171
172 172 component Top_FifoWrite is
173 173 generic(
174 174 Data_sz : integer := 16;
175 175 Addr_sz : integer := 8;
176 176 addr_max_int : integer := 256);
177 177 port(
178 178 clk : in std_logic;
179 179 raz : in std_logic;
180 180 flag_RE : in std_logic;
181 181 flag_WR : in std_logic;
182 182 Data_in : in std_logic_vector(Data_sz-1 downto 0);
183 183 Raddr : in std_logic_vector(addr_sz-1 downto 0);
184 184 full : out std_logic;
185 185 empty : out std_logic;
186 186 Waddr : out std_logic_vector(addr_sz-1 downto 0);
187 187 Data_out : out std_logic_vector(Data_sz-1 downto 0)
188 188 );
189 189 end component;
190 190
191 191 --===========================================================|
192 192 --===================== SRAM FIFOR ==========================|
193 193 --===========================================================|
194 194
195 195 component APB_FifoRead is
196 196 generic (
197 197 pindex : integer := 0;
198 198 paddr : integer := 0;
199 199 pmask : integer := 16#fff#;
200 200 pirq : integer := 0;
201 201 abits : integer := 8;
202 202 Data_sz : integer := 16;
203 203 Addr_sz : integer := 8;
204 204 addr_max_int : integer := 256);
205 205 port (
206 206 clk : in std_logic;
207 207 rst : in std_logic;
208 208 apbi : in apb_slv_in_type;
209 209 apbo : out apb_slv_out_type
210 210 );
211 211 end component;
212 212
213 213
214 214 component Top_FifoRead is
215 215 generic(
216 216 Data_sz : integer := 16;
217 217 Addr_sz : integer := 8;
218 218 addr_max_int : integer := 256);
219 219 port(
220 220 clk : in std_logic;
221 221 raz : in std_logic;
222 222 flag_RE : in std_logic;
223 223 flag_WR : in std_logic;
224 224 Data_in : in std_logic_vector(Data_sz-1 downto 0);
225 225 Waddr : in std_logic_vector(addr_sz-1 downto 0);
226 226 full : out std_logic;
227 227 empty : out std_logic;
228 228 Raddr : out std_logic_vector(addr_sz-1 downto 0);
229 229 Data_out : out std_logic_vector(Data_sz-1 downto 0)
230 230 );
231 231 end component;
232 232
233 233 end;
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@@ -1,146 +1,146
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_uart.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL de l'UART et le bus Amba
34 34
35 35 entity APB_UART is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8;
42 42 Data_sz : integer := 8);
43 43 port (
44 44 clk : in std_logic; --! Horloge du composant
45 45 rst : in std_logic; --! Reset general du composant
46 46 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
47 47 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
48 48 TXD : out std_logic; --! Transmission s�rie, c�t� composant
49 49 RXD : in std_logic --! Reception s�rie, c�t� composant
50 50 );
51 51 end APB_UART;
52 52
53 53
54 54 architecture ar_APB_UART of APB_UART is
55 55
56 56 constant REVISION : integer := 1;
57 57
58 58 constant pconfig : apb_config_type := (
59 59 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0),
60 60 1 => apb_iobar(paddr, pmask));
61 61
62 62 signal NwData : std_logic;
63 63 signal ACK : std_logic;
64 64 signal Capture : std_logic;
65 65 signal Send : std_logic;
66 66 signal Sended : std_logic;
67 67
68 68 type UART_ctrlr_Reg is record
69 69 UART_Cfg : std_logic_vector(2 downto 0);
70 70 UART_Wdata : std_logic_vector(7 downto 0);
71 71 UART_Rdata : std_logic_vector(7 downto 0);
72 72 UART_BTrig : std_logic_vector(11 downto 0);
73 73 end record;
74 74
75 75 signal Rec : UART_ctrlr_Reg;
76 76 signal Rdata : std_logic_vector(31 downto 0);
77 77 signal temp_ND : std_logic;
78 78
79 79 begin
80 80
81 81 Capture <= Rec.UART_Cfg(0);
82 82 Rec.UART_Cfg(1) <= Sended;
83 83 Rec.UART_Cfg(2) <= NwData;
84 84
85 85
86 COM0 : entity work.UART
86 COM0 : UART
87 87 generic map (Data_sz)
88 88 port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
89 89
90 90
91 91 process(rst,clk)
92 92 begin
93 93 if(rst='0')then
94 94 Rec.UART_Wdata <= (others => '0');
95 95
96 96
97 97 elsif(clk'event and clk='1')then
98 98 temp_ND <= NwData;
99 99 if(NwData='1' and temp_ND='1')then
100 100 ACK <= '1';
101 101 else
102 102 ACK <= '0';
103 103 end if;
104 104
105 105 --APB Write OP
106 106 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
107 107 case apbi.paddr(7 downto 2) is
108 108 when "000000" =>
109 109 Rec.UART_Cfg(0) <= apbi.pwdata(0);
110 110 when "000001" =>
111 111 Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0);
112 112 Send <= '1';
113 113 when others =>
114 114 null;
115 115 end case;
116 116 else
117 117 Send <= '0';
118 118 end if;
119 119
120 120 --APB READ OP
121 121 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
122 122 case apbi.paddr(7 downto 2) is
123 123 when "000000" =>
124 124 Rdata(3 downto 0) <= "000" & Rec.UART_Cfg(0);
125 125 Rdata(7 downto 4) <= "000" & Rec.UART_Cfg(1);
126 126 Rdata(11 downto 8) <= "000" & Rec.UART_Cfg(2);
127 127 Rdata(19 downto 12) <= X"EE";
128 128 Rdata(31 downto 20) <= Rec.UART_BTrig;
129 129 when "000001" =>
130 130 Rdata(31 downto 8) <= X"EEEEEE";
131 131 Rdata(7 downto 0) <= Rec.UART_Wdata;
132 132 when "000010" =>
133 133 Rdata(31 downto 8) <= X"EEEEEE";
134 134 Rdata(7 downto 0) <= Rec.UART_Rdata;
135 135 when others =>
136 136 Rdata <= (others => '0');
137 137 end case;
138 138 end if;
139 139
140 140 end if;
141 141 apbo.pconfig <= pconfig;
142 142 end process;
143 143
144 144 apbo.prdata <= Rdata when apbi.penable = '1';
145 145
146 146 end ar_APB_UART;
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