HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r643:a691a9e23336

Moved sig_reader to lpp.lpp_sim_pkg.

Jeandet Alexis -

r643:a691a9e23336 default

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r643:a691a9e23336

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lib/lpp/lpp_sim/sig_reader.vhd created 644 +53 0

@@ -0,0 +1,53
	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;
	3	USE ieee.numeric_std.ALL;
	4
	5	LIBRARY std;
	6	USE std.textio.ALL;
	7
	8	LIBRARY lpp;
	9	USE lpp.data_type_pkg.ALL;
	10
	11	ENTITY sig_reader IS
	12	GENERIC(
	13	FNAME : STRING := "input.txt";
	14	WIDTH : INTEGER := 1;
	15	RESOLUTION : INTEGER := 8;
	16	GAIN : REAL := 1.0
	17	);
	18	PORT(
	19	clk : IN std_logic;
	20	end_of_simu : out std_logic;
	21	out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
	22	);
	23	END sig_reader;
	24
	25	ARCHITECTURE beh OF sig_reader IS
	26	FILE input_file : TEXT OPEN read_mode IS FNAME;
	27	SIGNAL out_signal_reg : sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0):=(others=>(others=>'0'));
	28	SIGNAL end_of_simu_reg : std_logic:='0';
	29	BEGIN
	30	out_signal <= out_signal_reg;
	31	end_of_simu <= end_of_simu_reg;
	32	PROCESS
	33	VARIABLE line_var : LINE;
	34	VARIABLE value : INTEGER;
	35	VARIABLE cell : STD_LOGIC_VECTOR(RESOLUTION-1 downto 0);
	36	BEGIN
	37	WAIT UNTIL clk = '1';
	38	IF endfile(input_file) THEN
	39	end_of_simu_reg <= '1';
	40	ELSE
	41	end_of_simu_reg <= '0';
	42	readline(input_file,line_var);
	43	FOR COL IN 0 TO WIDTH-1 LOOP
	44	read(line_var, value);
	45	cell := std_logic_vector(to_signed(INTEGER(GAIN*REAL(value)) , RESOLUTION));
	46	FOR bit_idx IN RESOLUTION-1 downto 0 LOOP
	47	out_signal_reg(COL,bit_idx) <= cell(bit_idx);
	48	END LOOP;
	49	END LOOP;
	50	END IF;
	51	END PROCESS;
	52
	53	END beh;

designs/Validation_IIR_f0_LFR/Makefile +4 -4

             XSTOPT=
             SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
             #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
-            VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd sig_reader.vhd
+            VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
-            VHDLSIMFILES= tb.vhd sig_reader.vhd
+            VHDLSIMFILES= tb.vhd
             SIMTOP=testbench
             #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
             PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
             	./general_purpose/lpp_delay \
             	./lpp_bootloader \
             	./lfr_management \
-            	./lpp_sim \
             	./lpp_sim/CY7C1061DV33 \
             	./lpp_cna \
             	./lpp_uart \
                     lpp_lfr_ms_FFT.vhd \
             	lpp_lfr_apbreg.vhd \
             	CoreFFT.vhd \
-            	lpp_lfr_ms.vhd
+            	lpp_lfr_ms.vhd \
+            	lpp_lfr_sim_pkg.vhd
             include $(GRLIB)/bin/Makefile
             include $(GRLIB)/software/leon3/Makefile

designs/Validation_IIR_f0_LFR/tb.vhd +14 -13

             USE lpp.data_type_pkg.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
+            USE lpp.lpp_sim_pkg.ALL;
             ENTITY testbench IS
             GENERIC(
                   );
               END COMPONENT;
-              COMPONENT sig_reader IS
+              -- COMPONENT sig_reader IS
-                GENERIC(
+              --   GENERIC(
-                    FNAME       : STRING  := "input.txt";
+              --       FNAME       : STRING  := "input.txt";
-                    WIDTH       : INTEGER := 1;
+              --       WIDTH       : INTEGER := 1;
-                    RESOLUTION  : INTEGER := 8;
+              --       RESOLUTION  : INTEGER := 8;
-                    GAIN        : REAL    := 1.0
+              --       GAIN        : REAL    := 1.0
-                );
+              --   );
-                PORT(
+              --   PORT(
-                    clk             : IN std_logic;
+              --       clk             : IN std_logic;
-                    end_of_simu     : out std_logic;
+              --       end_of_simu     : out std_logic;
-                    out_signal      : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
+              --       out_signal      : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
-                );
+              --   );
-              END COMPONENT;
+              -- END COMPONENT;
               FILE input     : TEXT OPEN read_mode IS "input.txt";

lib/lpp/lpp_sim/lpp_sim_pkg.vhd +16 -1

             LIBRARY techmap;
             USE techmap.gencomp.ALL;
+            LIBRARY lpp;
+            USE lpp.data_type_pkg.ALL;
             PACKAGE lpp_sim_pkg IS
               PROCEDURE UART_INIT (
                 DATA      : OUT  STD_LOGIC_VECTOR
                 );
+              COMPONENT sig_reader IS
+                GENERIC(
+                  FNAME       : STRING  := "input.txt";
+                  WIDTH       : INTEGER := 1;
+                  RESOLUTION  : INTEGER := 8;
+                  GAIN        : REAL    := 1.0
+                );
+                PORT(
+                  clk             : IN std_logic;
+                  end_of_simu     : out std_logic;
+                  out_signal      : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
+                );
+              END COMPONENT;
             END lpp_sim_pkg;
             PACKAGE BODY lpp_sim_pkg IS

lib/lpp/lpp_sim/vhdlsim.txt +1 -1

+            sig_reader.vhd
             lpp_sim_pkg.vhd
             lpp_lfr_sim_pkg.vhd

designs/Validation_IIR_f0_LFR/generator.vhd removed 0 -74

NO CONTENT: file was removed

designs/Validation_IIR_f0_LFR/sig_reader.vhd removed 0 -53

NO CONTENT: file was removed

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