@@ -0,0 +1,53 | |||
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1 | LIBRARY ieee; | |
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2 | USE ieee.std_logic_1164.ALL; | |
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3 | USE ieee.numeric_std.ALL; | |
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4 | ||
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5 | LIBRARY std; | |
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6 | USE std.textio.ALL; | |
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7 | ||
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8 | LIBRARY lpp; | |
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9 | USE lpp.data_type_pkg.ALL; | |
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10 | ||
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11 | ENTITY sig_reader IS | |
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12 | GENERIC( | |
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13 | FNAME : STRING := "input.txt"; | |
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14 | WIDTH : INTEGER := 1; | |
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15 | RESOLUTION : INTEGER := 8; | |
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16 | GAIN : REAL := 1.0 | |
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17 | ); | |
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18 | PORT( | |
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19 | clk : IN std_logic; | |
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20 | end_of_simu : out std_logic; | |
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21 | out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0) | |
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22 | ); | |
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23 | END sig_reader; | |
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24 | ||
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25 | ARCHITECTURE beh OF sig_reader IS | |
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26 | FILE input_file : TEXT OPEN read_mode IS FNAME; | |
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27 | SIGNAL out_signal_reg : sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0):=(others=>(others=>'0')); | |
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28 | SIGNAL end_of_simu_reg : std_logic:='0'; | |
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29 | BEGIN | |
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30 | out_signal <= out_signal_reg; | |
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31 | end_of_simu <= end_of_simu_reg; | |
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32 | PROCESS | |
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33 | VARIABLE line_var : LINE; | |
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34 | VARIABLE value : INTEGER; | |
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35 | VARIABLE cell : STD_LOGIC_VECTOR(RESOLUTION-1 downto 0); | |
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36 | BEGIN | |
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37 | WAIT UNTIL clk = '1'; | |
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38 | IF endfile(input_file) THEN | |
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39 | end_of_simu_reg <= '1'; | |
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40 | ELSE | |
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41 | end_of_simu_reg <= '0'; | |
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42 | readline(input_file,line_var); | |
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43 | FOR COL IN 0 TO WIDTH-1 LOOP | |
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44 | read(line_var, value); | |
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45 | cell := std_logic_vector(to_signed(INTEGER(GAIN*REAL(value)) , RESOLUTION)); | |
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46 | FOR bit_idx IN RESOLUTION-1 downto 0 LOOP | |
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47 | out_signal_reg(COL,bit_idx) <= cell(bit_idx); | |
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48 | END LOOP; | |
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49 | END LOOP; | |
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50 | END IF; | |
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51 | END PROCESS; | |
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52 | ||
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53 | END beh; |
@@ -12,8 +12,8 EFFORT=high | |||
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12 | 12 | XSTOPT= |
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13 | 13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" |
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14 | 14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd |
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15 |
VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd |
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16 |
VHDLSIMFILES= tb.vhd |
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15 | VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd | |
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16 | VHDLSIMFILES= tb.vhd | |
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17 | 17 | SIMTOP=testbench |
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18 | 18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc |
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19 | 19 | PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc |
@@ -35,7 +35,6 DIRSKIP = b1553 pcif leon2 leon3v3 leon2 | |||
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35 | 35 | ./general_purpose/lpp_delay \ |
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36 | 36 | ./lpp_bootloader \ |
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37 | 37 | ./lfr_management \ |
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38 | ./lpp_sim \ | |
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39 | 38 | ./lpp_sim/CY7C1061DV33 \ |
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40 | 39 | ./lpp_cna \ |
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41 | 40 | ./lpp_uart \ |
@@ -52,7 +51,8 FILESKIP = i2cmst.vhd \ | |||
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52 | 51 | lpp_lfr_ms_FFT.vhd \ |
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53 | 52 | lpp_lfr_apbreg.vhd \ |
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54 | 53 | CoreFFT.vhd \ |
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55 | lpp_lfr_ms.vhd | |
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54 | lpp_lfr_ms.vhd \ | |
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55 | lpp_lfr_sim_pkg.vhd | |
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56 | 56 | |
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57 | 57 | include $(GRLIB)/bin/Makefile |
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58 | 58 | include $(GRLIB)/software/leon3/Makefile |
@@ -20,6 +20,7 USE lpp.general_purpose.ALL; | |||
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20 | 20 | USE lpp.data_type_pkg.ALL; |
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21 | 21 | USE lpp.lpp_lfr_pkg.ALL; |
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22 | 22 | USE lpp.general_purpose.ALL; |
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23 | USE lpp.lpp_sim_pkg.ALL; | |
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23 | 24 | |
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24 | 25 | ENTITY testbench IS |
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25 | 26 | GENERIC( |
@@ -75,19 +76,19 ARCHITECTURE behav OF testbench IS | |||
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75 | 76 | ); |
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76 | 77 | END COMPONENT; |
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77 | 78 | |
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78 | COMPONENT sig_reader IS | |
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79 | GENERIC( | |
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80 |
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81 | WIDTH : INTEGER := 1; | |
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82 |
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83 | GAIN : REAL := 1.0 | |
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84 | ); | |
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85 | PORT( | |
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86 | clk : IN std_logic; | |
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87 | end_of_simu : out std_logic; | |
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88 | out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0) | |
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89 | ); | |
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90 | END COMPONENT; | |
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79 | -- COMPONENT sig_reader IS | |
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80 | -- GENERIC( | |
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81 | -- FNAME : STRING := "input.txt"; | |
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82 | -- WIDTH : INTEGER := 1; | |
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83 | -- RESOLUTION : INTEGER := 8; | |
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84 | -- GAIN : REAL := 1.0 | |
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85 | -- ); | |
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86 | -- PORT( | |
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87 | -- clk : IN std_logic; | |
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88 | -- end_of_simu : out std_logic; | |
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89 | -- out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0) | |
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90 | -- ); | |
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91 | -- END COMPONENT; | |
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91 | 92 | |
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92 | 93 | |
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93 | 94 | FILE input : TEXT OPEN read_mode IS "input.txt"; |
@@ -32,6 +32,9 USE gaisler.jtagtst.ALL; | |||
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32 | 32 | LIBRARY techmap; |
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33 | 33 | USE techmap.gencomp.ALL; |
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34 | 34 | |
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35 | LIBRARY lpp; | |
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36 | USE lpp.data_type_pkg.ALL; | |
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37 | ||
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35 | 38 | PACKAGE lpp_sim_pkg IS |
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36 | 39 | |
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37 | 40 | PROCEDURE UART_INIT ( |
@@ -58,7 +61,19 PACKAGE lpp_sim_pkg IS | |||
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58 | 61 | DATA : OUT STD_LOGIC_VECTOR |
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59 | 62 | ); |
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60 | 63 | |
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61 | ||
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64 | COMPONENT sig_reader IS | |
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65 | GENERIC( | |
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66 | FNAME : STRING := "input.txt"; | |
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67 | WIDTH : INTEGER := 1; | |
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68 | RESOLUTION : INTEGER := 8; | |
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69 | GAIN : REAL := 1.0 | |
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70 | ); | |
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71 | PORT( | |
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72 | clk : IN std_logic; | |
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73 | end_of_simu : out std_logic; | |
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74 | out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0) | |
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75 | ); | |
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76 | END COMPONENT; | |
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62 | 77 | END lpp_sim_pkg; |
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63 | 78 | |
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64 | 79 | PACKAGE BODY lpp_sim_pkg IS |
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1 | NO CONTENT: file was removed |
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1 | NO CONTENT: file was removed |
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